B. P.

Poddar Institute of Management & Technology

Meggitt Decoder
Presented by
Group-13
Anjali Jain (11500318111)
Anjali Gupta (11500318112)
Ananya Sil (11500318113)
Aliva Biswas (11500318114)
Introduction
Cyclic code is a subclass of linear codes. Any cyclic shift of a code word
results in another valid code.
There are three basic steps to decode a cyclic code: (i) syndrome
computation, (ii) obtaining error pattern, and (iii) error correction.
Meggitt decoder is applicable to any cyclic code. Its performance
depends on the error-pattern detection circuit. Meggitt decoder can
also be designed with the detection and correction from leftmost digit.
Problem Statement
Construct a Meggitt decoder, with input to the low-order side, for the
(15, 11) cyclic code with generator polynomial . If the decoder input
corresponds to a codeword polynomial that has incurred a single
error, determine

Solution:
Meggit Decoder Design :
(15,11) cyclic code, hence n = 15 and k = 11, n-k = 4 , No of Shift-registers required: 4
Generator Polynomial :
g(x) = =

G=[11001]
Block Diagram:

Working principle:
Generator polynomial g(x) = =
The systematic encoder is designed according to the generator polynomial. As a result we will get output of four
register bits S1, S2, S3 and S4. S1 being the LSB and S4 the MSB.
S1 = XOR of previous S4 bit and previous message signal bit.
S2 = XOR of previous S1 bit and previous S4 bit.
S3 = Previous bit of S2.
S4 = Previous bit of S3.
Initially the register bits are s1 = 0, S2 = 0, S3 =0 and S4 = 0
Input signal
U=[1011100]
 Table to show changes in stages :
Shift cycle m S1 S2 S3 S4
0 0 0 0 0 0
1 0 0 0 0 0
2 1 0 0 0 0
3 1 1 0 0 0
4 1 1 1 0 0
5 0 1 1 1 0
6 1 0 1 1 1
7 0 0 1 1 1 At signal cycle 26 we get the register bit as
8 0 1 1 1 1 [1000]
9 0 1 0 1 1
Which means there is an error at the input bit
10 0 1 0 0 1
11 0 1 0 0 0
11. So at the 26th clock cycle the value of
12 0 0 1 0 0 s1,s2,s3,s4 becomes [1 0 0 0] which indicates
13 0 0 0 1 0 the presence of error. Hence the ouput of the
14 0 0 0 0 1
coincidence gate becomes 1.
15 0 1 1 0 0
16 0 0 1 1 0
XOR operation between the 11th bit and the
17 0 0 0 1 1 output of the coincidence gate corrects the
18 0 1 1 0 1 error bit i.e, now the 11th bit value becomes 1
19 0 1 0 1 0
Hence,
20 0 0 1 0 1
21 0 1 1 1 0
resulting codeword = [ 1 0 0 0 1 0 1 1 1 0 0 ]
22 0 0 1 1 1
23 0 1 1 1 1
24 0 1 0 1 1
25 0 1 0 0 1
26 0 1 0 0 0
Verification:
For the input signal we correct the value at the 11th bit. Hence the resulting sequence
becomes
[10001011100]
Table to show changes in stages :
Shift cycle m S1 S2 S3 S4
0 0 0 0 0 0
1 0 0 0 0 0
2 1 0 0 0 0 We can observe that for the
3
4
1
1
1
1
0
1
0
0
0
0
message sequence [1 0 0 0 1 0 1 1
5 0 1 1 1 0 1 0 0 ] the output after the 10th
6 1 0 1 1 1 shift cycle is zero.
7 0 0 1 1 1
8 0 1 1 1 1

9 0 1 0 1 1
10 1 1 0 0 1 Hence, Codeword
11 0 0 0 0 0
12 0 0 0 0 0 C=[10001011100]
13 0 0 0 0 0
14 0 0 0 0 0 ( Hence Verified )
15 0 0 0 0 0
16 0 0 0 0 0
17 0 0 0 0 0
18 0 0 0 0 0
19 0 0 0 0 0
20 0 0 0 0 0
21 0 0 0 0 0
22 0 0 0 0 0
23 0 0 0 0 0
24 0 0 0 0 0
25 0 0 0 0 0
26 0 0 0 0 0
APPLICATIONS :
Internet - In a typical TCP/IP stack, error control is performed at multiple levels

Deep space telecommunications - As a spacecraft increases its distance from Earth, the
problem of correcting for noise becomes more difficult.

Satellite broadcasting - The demand for satellite transponder bandwidth continues to grow,
fueled by the desire to deliver television (including new channels and
high-definition television) and IP data. Transponder availability and bandwidth constraints
have limited this growth. Transponder capacity is determined by the selected modulation
scheme and the proportion of capacity consumed by FEC.

Data storage - Error detection and correction codes are often used to improve the reliability
of data storage media.

Error correcting memory - Dynamic random-access memory (DRAM) may provide stronger
protection against soft errors by relying on error-correcting codes. Such error-correcting
memory, known as ECC or EDAC-protected memory, is particularly desirable for mission-
critical applications, such as scientific computing, financial, medical, etc. as well as
extraterrestrial applications due to the increased radiation in space.
CONCLUSION

Cyclic code is a subclass of linear codes in which shifts reproduce codewords. If the
generator polynomial is provided, we can design a meggitt decoder which takes input of
the message signal and the resultant table that consists of the register bits signifies the
presence or absence of error. The number of shift registers in the decoder circuit is
determined by the value of n-k. After successfully implementing the decoder circuit and
the table we observed the pattern of the coincidence gate and determined the error bit
and thus obtained the resulting codeword. We can verify our codeword by giving the
message input as the resultant codeword to the decoder circuit and observe the values of
the register.

REFERENCES
[1]https://en.wikipedia.org/wiki/Cyclic_code#:~:text=In%20coding%20theory%2C%20a
%20cyclic,efficient%20error%20detection%20and%20correction.

[2] https://drive.google.com/file/d/1iDhcWJAZnbL14GWjn_x0-xZryG3tv1t4/view
Thank You