INPUT-OUTPUT ORGANIZATION

• Peripheral Devices

• Input-Output Interface

• Asynchronous Data Transfer

• Modes of Transfer

• Priority Interrupt

• Direct Memory Access

• Input-Output Processor

• Serial Communication
 Peripheral Devices

PERIPHERAL DEVICES
Input Devices Output Devices
• Keyboard • Card Puncher, Paper Tape Puncher
• Optical input devices • CRT
- Card Reader • Printer (Impact, Ink Jet,
- Paper Tape Reader Laser, Dot Matrix)
- Bar code reader • Plotter
- Digitizer • Analog
- Optical Mark Reader • Voice
• Magnetic Input Devices
- Magnetic Stripe Reader
• Screen Input Devices
- Touch Screen
- Light Pen
- Mouse
• Analog Input Devices
 Input/Output Interfaces

INPUT/OUTPUT INTERFACE

 Providesa method for transferring

information between internal storage (such
as memory and CPU registers) and external
I/O devices

 Resolves
the differences between the
computer and peripheral devices
DIFFERENCES IN CPU AND PERIPHERALS
 CPU and Memory are electronic in
nature while devices are
electromagnetic and
electromechanical.
 Difference in data transfer rate

 Data codes and formats are different

 The operating modes of peripheral are

different from each other.

INTERFACE
 To resolve these differences, computer
systems include special hardware
components between the CPU and peripheral
devices to supervise and synchronize all
input and output transfers.
 These components are known as interface

units.
 Each device may have a device controller.
 Input/Output Interfaces

I/O BUS AND INTERFACE MODULES

I/O bus
Data
Processor Address
Control

Interface Interface Interface Interface

Keyboard
and Printer Magnetic Magnetic
display disk tape
terminal

Each peripheral has an interface module associated with it

Interface
- Decodes the device address (device code)
- Decodes the commands (operation)
- Provides signals for the peripheral controller
- Synchronizes the data flow and supervises
the transfer rate between peripheral and CPU or Memory
Typical I/O instruction
Op. code Device address Function code
(Command)
 Each interface attached to the I/O bus has an
address decoder that monitors that address
lines.
 When the interface detects its own address,

it activates the path between the bus line

and the device that it controls.
 All peripherals whose address does not

corresponds to the address in the bus are

disabled by their interface.
I/ O COMMANDS
 At the same time when processor provides
address on address line it also generates
function codes on control lines.
 The function code is actually the instruction

that is executed in the interface and its

attached unit.
 There are four types of command

 (1) Control Command: What to DO??

 A magnetic tape may be instructed to rewind

the tape, to read

 (2) Status Command: test the various
conditions in the interface and
peripheral.
 Before the transmission

 During the transmission

 (3) Output data command: it causes the

interface to respond by transferring

data from the bus into one of its
register.
 (4) Input data Command: it causes the

interface to receive an item of data

from the peripherals and places it in its
buffer register.
CPU TO I/O
 Consider an example with a tape unit.
 The computer starts the tape moving by

issuing a control command.

 The processor then monitors the status of the

tape by means of a status command.

 When tape is in correct position, the

processor issues a data output command.

 The interface responds to the address and

command and transfer the information from

the data lines in the bus to its buffer register.
 The interface then communicates with the

tape controller and sends the data to be

stored on tape.
 Input/Output Interfaces

I/O BUS AND MEMORY BUS

Functions of Buses
* MEMORY BUS is for information transfers between CPU and the MM
• I/O BUS is for information transfers between CPU
and I/O devices through their I/O interface

Physical Organizations
* Many computers use a common single bus system
for both memory and I/O interface units
- Use one common bus but separate control lines for each
function
- Use one common bus with common control lines for both functions
* Some computer systems use two separate buses,
one to communicate with memory and the other with I/O interfaces

I/O Bus
- Communication between CPU and all interface units is via a common
I/O Bus
- An interface connected to a peripheral device may have a number of
data registers , a control register, and a status register
- A command is passed to the peripheral by sending
to the appropriate interface register
- Function code and sense lines are not needed (Transfer of data, control,
and status information is always via the common I/O Bus)
 Input/Output Interfaces

ISOLATED VS. MEMORY MAPPED I/O

Isolated I/O
- Separate I/O read/write control lines in addition to memory read/write
control lines
- Separate (isolated) memory and I/O address spaces
- Distinct input and output instructions

Memory-mapped I/O
- A single set of read/write control lines
(no distinction between memory and I/O transfer)
- Memory and I/O addresses share the common address space
-> reduces memory address range available
- No specific input or output instruction
-> The same memory reference instructions can
be used for I/O transfers
- Considerable flexibility in handling I/O operations
 Input/Output Interfaces

I/O INTERFACE
Port A I/O data
register
Bidirectional Bus
data bus buffers
Port B I/O data
register

Internal bus
CPU Chip select CS
I/O
Register select RS1 Control Control Device
Timing register
Register select RS0 and
I/O read Control
RD Status Status
I/O write WR register

CS RS1 RS0 Register selected

The interface registers 0 x x None - data bus in high-impedence
1 0 0 Port A register
communicates with the cpu 1 0 1 Port B register
through the bidirectional bus. 1 1 0 Control register
1 1 1 Status register

The address bus selects the

interface unit through the select
and the two register select inputs.
The two register select inputs RS1 and RS0 are used to select one of
the four register
 Asynchronous Data Transfer

ASYNCHRONOUS DATA TRANSFER

Synchronous and Asynchronous Operations
Synchronous - All devices derive the timing
information from common clock line
Asynchronous - No common clock

Asynchronous Data Transfer

Asynchronous data transfer between two independent units requires that
control signals be transmitted between the communicating units to
indicate the time at which data is being transmitted

Two Asynchronous Data Transfer Methods

Strobe pulse
- A strobe pulse is supplied by one unit to indicate
the other unit when the transfer has to occur

Handshaking
- A control signal is accompanied with each data
being transmitted to indicate the presence of data
- The receiving unit responds with another control
signal to acknowledge receipt of the data
STROBE CONTROL( SOURCE
INITIATED)
 Employs a single control line to time each
transfer
 The strobe may be activated by either the

source or the destination unit.

 The source unit first places the data on the

data bus, after a brief delay to ensure that

the data is settle to steady value, the source
activates the strobe pulse.
 The information on the data bus and the

strobe signal remains for a sufficient time.

 The source removes the data from the bus a

brief period after it disables its strobe pulse.

 Ex. Memory Write.
STROBE CONTROL( DESTINATION INITIATED)
 The Dest. Unit activates the strobe pulse
 The source unit respond by placing the data

on data bus.
 After accepting the data the Dest. Unit

disables the strobe.

 The source unit then removes the data from

data bus.
 ex. Memory read operation
 Asynchronous Data Transfer

STROBE CONTROL
*

Source-Initiated Strobe Destination-Initiated Strobe

for Data Transfer for Data Transfer

Block Diagram Block Diagram

Data bus Data bus
Source Destination Source Destination
unit Strobe unit unit Strobe unit

Timing Diagram Timing Diagram

Valid data Valid data
Data Data

Strobe Strobe
 Asynchronous Data Transfer

HANDSHAKING

Strobe Methods

Source-Initiated

The source unit that initiates the transfer has

no way of knowing whether the destination unit
has actually received data

Destination-Initiated

The destination unit that initiates the transfer

no way of knowing whether the source has
actually placed the data on the bus

To solve this problem, the HANDSHAKE method

introduces a second control signal to provide a Reply
to the unit that initiates the transfer
 Asynchronous Data Transfer

SOURCE-INITIATED TRANSFER USING HANDSHAKE

Data bus
Source Data valid Destination
Block Diagram unit Data accepted unit

Valid data
Data bus
Timing Diagram

Data valid

Data accepted

Sequence of Events Source unit Destination unit

Place data on bus.
Enable data valid.
Accept data from bus.
Enable data accepted
Disable data valid.
Invalidate data on bus.
Disable data accepted.
Ready to accept data
(initial state).
* Allows arbitrary delays from one state to the next
* Permits each unit to respond at its own data transfer rate
* The rate of transfer is determined by the slower unit
 Asynchronous Data Transfer

DESTINATION-INITIATED TRANSFER USING HANDSHAKE

Data bus
Block Diagram Source Data valid Destination
unit Ready for data unit

Timing Diagram Ready for data

Data valid

Valid data
Data bus

Sequence of Events Source unit Destination unit

Ready to accept data.
Place data on bus. Enable ready for data.
Enable data valid.

Accept data from bus.

Disable data valid. Disable ready for data.
Invalidate data on bus
(initial state).

* Handshaking provides a high degree of flexibility and reliability because the

successful completion of a data transfer relies on active participation by both units
* If one unit is faulty, data transfer will not be completed
-> Can be detected by means of a timeout mechanism
 Asynchronous Data Transfer

ASYNCHRONOUS SERIAL TRANSFER

Asynchronous serial transfer
Four Different Types of Transfer Synchronous serial transfer
Asynchronous parallel transfer
Synchronous parallel transfer
Asynchronous Serial Transfer
- Employs special bits which are inserted at both
ends of the character code
- Each character consists of three parts; Start bit; Data bits; Stop bits.

1 1 0 0 0 1 0 1
Start Character bits Stop
bit bits
(1 bit) (at least 1 bit)

A character can be detected by the receiver from the knowledge of 4 rules;

- When data are not being sent, the line is kept in the 1-state (idle state)
- The initiation of a character transmission is detected
by a Start Bit , which is always a 0
- The character bits always follow the Start Bit
- After the last character , a Stop Bit is detected when
the line returns to the 1-state for at least 1 bit time
The receiver knows in advance the transfer rate of the
bits and the number of information bits to expect
ASYNCHRONOUS SERIAL TRANSFER
 At the end of the character the line is held at
the 1 state for a period of at least one or two
bit times so that both devices can
resynchronize.
 Assume that a terminal transfers 10 char per

second.
 Each character has 11 bits

 1 start

 8 data

 2 stop

 So baud rate:-- rate at which serial

information is transmitted in bits per second.

 110 baud rate
MODES OF TRANSFER
 Data transfer between the CPU and the
external devices may be handled in a variety
of modes.
 Some modes use the CPU as an intermediate

path and others transfer the data directly to

and from memory unit.
 Data transfer to and from the external

devices may be handled in one of three

possible modes:
 (1) programmed I/O

 (2) Interrupt-initiated I/O

 (3) Direct memory Access( DMA)

PROGRAMMED I/O

 Usually the transfer is to and from a CPU

register and peripheral.
 Other instruction are needed to transfer the

data to and from CPU and memory.

 Here the I/O device does not have a direct

access to memory.
 The transfer operation between CPU and I/O

requires
 Input device to CPU

 Store CPU to memory

 Modes of Transfer

PROGRAM-CONTROLLED I/O -
Program-Controlled I/O(Input Dev to CPU)

Data bus Interface I/O bus

Address bus Data register
Data valid I/O
CPU I/O read device
I/O write Status Data accepted
register F

Read status register

Check flag bit

=0 Polling or Status Checking

flag
=1 • Continuous CPU involvement
• CPU slowed down to I/O speed
Read data register
Transfer data to memory • Simple
• Least hardware
no Operation
complete?
yes
Continue with
program
PROGRAMMED I/O
 The device transfer bytes of data one at a time.
 When a byte of data is available, the device places it on the i/o bus
and enables the data valid lines.
 The interface accepts the byte into its data register and enables the
data accepted line.
 The interface sets a bit in status register refer to as an F (flag bit)
bit.
 The device now disables the data valid line.
 But will not perform next transfer until the data accepted line is
disabled by interface.
 CPU reads the status register and checks the flag bit. If it is 1 the
CPU reads the data register
 The flag bit is cleared to 0.
 Now the interface disables the data accepted line.
 Each byte is read into a CPU register and then transferred to
memory with a store instruction.
 Here CPU continuously monitors the status register which keeps it
busy.
 It can be avoided using an interrupt facility.
INTERRUPT INITIATED I/O
 This mode of transfer uses the interrupt
facility.
 While the CPU is running a program, it does

not check the flag.

 However when the flag is set the CPU is

interrupted from proceeding the current

program.
 It deviates from what it is doing to take care

of I/O transfer.
 After the transfer is completed the computer

returns to previous program and continues.

INTERRUPT INITIATED I/O

CPU
Program
101
102 Service routine
103
I/O interrupt

104 104

stack

CPU responds to the interrupt signal by storing the return address from the PC
into a memory stack and then control branches to a service routine that
process the required I/O transfer.
Vectored interrupt The source that interrupts supplies the branch information
Non vectored interrupt  the branch address is assigned to fixed location in
memory.
PRIORITY INTERRUPT
 A priority interrupt is a system that establishes a
priority over the various sources to determine
which condition is to be serviced first.
 Higher priority interrupt level are assigned to

request which if delayed could have serious

consequences.
 When two devices interrupt the computer at the

same time the computer services the device with

the higher priority first.
 Establishing the priority of interrupts can be done

by software or hardware.
POLLING
 In this method there is one common branch
address for all interrupts. The program that
handles the interrupt polls the interrupt sources in
sequences.
 The order in which they are tested determines

their priority.
 The highest priority source is tested first, if its

interrupt signal is on, control branches to a

service routine for this source.
 Otherwise next lower priority source is tested.

 The disadvantage is that if there are many

interrupts the time required to poll them can

exceed the time available to service the I/O.
HARDWARE PRIORITY INTERRUPTS
 (1) daisy Chaining Priority
 The device with highest priority is placed in the

first position.
 The interrupt request line is common to all

devices.
 When no interrupts are pending the interrupt line

stays in high level state.

 The CPU responds to the interrupt by enabling the

interrupt acknowledge line.

 Priority Interrupt

HARDWARE PRIORITY INTERRUPT - DAISY-CHAIN -

Processor data bus
VAD 1 VAD 2 VAD 3 * Serial hardware priority function
Device 1 Device 2 Device 3 * Interrupt Request Line
To next
PI PO PI PO PI PO
device
- Single common line
* Interrupt Acknowledge Line
- Daisy-Chain
Interrupt request INT
CPU
Interrupt acknowledge
INTACK

Interrupt Request from any device(>=1)

-> CPU responds by INTACK <- 1
-> Any device receives signal(INTACK) 1 at PI puts the VAD on the bus
Among interrupt requesting devices the only device which is physically closest
to CPU gets INTACK=1, and it blocks INTACK to propagate to the next device
One stage of the daisy chain priority arrangement
Priority in VAD
PI Enable
Vector address
Interrupt Priority out PI RF PO Enable
RF PO 0 0 0 0
request S Q
from device 0 1 0 0
R 1 0 1 0
1 1 0 1
Delay

Interrupt request to CPU

 Priority Interrupt

PARALLEL PRIORITY INTERRUPT

Interrupt register Bus
Buffer
Disk 0 I0 y
Printer 1 I1 x
Priority 0
Reader 2 I 2 encoder
0 VAD
Keyboard 3 0 to CPU
I3
0
0
0 IEN IST
0
Mask
register 1 Enable

2
Interrupt
to CPU
3
INTACK
from CPU
IEN: Set or Clear by instructions ION or IOF
IST: Represents an unmasked interrupt has occurred. INTACK enables
tristate Bus Buffer to load VAD generated by the Priority Logic
Interrupt Register:
- Each bit is associated with an Interrupt Request from
different Interrupt Source - different priority level
- Each bit can be cleared by a program instruction
Mask Register:
- Mask Register is associated with Interrupt Register
- Each bit can be set or cleared by an Instruction
PARALLEL PRIORITY INTERRUPT
 Each interrupt bit and its corresponding mask bit are applied
to an AND gate to produce the four inputs to a priority
encoder.
 The priority encoder generates two bits of the vector
address which is transferred to the CPU.
 IST (interrupt status flip flop)is enabled when an interrupt
occurs.
 IEN (Interrupt enable flip flop) can be set or cleared to
provide an over-all control over the interrupt system.
 The outputs of IST ANDed with IEN provide a common
interrupt signal for the CPU.
 The INTACK signal from the CPU places the VAD onto the
data bus.
 Priority Interrupt

INTERRUPT PRIORITY ENCODER

Determines the highest priority interrupt when

more than one interrupts take place

Priority Encoder Truth table

Inputs Outputs
I0 I1 I2 I3 x y IST Boolean functions
1 d d d 0 0 1
0 1 d d 0 1 1
0 0 1 d 1 0 1 x = I 0' I 1'
0 0 0 1 1 1 1 y = I 0' I 1 + I 0’ I 2’
0 0 0 0 d d 0 (IST) = I0 + I1 + I2 + I3

The logic of the priority encoder is such that if two or more inputs arrive at the
same time, the input having the highest priority will take precedence.
IST is set only when one or more inputs are equal to 1.
If all inputs are 0, the IST is cleared to 0, and no Vector address will be
transferred on to the bus.
 Priority Interrupt

INTERRUPT CYCLE
At the end of each Instruction cycle
- CPU checks IEN and IST
- If IEN  IST = 1, CPU -> Interrupt Cycle

SP SP - 1 Decrement stack pointer

M[SP]  PC Push PC into stack
INTACK  1 Enable interrupt acknowledge
PC  VAD Transfer vector address to PC
IEN  0 Disable further interrupts
Go To Fetch to execute the first instruction
in the interrupt service routine
 Priority Interrupt

INTERRUPT SERVICE ROUTINE

address Memory I/O service programs
7
0 JMP DISK DISK Program to service
1 JMP PTR magnetic disk
VAD=00000011 3
2 JMP RDR PTR Program to service
3 JMP KBD line printer
8
1 Main program RDR
KBD Program to service
749 current instr.
interrupt 750 character reader
4
KBD Program to service
Stack
11 keyboard
5
2 255
256 Disk 256
750 interrupt
6 9 10
Initial and Final Operations
Each interrupt service routine must have an initial and final set of
operations for controlling the registers in the hardware interrupt system

Initial Sequence Final Sequence

[1] Clear lower level Mask reg. bits [1] IEN <- 0
[2] IST <- 0 [2] Restore CPU registers
[3] Save contents of CPU registers [3] Clear the bit in the Interrupt Reg
[4] IEN <- 1 [4] Set lower level Mask reg. bits
[5] Go to Interrupt Service Routine [5] Restore return address, IEN <- 1
DIRECT MEMORY ACCESS
 DMA is a technique in which memory and peripheral devices
communicate directly.
 The CPU is placed in idle state by disabling the buses through
special signals.
 The BR ( bus request) input is used by DMA controller to request the
CPU to relinquish the control over the buses.
 The CPU activates the BG ( Bus grant signal)to inform the DMA can
now take over the buses.
 Now the DMA can directly communicate with memory.
 Burst transfer a block sequence consisting of a number of memory
words is transferred.
 Cycle Stealing it allows the DMA controller to transfer one data
word at a time after which it must return control of the buses to
CPU. CPU delays its operation for memory cycle.
 Direct Memory Access

DIRECT MEMORY ACCESS

* Block of data transfer from high speed devices, Drum, Disk, Tape
* DMA controller - Interface which allows I/O transfer directly between
Memory and Device, freeing CPU for other tasks
* CPU initializes DMA Controller by sending memory
address and the block size(number of words)
CPU bus signals for DMA transfer


ABUS Address bus High-impedence
Bus request BR DBUS Data bus (disabled)
CPU when BG is
Bus granted BG RD Read
WR Write enabled

Block diagram of DMA controller

Address bus

Data bus Data bus Address bus

buffers buffers

Internal Bus
DMA select DS Address register
Register select RS
Read RD Word count register
Write WR Control
logic
Bus request BR Control register

Bus grant BG
Interrupt Interrupt DMA request
DMA acknowledge to I/O device
DMA CONTROLLER
 It needs the usual circuit of an interface.
 In addition it needs an address register, a

word count register and a set of address

lines.
 The unit communicates with the CPU through

the data bus and control lines.

 The registers in DMA are selected by DS and

RS.
 When BG=0 the CPU can communicate with

the with the DMA registers

 When BG=1 the CPU relinquishes the buses

and DMA can communicate with the memory.

 The DMA communicates with the devices

through the request and acknowledge lines.

 Direct Memory Access

DMA I/O OPERATION

Starting an I/O
- CPU executes instruction to
Load Memory Address Register
Load Word Counter
Load Function(Read or Write) to be performed
Issue a GO command or a control to start DMA

Upon receiving a GO Command DMA performs I/O

operation as follows independently from CPU

DMA Transfer
When device sends a request the DMA controller activates the BR lines
CPU responds with its BG lines.
DMA then puts the current value of its address register into address bus
and initiates the RD or WR signals.
And sends a DMA acknowledge to the peripheral devices
When device receives an acknowledge, it puts the word on data busor
receives from data bus.
DMA increments its address register and decrements its word count
register.
If word count reaches to zero the stops any transfer and relinquishes the
buses.
 Direct Memory Access

CYCLE STEALING
While DMA I/O takes place, CPU is also executing instructions

DMA Controller and CPU both access Memory -> Memory Access Conflict

Memory Bus Controller

- Coordinating the activities of all devices requesting memory access

- Priority System

Memory accesses by CPU and DMA Controller are interwoven,

with the top priority given to DMA Controller
-> Cycle Stealing

Cycle Steal

- CPU is usually much faster than I/O(DMA), thus

CPU uses the most of the memory cycles
- DMA Controller steals the memory cycles from CPU
- For those stolen cycles, CPU remains idle
- For those slow CPU, DMA Controller may steal most of the memory
cycles which may cause CPU remain idle long time
 Direct Memory Access

DMA TRANSFER
Interrupt
Random-access
BG
CPU memory unit (RAM)
BR
RD WR Addr Data RD WR Addr Data
Read control
Write control
Data bus
Address bus

Address
select

RD WR Addr Data
DS DMA ack.

RS DMA I/O
Controller Peripheral
BR device
BG DMA request
Interrupt