Course – Computer Organization and

Architecture

Course Instructor
Dr. Umadevi V
Department of CSE, BMSCE

1
January 21, 2025 CSE, BMSCE
 Unit-1

Basic Structure of Computers and Instruction Set

Architecture: Functional Units, Basic Operational Concepts, Number
Representation and Arithmetic Operations , Memory Locations and Addresses,
Memory Operations, Instructions and Instruction Sequencing, Addressing Modes,
Assembly Language

January 21, 2025 CSE, BMSCE 2

A Computer

Computer is a “machine”
As long as power is supplied, processor keeps executing
instructions
 Stored program model
 Sequential order of execution
Memory: Program and data storage

January 21, 2025 CSE, BMSCE 3

Functional Units
A computer consists of 5 functionally independent main parts: 1) Input 2) Memory 3)
ALU (Arithmetic and Logic Unit) 4) Output and 5) Control unit

Basic functional units of a computer

January 21, 2025 CSE, BMSCE 4
Functional Units
1. Input Unit: Computer accepts encoded information through input unit. The standard input
device is a keyboard. Whenever a key is pressed, keyboard controller sends the code to
CPU/Memory.
Examples include Keyborad, Mouse, Joystick, Tracker ball, Light pen, Digitizer, Scanner etc.

2. Output Unit: Computer after computation returns the computed results, error messages,
etc. via output unit. The standard output device is a video monitor, LCD/TFT monitor. Other
output devices are printers, plotters etc.

January 21, 2025 CSE, BMSCE 5

Functional Units
3. Memory Unit: Memory unit stores the program instructions (Code), data and results
of computations etc. Memory unit is classified as:
• Primary /Main Memory
• Secondary /Auxiliary Memory

Primary memory is a semiconductor memory that provides access at high speed. Run time program instructions and operands
are stored in the main memory. Main memory is classified again as ROM and RAM. ROM holds system programs and firmware
routines such as BIOS, POST, I/O Drivers that are essential to manage the hardware of a computer. RAM is termed as Read/Write
memory or user memory that holds run time program instruction and data. While primary storage is essential, it is volatile in
nature and expensive. Additional requirement of memory could be supplied as auxiliary memory at cheaper cost. Secondary
memories are non volatile in nature.

January 21, 2025 CSE, BMSCE 6

Functional Units
4. Arithmetic and logic unit: ALU consist of necessary logic circuits like adder, comparator etc., to perform
operations of addition, multiplication, comparison of two numbers etc.
5. Control Unit: Control unit co-ordinates activities of all units by issuing control signals. Control signals issued
by control unit govern the data transfers and then appropriate operations take place. Control unit interprets or
decides the operation/action to be performed.

The control Unit and the Arithmetic and Logic unit of a computer system are jointly known as the Central
Processing Unit (CPU).

Processor Control Unit

January 21, 2025 CSE, BMSCE 7

 Next we will learn

Unit 1: Basic Operational Concepts

January 21, 2025 CSE, BMSCE 8

Background information to understand “Basic Operational Concepts”

High Level Language (HLL) Assembly Level Language (ALL)

Program P.c Program T.asm
N Instructions
#include <stdio.h> .
main() .
{ .
. Load R2, A
. Load R3, B
C=A+B; Add R4, R2, R3
. Store R4, C
. .
} .
A, B, and C, are labels
representing memory word
addresses
Ri are processor registers

January 21, 2025 CSE, BMSCE 9

Background information to understand “Basic Operational Concepts”

Program consists of
Basic Step1
N Instructions Instruction
Basic
. Step2
Instruction 1
.
Instruction 2 . Operation Operand
Basic Step m Or
.
. Opcode
.
. Register Memory
.
Instruction N.

January 21, 2025 CSE, BMSCE 10

Background information to understand “Basic Operational Concepts”: Instruction types

Three basic instruction types:

 Load - Read a data operand from memory or an input device into the processor
 Store - Write a data operand from a processor register to memory or an output
device
 Operate - Perform an arithmetic or logic operation on data operands in processor
registers

January 21, 2025 CSE, BMSCE 11

 BASIC OPERATIONAL CONCEPTS
- The Program Counter (PC) register holds the
memory address of the current instruction
- The Instruction Register (IR) holds the current
instruction
- General-purpose registers hold data and
addresses (R0, R1, ….)
- Control circuits and the Arithmetic and Logic
Unit (ALU) fetch and execute instructions

Connection Between the Processor and the Main Memory

January 21, 2025 CSE, BMSCE 12

BASIC OPERATIONAL CONCEPTS:
Fetching and executing instructions

Example: Load R2, LOC

The processor control circuits do the following:

 Send address in PC to memory; issue Read
 Load instruction from memory into IR
 Increment PC to point to next instruction
 Send address LOC to memory; issue Read
 Load word from memory into register R2

January 21, 2025 CSE, BMSCE 13

 BASIC OPERATIONAL CONCEPTS: Fetching and executing instructions : Illustration with
example
Memory
Basic Steps to execute the instruction Load R2, A Address Instructions / Data
1. Send address in PC to memory; issue Read
2. Load instruction from memory into IR 100 Load R2, A
3. Increment PC to point to next instruction 101 Load R3, B
4. Send address A to memory; issue Read
5. Load word from memory into register R2 102 Add R4, R2, R3

….. -----
Memory Address 200 76
Label A

PC 100 R2

IR

Processor

January 21, 2025 CSE, BMSCE 14

 BASIC OPERATIONAL CONCEPTS: Fetching and executing instructions : Illustration with
example
Memory
Basic Steps to execute the instruction Load R2, A: Address
1. Send address in PC to memory; issue Read
2. Load instruction from memory into IR 100 Load R2, A
3. Increment PC to point to next instruction 101 Load R3, B
4. Send address A to memory; issue Read
5. Load word from memory into register R2 102 Add R4, R2, R3

….. -----
Memory Address 200 76
Label A

PC 100 R2

IR

Processor

January 21, 2025 CSE, BMSCE 15

 BASIC OPERATIONAL CONCEPTS: Fetching and executing instructions : Illustration with
example
Memory
Basic Steps to execute the instruction Load R2, A: Address
1. Send address in PC to memory; issue Read
2. Load instruction from memory into IR 100 Load R2, A
3. Increment PC to point to next instruction 101 Load R3, B
4. Send address A to memory; issue Read
5. Load word from memory into register R2 102 Add R4, R2, R3

….. -----
Memory Address 200 76
Label A

PC 100 R2

IR Load R2, A

January 21, 2025 CSE, BMSCE 16

 BASIC OPERATIONAL CONCEPTS: Fetching and executing instructions : Illustration with
example
Memory
Basic Steps to execute the instruction Load R2, A: Address
1. Send address in PC to memory; issue Read
2. Load instruction from memory into IR 100 Load R2, A
3. Increment PC to point to next instruction 101 Load R3, B
4. Send address A to memory; issue Read
5. Load word from memory into register R2 102 Add R4, R2, R3

….. -----
Memory Address 200 76
Label A

PC 101 R2

IR Load R2, A

January 21, 2025 CSE, BMSCE 17

 BASIC OPERATIONAL CONCEPTS: Fetching and executing instructions : Illustration with
example
Memory
Basic Steps to execute the instruction Load R2, A: Address
1. Send address in PC to memory; issue Read
2. Load instruction from memory into IR 100 Load R2, A
3. Increment PC to point to next instruction 101 Load R3, B
4. Send address A to memory; issue Read
5. Load word from memory into register R2 102 Add R4, R2, R3

….. -----

Memory Address 200 76

Label A

PC 101 R2

IR Load R2, A

January 21, 2025 CSE, BMSCE 18

 BASIC OPERATIONAL CONCEPTS: Fetching and executing instructions : Illustration with
example
Memory
Basic Steps to execute the instruction Load R2, A: Address
1. Send address in PC to memory; issue Read
2. Load instruction from memory into IR 100 Load R2, A
3. Increment PC to point to next instruction 101 Load R3, B
4. Send address A to memory; issue Read
5. Load word from memory into register R2 102 Add R4, R2, R3

….. -----

Memory Address 200 76

Label A

PC 101 R2 76

IR Load R2, A

January 21, 2025 CSE, BMSCE 19

 BASIC OPERATIONAL CONCEPTS:
Fetching and executing instructions
Memory
Basic Steps to execute the instruction Load R2, A: Address
1. Send address in PC to memory; issue Read
2. Load instruction from memory into IR 100 Load R2, A
3. Increment PC to point to next instruction 101 Load R3, B
4. Send address A to memory; issue Read
5. Load word from memory into register R2 102 Add R4, R2, R3

….. -----
Memory Address 200 76
Label A

100 R2 76
PC

IR Load R2, A

Processor

January 21, 2025 CSE, BMSCE 20

Test Your Knowledge
W.r.t Computer Processor,
What is the role of PC ?
What is the role of IR ?

January 21, 2025 CSE, BMSCE 21

Test Your Knowledge
What is the role of PC ?
The Central Processing Unit (CPU) contains a register called the Program Counter (PC), which
holds the address of instruction to be executed next.. to begin the execution of the program the
address of its First instruction must be placed into the PC.
What is the role of IR ?
The instruction register (IR) is used to hold the instruction that is currently being executed.
The contents of IR are available to the control unit, which generate the timing signals that
control the various processing elements involved in executing the instruction.

January 21, 2025 CSE, BMSCE 22

BASIC OPERATIONAL CONCEPTS:
Fetching and executing instructions

Example: Store LOC, R4

The processor control circuits do the following:

 Send address in PC to memory; issue Read
 Load instruction from memory into IR
 Increment PC to point to next instruction
 Send address LOC to memory; issue Write
 Store the word from register R4 into LOC

January 21, 2025 CSE, BMSCE 23

BASIC OPERATIONAL CONCEPTS:
Fetching and executing instructions

Example: Add R4, R2, R3

The processor control circuits do the following:

 Send address in PC to memory; issue Read
 Load instruction from memory into IR
 Increment PC to point to next instruction
 Add the content of Register R2 and the contents of register R3.
 Store the result (sum) in R4.

January 21, 2025 CSE, BMSCE 24

Question
(a) Give a short sequence of machine instructions for the task “Add the contents of memory-location A to those of location B,
and place the answer in location C”. Instructions:
Load Ri , LOC
and
Store LOC , Ri
are the only instructions available to transfer data between memory and the general purpose registers. Add instructions of type
ADD LOCA, R0 and Add R1, R0 are available. Do not change contents of either location A or B.
(b) Suppose that Move and Add instructions are available with the formats:
Move Location1, Location2
and
Add Location1, Location2
These instructions move or add a copy of the operand at the second location to the first location, overwriting the original
operand at the first location. Either or both of the operands can be in the memory or the general-purpose registers.
Is it possible to use fewer instructions of these types to accomplish the task in part (a)? If yes, give the sequence.

January 21, 2025 CSE, BMSCE 25

Answer
(a) Give a short sequence of machine instructions for the task “Add the contents of memory-location A to those of location B,
and place the answer in location C”. Instructions:
Load Ri , LOC
and
Store LOC , Ri
are the only instructions available to transfer data between memory and the general purpose registers. Add instructions of type
ADD LOCA, R0 and Add R1, R0 are available. Do not change contents of either location A or B.

January 21, 2025 CSE, BMSCE 26

Answer
(a) Give a short sequence of machine instructions for the task “Add the contents of memory-location A to those of location B,
and place the answer in location C”. Instructions:
Load Ri , LOC
and
Store LOC , Ri
are the only instructions available to transfer data between memory and the general purpose registers. Add instructions of type
ADD LOCA, R0 and Add R1, R0 are available. Do not change contents of either location A or B.

Solution:
(a)
Load R0 , A
Load R1 , B
Add R1, R0
Store C , R1

January 21, 2025 CSE, BMSCE 27

Answer
(b) Suppose that Move and Add instructions are available with the formats:
Move Location1, Location2
and
Add Location1, Location2
These instructions move or add a copy of the operand at the second location to the first location, overwriting the
original operand at the first location. Either or both of the operands can be in the memory or the general-purpose
registers.
Is it possible to use fewer instructions of these types to accomplish the task in part (a)? If yes, give the sequence.

January 21, 2025 CSE, BMSCE 28

Answer
(b) Suppose that Move and Add instructions are available with the formats:
Move Location1, Location2
and
Add Location1, Location2
These instructions move or add a copy of the operand at the second location to the first location, overwriting the
original operand at the first location. Either or both of the operands can be in the memory or the general-purpose
registers.
Is it possible to use fewer instructions of these types to accomplish the task in part (a)? If yes, give the sequence.
Solution:
(b) Yes;
Move C, B
Add C, A

January 21, 2025 CSE, BMSCE 29

Test Your Knowledge
 ________ contains the memory address of the next
instruction to be fetched and executed.
a. Memory Address Register
b. Memory Data Register
c. Instruction Register
d. Program Counter

January 21, 2025 CSE, BMSCE 30

Test Your Knowledge
 ________ contains the memory address of the next
instruction to be fetched and executed.
a. Memory Address Register
b. Memory Data Register
c. Instruction Register
d. Program Counter

January 21, 2025 CSE, BMSCE 31

Test Your Knowledge
 _________ holds the instruction that is currently being
executed.
a. Memory Address Register
b. Memory Data Register
c. Instruction Register
d. Program Counter

January 21, 2025 CSE, BMSCE 32

Test Your Knowledge
 _________ holds the instruction that is currently being
executed.
a. Memory Address Register
b. Memory Data Register
c. Instruction Register
d. Program Counter

January 21, 2025 CSE, BMSCE 33

 Next we will learn

Unit 1: Number Representation and Arithmetic Operations

January 21, 2025 CSE, BMSCE 34

Three major representations of Signed Integer

1. Sign and Magnitude

2. One’s complement
3. Two’s complement

January 21, 2025 CSE, BMSCE 35

Decimal Number Representation or Base 10

In Decimal or Base 10 System, digits used are:

0123456789

Representing 537 (Five hindered and thirty Seven)

January 21, 2025 CSE, BMSCE 36

Binary Number Representation or Base 2
 Binary Digit or Bit is the smallest unit of computation on most digital
computers
 Bit has two states
 0 represents zero voltage (0v) or ground
 1 represents positive voltage (+5v)

January 21, 2025 CSE, BMSCE 37

Binary Number Representation or Base 2
Power of 2 Calculation Value

20 1 1

21 2 2

January 21, 2025 CSE, BMSCE 38

Binary Number Representation or Base 2
Power of 2 Calculation Value

20 1 1

21 2 2

Decimal Binary

0 00

1 01

2 10

3 11
January 21, 2025 CSE, BMSCE 39
Binary Number Representation or Base 2
Power of 2 Calculation Value

20 1 1

21 2 2

Decimal Binary

0 00 21 * 0 + 20 * 0 = 2*0 +1*0 = 0+0=0

1 01

2 10

3 11

January 21, 2025 CSE, BMSCE 40

Binary Number Representation or Base 2
Power of 2 Calculation Value

20 1 1

21 2 2

Decimal Binary

0 00 21 * 0 + 20 * 0 = 2*0 +1*0 = 0+0=0

1 01 21 * 0 + 20 * 1 = 2*0 +1*1 =0+1= 1

2 10 21 * 1 + 20 * 0 = 2*1 +1*0 = 2+0=2

3 11 21 * 1 + 20 * 1 = 2*1 +1*1 = 2+1=3

January 21, 2025 CSE, BMSCE 41

Example: 3-bit binary numbers
Decimal Binary Power of 2 Calculation Value
0 000
20 1
1 001
2 010 21 2 2
3 011
4 100 22 2*2 4
5 101
6 110
7 111

January 21, 2025 CSE, BMSCE 42

Question: List out all 4-bit binary numbers

Decimal Binary Power of 2 Calculation Value

0
20 1
1
2 21 2 2
3
4 22 2*2 4
5
23 2*2*2 8
6
7
8
9
10
11
12
13
14
15

January 21, 2025 CSE, BMSCE 43

Example: 4-bit binary numbers
Decimal Binary Power of 2 Calculation Value
0 0000
20 1
1 0001
2 0010 21 2 2
3 0011
4 0100 22 2*2 4
5 0101
23 2*2*2 8
6 0110
7 0111
8 1000
9 1001
10 1010
11 1011
12 1100
13 1101
14 1110
15 1111

January 21, 2025 CSE, BMSCE 44

Representation of a Binary Number
 Converting from decimal to binary (base 10 to base 2) will also produce a weighted binary
number with the right-hand most bit being the Least Significant Bit or LSB, and the left-
hand most bit being the Most Significant Bitor MSB, and we can represent this as:

 Convert binary to decimal by finding the decimal equivalent of the binary array of
digits 1011001012 and expanding the binary digits into a series with a base of 2giving an
equivalent of 35710 in decimal or denary.

(256) + (64) + (32) + (4) + (1) = 357 10

January 21, 2025 CSE, BMSCE 45

Question: Convert the following Binary number to Decimal

 Binary number: 100011

January 21, 2025 CSE, BMSCE 46

Answer

 Binary number: 100011

 Equivalent Decimal number is: 35

January 21, 2025 CSE, BMSCE 47

Decimal to Binary Conversion

January 21, 2025 CSE, BMSCE 48

Question: Represent the following Decimal number in 7-bit binary numbers

7-bit Binary
Decimal
Number
5
14
26
53

January 21, 2025 CSE, BMSCE 49

Answer

7-bit Binary
Decimal
Number
5 0000101
14 0001110
26 0011010
53 0110101

January 21, 2025 CSE, BMSCE 50

Question
 What is the biggest decimal number we can represent in
binary using 8-bit ?

 How many different decimal numbers that we can

represent in binary using 8-bit ?

January 21, 2025 CSE, BMSCE 51

Answer

What is the biggest decimal number that you can represent

in binary using 8-bit ?
255 (i.e., 28 -1=256-1=255)

How many different decimal numbers that you can

represent in binary using 8-bit ?
0 to 255 i.e., 256 decimal numbers

January 21, 2025 CSE, BMSCE 52

Signed Binary Number Representation

 We can use a single bit to identify the sign of a signed binary number as being positive or negative in
value. So to represent a positive binary number (+n) and a negative (-n) binary number, we can use
them with the addition of a sign.
 For signed binary numbers the most significant bit (MSB) is used as the sign bit. If the sign bit is “0”,
this means the number is positive in value. If the sign bit is “1”, then the number is negative in value.
The remaining bits in the number are used to represent the magnitude of the binary number in the
usual unsigned binary number format way.
 Then we can see that the Sign-and-Magnitude (SM) notation stores positive and negative values by
dividing the “n” total bits into two parts: 1 bit for the sign and n–1 bits for the value which is a pure
binary number. For example, the decimal number 53 can be expressed as an 8-bit signed binary
number as follows:

January 21, 2025 CSE, BMSCE 53

Signed Binary Number Representation
 We can use a single bit to identify the sign of a signed binary number as being positive or negative in value. So to represent a
positive binary number (+n) and a negative (-n) binary number, we can use them with the addition of a sign.
 For signed binary numbers the most significant bit (MSB) is used as the sign bit. If the sign bit is “0”, this means the number is
positive in value. If the sign bit is “1”, then the number is negative in value. The remaining bits in the number are used to represent
the magnitude of the binary number in the usual unsigned binary number format way.
 Then we can see that the Sign-and-Magnitude (SM) notation stores positive and negative values by dividing the “n” total bits into
two parts: 1 bit for the sign and n–1 bits for the value which is a pure binary number. For example, the decimal number 53 can be
expressed as an 8-bit signed binary number as follows:

January 21, 2025 CSE, BMSCE 54

Example: Signed numbers

January 21, 2025 CSE, BMSCE 55

1’s (One’s) complement number representation

 If all bits in a byte are inverted by changing each 1 to 0 and each 0 to 1, we have
formed the one’s complement of the number.

January 21, 2025 CSE, BMSCE 56

Binary Sign-Magnitude and One’s Complement representation

In One’s Complement representation, negative

values are obtained by complementing each bit
of the corresponding positive number.

January 21, 2025 CSE, BMSCE 57

Two’s Complement of Number representation
The two’s complement is a method for representing positive and negative integer values in binary. The useful
part of two’s complement is that it automatically includes the sign bit.
Rule: To form the two’s complement, add 1 to the one’s complement.

Step 1: Begin with the original binary value

10011001 Original binary number
Step 2: Find the one's complement
01100110 One's complement
Step 3: Add 1 to the one's complement
01100110 One's complement
+ 1 Add 1
-----------
01100111 <--- Two's complement

January 21, 2025 CSE, BMSCE 58

Two’s Complement
The two’s complement is a method for representing positive and negative integer values in binary. The useful
part of two’s complement is that it automatically includes the sign bit.
Rule: To form the two’s complement, add 1 to the one’s complement.

January 21, 2025 CSE, BMSCE 59

Binary Sign-Magnitude, One’s Complement representation and Two’s Complement

January 21, 2025 CSE, BMSCE 60

Conversion of Negative Numbers to Two’s Complement

 These examples show conversion of a decimal number to 4-bit twos complement.

 The bit size is always important with twos complement, since you must be able to tell where the sign bit is.
 The steps are simple.
 First, you convert the magnitude of the number to binary, and pad to the word size (4 bits).
 If the original number was positive, you are done.
 Otherwise, you must negate the binary number by inverting the bits and adding 1.

January 21, 2025 CSE, BMSCE 61

Conversion of Negative Numbers to Two’s Complement

 These examples show conversion of a decimal number to 4-bit twos complement.

 The bit size is always important with twos complement, since you must be able to tell where the sign bit is.
 The steps are simple.
 First, you convert the magnitude of the number to binary, and pad to the word size (4 bits).
 If the original number was positive, you are done.
 Otherwise, you must negate the binary number by inverting the bits and adding 1.
 Convert -6 to an 4-bit, twos complement binary number.
 Convert the magnitude, 6 to binary. So 6 10 = 1102.
 Pad to 4 bits: 0110
 Negate the number by inverting the bits and adding 1.
0110
Negate 1001
Add 1 1
--------
1010 Two’s complement of -6

January 21, 2025 CSE, BMSCE 62

Conversion of Negative Numbers to Two’s Complement

 These examples show conversion of a decimal number to 8-bit twos complement.

 The bit size is always important with twos complement, since you must be able to tell where the sign bit is.
 The steps are simple.
 First, you convert the magnitude of the number to binary, and pad to the word size (8 bits).
 If the original number was positive, you are done.
 Otherwise, you must negate the binary number by inverting the bits and adding 1.
 Convert -72 to an 8-bit, twos complement binary number.
 Convert the magnitude, 72 to binary. So 7210 = 10010002.
 Pad to 8 bits: 01001000
 Negate the number by inverting the bits and adding 1.

January 21, 2025 CSE, BMSCE 63

Question
 Using 7 bits to represent each number, write the representations of 23 and -23 in
signed-magnitude , 1’s complement and 2's complement system

January 21, 2025 CSE, BMSCE 64

Answer
 Using 7 bits to represent each number, write the representations of 23 and -23 in
signed magnitude and 2's complement integers

January 21, 2025 CSE, BMSCE 65

Question
Represent the decimal values 5, -2, 14, -10, 26, -19, 51 and -43 as signed 7-bit
numbers in the following formats
a.Sign-Magnitude
b.1’s complement
c.2’s complement

January 21, 2025 CSE, BMSCE 66

Answer
Represent the decimal values 5, -2, 14, -10, 26, -19, 51 and -43 as signed 7-bit
numbers in the following formats
a.Sign-Magnitude
b.1’s complement
c.2’s complement

January 21, 2025 CSE, BMSCE 67

Conversion of Negative Numbers to Two’s Complement

 Convert 47 to an 8-bit, twos complement binary number. This is positive, so all that is needed is to convert to
binary and pad to eight bits. So 4710 = 1011112. So 47 as an 8-bit two's complement number is just
00101111.
 Convert -109 to an 8-bit, twos complement number. So 10910 = 11011012.

 Convert -67 to an 8-bit, twos complement number. So 67 10 = 10000112.

 Convert 81 to an 8-bit, twos complement number. Since this is positive, it's just a matter of converting to binary and
padding to 8 bits. So 8110 = 10100012, giving 01010001

January 21, 2025 CSE, BMSCE 68

Under Signed Number Representation
 Number of bits used for representation is important
because
Under 8-bit representation
00000101 +5
10000101 -5
Under 4-bit representation
0101 +5
1101 -5

January 21, 2025 CSE, BMSCE 69

4-bit Signed Binary Number Representation
Decimal Signed Magnitude Signed One’s Complement Signed Two’s Complement

+7 0111 0111 0111

+6 0110 0110 0110
+5 0101 0101 0101
+4 0100 0100 0100
+3 0011 0011 0011
+2 0010 0010 0010
+1 0001 0001 0001
+0 0000 0000 0000
-0 1000 1111 –
-1 1001 1110 1111
-2 1010 1101 1110
-3 1011 1100 1101
-4 1100 1011 1100
-5 1101 1010 1011
-6 1110 1001 1010
-7 1111 1000 1001
January 21, 2025 CSE, BMSCE 70
Problem with arithmetic
 Under Sign-magnitude representation
 Under One’s Complement representation
Sign-Magnitude (4-bit Representation)

Adding 0101 +5
+5-5 1101 -5
Total 10010 INCORRECT, because the result should be zero
(1 i.e., 00000
Carryout)

One’s Complement (4-bit Representation)

Adding 0101 +5
+5-5 1010 -5
One’s Complement of -5

Total 1111 INCORRECT, because the result should be zero

i.e., 00000
But it is Minus Zero
January 21, 2025 CSE, BMSCE 71
 Arithmetic under Two’s Complement
Decimal Signed Two’s Complement

+7 0111
Two’s Complement
+6 0110 (4-bit Representation)
+5 0101
Adding 0101 +5
+4 0100 +5-5 1011 -5
+3 0011
Total 10000 CORRECT(Zero)
+2 0010
(1 Ignore the Carryout
+1 0001 Carryout)
+0 0000
-0 – Two’s Complement
(4-bit Representation)
-1 1111
-2 1110 Adding 0110 +6
+6-2 1110 -2
-3 1101
-4 1100 Total 10100 CORRECT(+4)
-5 1011 (1 Ignore the Carryout
Carryout)
-6 1010
-7 1001
January 21, 2025 CSE, BMSCE 72
Addition and Subtraction of Signed Numbers using two’s Complement

The 2’s complement is the most efficient method for performing addition and subtraction
operations

The rules governing addition and subtraction of n-bit signed numbers using 2's complement
representation system may be stated as follows:
To add two numbers, add their n-bit representation , ignoring the carry-out bit from the Most
Significant Bit (MSB) position. The sum will be algebraically correct value in 2’s complement
representation if the actual result is in the range -2n-1 through +2n-1 -1
To subtract two numbers X and Y, that is, to perform X-Y, form the 2’s complement of Y,
then add it to X using the add rule. Again, the result will be algebraically correct value in 2’s
complement representation if the actual result is in the range -2n-1 through +2n-1 -1

January 21, 2025 CSE, BMSCE 73

Addition and Subtraction of Signed Numbers
 Using 2’s complement system and considering 5-bit
representation
 Example
5+4 +5 00101
+4 00100
01001 +9

January 21, 2025 CSE, BMSCE 74

Subtraction by 2’s Complement:
The operation is carried out by means of the following steps:
(i) At first, 2’s complement of the subtrahend is found.
(ii) Then it is added to the minuend.
(iii) Throw away extra carries
(iv) If leading number (MSB) is 0, answer is positive. If leading number is 1,
answer is negative.

Note:
Subtrahend: what is being subtracted
Minuhend: what it is being subtracted from

January 21, 2025 CSE, BMSCE 75

Addition and Subtraction of Signed Numbers
 Using 2’s complement system and considering 5-bit
representation
 Example 2’s complement of -5
-5+4 -5 11011 00101 +5
11010 1’s complement
+4 00100
Add 1
1
11111 -1
11011 -5

January 21, 2025 CSE, BMSCE 76

Addition and Subtraction of Signed Numbers
 Using 2’s complement system and considering 5-bit
representation
 Example 2’s complement of -4
+5-4 5 00101 00100 +4
11011 1’s complement
-4 11100
Add 1
1
100001 +1
11100 -4

Carry Out
Ignore

January 21, 2025 CSE, BMSCE 77

Addition and Subtraction of Signed Numbers
 Using 2’s complement system and considering 5-bit
representation
2’s complement of -5
 Example 00101 +5
11010 1’s complement
-5-4 -5 11011 Add 1
1
-4 11100 11011 -5

110111 -9 2’s complement of -4

00100 +4
11011 1’s complement

Carry Out 1 Add 1

Ignore
11100 -4

January 21, 2025 CSE, BMSCE 78

Test Your knowledge

Convert the following pairs of decimal numbers to 5-bit

2’s-complement numbers, then add them.
a.-5 and 7 b. -3 and -8

January 21, 2025 CSE, BMSCE 79

Answer

Convert the following pairs of decimal numbers to 5-bit

2’s-complement numbers, then add them.
a.-5 and 7 b. -3 and -8

January 21, 2025 CSE, BMSCE 80

Example of two’s Complement Arithmetic

January 21, 2025 CSE, BMSCE 81

Example of two’s Complement Arithmetic

January 21, 2025 CSE, BMSCE 82

Arithmetic Overflow
 In 2's complement number representation system, n-bits can represent values in the
range (-2n-1) to (+2n-1 – 1).
 When the result of an arithmetic operation is outside the representable range, an
arithmetic overflow has occurred.

January 21, 2025 CSE, BMSCE 83

Arithmetic Overflow

Care must be taken when adding numbers of like sign since overflow can occur.
If you add two numbers of like sign and the result is of the opposite sign, then the result cannot be used. This
"overflow" condition occurs because, in order to represent the result, we would need more bits than are available
in the bit field. (Remember, we can't just "enlarge" the size of the result- it must remain the same size as the
operands.) Here are examples for adding two negative numbers, and adding two positive numbers, each of which
results in overflow.

January 21, 2025 CSE, BMSCE 84

Detecting overflow when adding two 2’s complement numbers
If 2 Two's Complement numbers are added, and they both have the same sign (both positive or both
negative), then overflow occurs if and only if the result has the opposite sign. Overflow never occurs when
adding operands with different signs. i.e. Adding two positive numbers must give a positive result Adding
two negative numbers must give a negative result

Overflow occurs if
(+A) + (+B) = −C
(−A) + (−B) = +C

Example: Using 4-bit Two's Complement numbers (−8 ≤ x ≤ +7)

(−7) 1001
+(−6) 1010
---------------
(−13) 1 0011 = 3 : Overflow (largest −ve number is −8)

January 21, 2025 CSE, BMSCE 85

Test Your Knowledge
Convert the following pairs of decimal numbers to 5-bit 2’s-complement numbers, then
add them. State whether or not overflow occurs in each case
a. 7 and 13 b. -10 and -13

January 21, 2025 CSE, BMSCE 86

Answer
Convert the following pairs of decimal numbers to 5-bit 2’s-complement numbers, then
add them. State whether or not overflow occurs in each case
a. 7 and 13 b. -10 and -13

January 21, 2025 CSE, BMSCE 87

Question
Convert the following pairs of decimal numbers to 5-bit 2’s-complement numbers, then
add them. State whether or not overflow occurs in each case
a.5 and 10
b.7 and 13
c.-14 and 11
d.-5 and 7
e.-3 and -8
f.-10 and -13

January 21, 2025 CSE, BMSCE 88

Detecting overflow when subtracting two 2’s complement numbers

If two 2's Complement numbers are subtracted, and their signs are different, then overflow
occurs if and only if the result has the same sign as the subtrahend.
Overflow occurs if
(+A) − (−B) = −C
(−A) − (+B) = +C
Example: Using 4-bit Two's Complement numbers (−8 ≤ x ≤ +7)
Subtract −6 from +7
(+7) 0111 0111
−(−6) 1010 -> Negate -> +0110
---------- -----
13 1101 (−3) : Overflow

January 21, 2025 CSE, BMSCE 89

Question
Repeat for subtraction operation, where the second number of each pair to be
subtracted from first number. State whether or not overflow occurs in each case
a.5 and 10
b.7 and 13
c.-14 and 11
d.-5 and 7
e.-3 and -8
f.-10 and -13

January 21, 2025 CSE, BMSCE 90

How to avoid Overflow
 You can enlarge the size of the bit field, but only before you perform any operations, and it must be done a
certain way. If you find that the size of the bit field is too small and overflow is occurring, you can promote the values to
larger bit fields. This is done by a technique called sign extension. To enlarge the bit field, add bits on the left, duplicating
the most significant bit. This preserves the sign of the number and does not alter its value. Remember, you must promote
all values to the same size. The table below illustrates sign-extension of a 4-bit number to 5, 6, and 8-bit fields. In each
case, the most significant bit of the original 4-bit field (in blue) is simply repeated as many times as necessary on the left(in
red).

January 21, 2025 CSE, BMSCE 91

 Unit1:Memory Locations and Addresses

January 21, 2025 CSE, BMSCE 92

Memory Locations and Addresses

January 21, 2025 CSE, BMSCE 93

 Memory Locations and Addresses
Address n bits
0 first word

1 second word

•
•
•
i th word

•
•
•
M-1 last word

January 21, 2025 CSE, BMSCE 94

Memory Locations and Addresses

Address Length Addressable Locations

K-bits 2k

2 22=4 Locations
3 23=8 Locations
4 24=16 Locations

Memory
Address Word Length
K=2bits n =8bits = 1 Byte
0 00 0000 0110 1st Byte or word
1 01 0000 0111 2nd Byte or word
2 10 0000 1000 3rd Byte or word
3 11 0000 1010 4th Byte or word

January 21, 2025 CSE, BMSCE

Memory Locations and Addresses
Address Length Addressable Locations Memory
K-bits 2k
Address Word Length
2 22=4 Locations K=3bits n =8bits = 1 Byte
3 23=8 Locations 0 000 0000 0110 1st Byte or word

4 24=16 Locations 1 001 0000 0111 2nd Byte or word

2 010 0000 1000 3rd Byte or word
3 011 0000 1010 4th Byte or word
4 100 0000 1011 5th Byte or word

5 101 0000 1100 6th Byte or word

6 110 0000 1101 7th Byte or word
7 111 0000 1110 8th Byte or word

Examples: k  20  220 or 1M locations,

k  32  232 or 4G locations

January 21, 2025 CSE, BMSCE

 Question
Address Length Addressable Locations
Memory
K-bits 2k Address Word Length
K=3bits n =8bits = 1 Byte
2 22=4 Locations 0 000 0000 0110 1st Byte or word
3 23=8 Locations 1 001 0000 0111 2nd Byte or word
4 24=16 Locations 2 010 0000 1000 3rd Byte or word
3 011 0000 1010 4th Byte or word
4 100 0000 1011 5th Byte or word
Question:
Consider in one memory location, 5 101 0000 1100 6th Byte or word
One byte of information can be stored 6 110 0000 1101 7th Byte or word
i.e., n=8bits. To store 1024 bytes of information, 7 111 0000 1110 8th Byte or word
How many address bits should be used
i.e., what should be the k value ?

January 21, 2025 CSE, BMSCE

 Question
Address Length Addressable Locations Address Word Length
K-bits 2k K=3bits n =8bits = 1 Byte
0 000 0000 0110 1st Byte or word
2 22=4 Locations
1 001 0000 0111 2nd Byte or word
3 23=8 Locations
2 010 0000 1000 3rd Byte or word
4 24=16 Locations
3 011 0000 1010 4th Byte or word
4 100 0000 1011 5th Byte or word

5 101 0000 1100 6th Byte or word

Question: 6 110 0000 1101 7th Byte or word
Consider in one memory location,
7 111 0000 1110 8th Byte or word
One byte of information can be stored
i.e., n=8bits. To store 1024 bytes of information
Answer
How many address bits should be used
i.e., what should be the k value ? Kilo Bytes (103) 210 =1024
or Therefore number of address
1024 Bytes bits should be 10 bits

January 21, 2025 CSE, BMSCE

Byte Addressability
 Byte size is always 8 bits
 But word length may range from 16 to 64 bits
 Impractical to assign an address to each bit
 Instead, provide a byte-addressable memory that assigns
an address to each byte
 Byte locations have addresses 0, 1, 2, …
 Assuming that the word length is 32 bits,
word locations have addresses 0, 4, 8, …

January 21, 2025 CSE, BMSCE 99

Two ways of Byte address assignment across words

 Big-endian and little-endian are terms that describe the order in which
a sequence of bytes are stored in computer memory.
1. Big-endian addressing assigns Lower byte addresses to Most Significant
(leftmost) bytes of word
2. Little-endian addressing assigns Lower byte addresses to Least Significant
(rightmost) bytes of word

January 21, 2025 CSE, BMSCE 100

Two ways of Byte address assignment across words

 Example: Consider storing the number 2064 i.e., Two thousand Sixty four. We will assume one digit
occupies 4bits.

2064 2 0 6 4
0010 0000 0110 0100
MSB LSB
Most Significant Byte Least Significant Byte

January 21, 2025 CSE, BMSCE 101

 Two ways of Byte address assignment across words

 Example: Consider storing the number 2064 i.e., Two thousand Sixty four. We will assume one digit
occupies 4bits.
2064 2 0 6 4
0010 0000 0110 0100
MSB LSB
Most Significant Byte Least Significant Byte

Big-Endian Approach Little-Endian Approach

Word Length Word Length

Address n=8bits=1 Byte Address n=8bits=1 Byte
00 0010 0000 20 MSB 00 0110 0100 64 LSB

01 0110 0100 64 LSB 01 0010 0000 20 MSB

Big-endian addressing assigns Lower byte addresses Little-endian addressing assigns Lower byte addresses
to Most Significant (leftmost) bytes of word to Least Significant (rightmost) bytes of word

January 21, 2025 CSE, BMSCE 102

Big-Endian and Little-Endian Assignments
 Big-Endian: lower byte addresses are used for the most significant bytes of the word
 Little-Endian: opposite ordering. lower byte addresses are used for the less significant bytes of the word

W ord
address Byte address Byte address

0 0 1 2 3 0 3 2 1 0

4 4 5 6 7 4 7 6 5 4

• •
• •
• •
k k k k k k k k k k
2 - 4 2 - 4 2 - 3 2 - 2 2 - 1 2 - 4 2 - 1 2 - 2 2 - 3 2 - 4

(a) Big-endian assignment (b) Little-endian assignment

Figure :. Byte and word addressing.
January 21, 2025 CSE, BMSCE 103
Hexadecimal numbers
 A group of 4 bits can take any value between 0 (0000 binary) and 15 (1111 binary).
 In hexadecimal, we replace each group of 4 bits with a single digit to represent the value 0 to 15. Since we only have digits 0 to 9, we use
letters A to E to represent values 10 to 15. Here is a table of binary, denary and hex values:

Note: To specify
Hexadecimal numbers
Prefix 0x will be used
i.e.,
0x123
or
123h

January 21, 2025 CSE, BMSCE 104

Question
 Consider a computer has a byte-addressable memory organized in 32-bit words according to the big-endian
scheme. A program reads ASCII characters entered at a keyboard and stores them in successive byte
locations, starting at location 1000. Show the contents of the two memory words at locations 1000 and 1004
after the word “computer” has been entered. Values corresponding to the characters are as shown below:

Hex
c 0x63
o 0x6F
m 0x6D
p 0x70
u 0x75
t 0x74
e 0x65
r 0x72

January 21, 2025 CSE, BMSCE 105

Answer
 Consider a computer has a byte-addressable memory organized in 32-bit words according to the big-endian scheme. A
program reads ASCII characters entered at a keyboard and stores them in successive byte locations, starting at location
1000. Show the contents of the two memory words at locations 1000 and 1004 after the word “computer” has been
entered. Values corresponding to the characters are as shown below:

Word Length
Hex Address n=8bits=1 Byte
c 63 1000 0110 0011 c 63 MSB
o 6F 1001 0110 1111 o 6F
m 6D 1002 0110 1101 m 6D
p 70 1003 0111 0000 p 70
u 75 1004 0111 0101 u 75 Big-Endian Approach
t 74 1005 0111 0100 t 74
e 65 1006 0110 0101 e 65
r 72 1007 0111 0010 r 72 LSB
January 21, 2025 CSE, BMSCE 106
Question
 Consider a computer has a byte-addressable memory organized in 32-bit words according to the Little-endian scheme. A
program reads ASCII characters entered at a keyboard and stores them in successive byte locations, starting at location
1000. Show the contents of the two memory words at locations 1000 and 1004 after the word “computer” has been
entered. Values corresponding to the characters are as shown below:

Hex
c 63
o 6F
m 6D
p 70
u 75
t 74
e 65
r 72

January 21, 2025 CSE, BMSCE 107

Answer
 Consider a computer has a byte-addressable memory organized in 32-bit words according to the Little-endian scheme. A
program reads ASCII characters entered at a keyboard and stores them in successive byte locations, starting at location
1000. Show the contents of the two memory words at locations 1000 and 1004 after the word “computer” has been
entered. Values corresponding to the characters are as shown below:

Word Length
Hex Address n=8bits=1 Byte
c 63 1000 0110 0011 r 72 LSB
o 6F 1001 0110 1111 e 65 1000: 72 65 74 75
m 6D 1002 0110 1101 t 74 r e t u
p 70 1003 0111 0000 u 75
1004: 70 6D 6F 63
u 75 p m o c
1004 0111 0101 p 70 Little-Endian
t 74 1005 0111 0100 m 6D Approach
e 65 1006 0110 0101 o 6F
r 72 1007 0111 0010 c 63 MSB

January 21, 2025 CSE, BMSCE 108

Memory Word Alignment
 Words are said to be Aligned in memory if they begin at a byte-address
that is a multiple of number of bytes in a word.
 For example,
 If the word length is 16 (2 Bytes), aligned words begin at byte addresses 0, 2,
4,....
 If the word length is 32 (4 Bytes), aligned words begin at byte addresses 0, 4,
8,....
 Words are said to have Unaligned Addresses, if they begin at an
arbitrary byte-address

January 21, 2025 CSE, BMSCE 109

Memory Operations

January 21, 2025 CSE, BMSCE 110

 INSTRUCTIONS and INSTRUCTION SEQUENCING

January 21, 2025 CSE, BMSCE 111

Instructions
A computer must have instruction capable of performing the following
operations. They are:
Data transfer between memory and processor register (Ex.: MOVE,
LOAD, STORE )
Arithmetic and logical operations on data (Ex.: ADD, SUB)
Program sequencing and control (Ex.: BRANCH, CALL, RET)
I/O transfer (Ex. IN, OUT).

January 21, 2025 CSE, BMSCE 112

Register Transfer Notation
The possible locations that may be involved during data transfer are
1.Memory Location
2.Processor register
3.Registers in I/O sub-system.

Use […] to denote contents of a location

Use  to denote transfer to a destination
Example: R2  [LOC]
(transfer from LOC in memory to register R2)
Example: R4  [R2]  [R3]
(add the contents of registers R2 and R3, place the sum in register R4)

January 21, 2025 CSE, BMSCE 113

Assembly Language Notation
 To represent machine instructions and programs, assembly language
format is used

Example
Load R2, LOC ; R2  [LOC]

Add R4, R2, R3 ; R4  [R2]  [R3]

January 21, 2025 CSE, BMSCE 114

RISC and CISC Instruction Sets
 One of the most important characteristics that distinguish
different computers is the nature of their instructions.
Two fundamental approaches in design of instruction sets for modern
computers
Reduced Instruction Set Computers Complex Instruction Set Computers
(RISC) (CISC)
Have one-word instructions and Have multi-word instructions and
require arithmetic operands to be allow operands directly from
in registers. memory.

January 21, 2025 CSE, BMSCE 115

RISC Instruction Sets
 Focus on RISC first because it is simpler
 RISC instructions each occupy a single word
 A load/store architecture is used, meaning:
 only Load and Store instructions are used
to access memory operands
 operands for arithmetic/logic instructions
must be in registers, or one of them
may be given explicitly in instruction word

January 21, 2025 CSE, BMSCE 116

RISC Instruction Sets

1. Load instruction format

Load Destination , Source or
Load Processor_register, Memory_location

2. Store instruction format

Store Source , Destination or
Store Processor_register, Memory_location

January 21, 2025 CSE, BMSCE 117

RISC Instruction Sets

Example, sequence of instructions to perform the task

C=A+B ; C ← [A] + [B]

Sequence of simple RISC instructions for the task C = A + B :

Load R2, A
Load R3, B
Add R4, R2, R3
Store R4, C

January 21, 2025 CSE, BMSCE 118

Task of adding a list of n numbers
Without Looping

The program outlined in Figure is adding n

numbers. The addresses of the memory locations
containing the n numbers are symbolically
given as NUM1, NUM2, . . . , NUMn, and
separate Load and Add instructions are used to
add each number to the contents of register R2.
After all the numbers have been added, the result
is placed in memory location SUM.

January 21, 2025 CSE, BMSCE 119

Rough Slide : To explain “Program to add n numbers” without Looping
Memory Address
4 Bytes Address 3000
Load R2, NUM1
N 4 1000 3004
Load R3, Num2
Sum 1004 3008
Add R2, R2, R3
Num1 2 1008 3012
Load R3, Num3
Num2 1 1012
Add R2, R2, R3 3016
Num3 3 1016
Load R3, Num4 3020
Num4 10 1020
Add R2, R2, R3 3024

R3 Store R2, SUM 3028

R2

January 21, 2025 CSE, BMSCE 120

Task of adding a list of n numbers With Looping/Branching
Instead of using a long list of Load and Add instructions,
it is possible to implement a program loop in which the instructions
read the next number in the list and add it to the current sum.
To add all numbers, the loop has to be executed as many times
as there are numbers in the list. Figure shows the structure of the
desired program. The body of the loop is a straight-line sequence
of instructions executed repeatedly. It starts at location LOOP and
ends at the instruction Branch_if_[R2]>0. During each pass through
this loop, the address of the next list entry is determined, and that
entry is loaded into R5 and added to R3.

January 21, 2025 CSE, BMSCE 121

 Rough Slides : To explain “Program to add n numbers” with Branching
Memory 4 Bytes Address
Address
Load R2, N 3000
N 4 1000
Clear R3 3004
Sum 1004
Move R4, #Num1 3008
Num1 2 1008
Loop: Load R5, (R4) 3012
Num2 1 1012
Add R3, R3, R5 3016
Num3 3 1016
Num4 Add R4, R4, #4 3020
10 1020
Subtract R2, R2, #1 3024
R2 R3 R5 R4 Branch_if_[R2] > 0 LOOP 3028

Store R3, SUM 3032

January 21, 2025 CSE, BMSCE 122

 Addressing Modes

January 21, 2025 CSE, BMSCE 123

Addressing Modes
The term addressing modes refers to the way in which the operand of an instruction is
specified. Information contained in the instruction code is the value of the operand or
the address of the operand. Following are the main addressing modes that are used on
various platforms and architectures.
1.Register Addressing Mode
2.Immediate Addressing Mode
3.Absolute (or Direct) Addressing Mode
4.Register Indirect Addressing Mode
5.Index Addressing Mode
6.Base with Index Addressing Mode

January 21, 2025 CSE, BMSCE 124

Register Addressing Mode
 The operand is the content of a processor register. Register name is specified in the
instruction.
 Effective Address of the Operand: Register name specified in the instruction

ADD R1, R0, R1 ; R1 ← [R0] + [R1]

Before Executing the Instruction After Executing the Instruction

Registers Contents Registers Contents

R0 8 R0 8
R1 2 R1 10

January 21, 2025 CSE, BMSCE 125

Register Addressing Mode
 The operand is the content of a processor register. Register name is specified in the
instruction.
 Effective Address of the Operand: Register name specified in the instruction

Move R1, R0 ; R1 ← [R0]

Before Executing the Instruction After Executing the Instruction

Registers Contents Registers Contents

R0 8 R0 8
R1 2 R1 8

January 21, 2025 CSE, BMSCE 126

Immediate Addressing Mode
 The operand is given explicitly in the instruction
 Effective Address of the Operand: Operand value given in the instruction

ADD R1, R1, #10 ; R1 <- R1 +10

Before Executing the Instruction After Executing the Instruction

Registers Contents Registers Contents

R1 2 R1 12

January 21, 2025 CSE, BMSCE 127

Immediate Addressing Mode
 The operand is given explicitly in the instruction
 Effective Address of the Operand: Operand value given in the instruction

Move R1 , #10 ; R1 <- 10

Before Executing the Instruction After Executing the Instruction

Registers Contents Registers Contents

R1 2 R1 10

January 21, 2025 CSE, BMSCE 128

Absolute (or Direct) Addressing Mode
 The operand is a Memory location. The address of the memory location is given in
the instruction explicitly.
 Effective Address of the Operand: Address of the memory location given directly in
the instruction
ADD R1 , R2, LOCA ; R1 ← [R2] + [LOCA]
Before Executing the Instruction After Executing the Instruction
Addr Memory Contents Addr Memory Contents

LOCA 0x1000 8 LOCA 0x1000 8

R1 2 R1 18
R2 10 R2 10

January 21, 2025 CSE, BMSCE 129

Register Indirect Addressing Mode
 Here neither the operands nor the their addresses are given explicitly. The instruction provides the
information from which the address of the operand is determined i.e., the instruction provides effective
address of the operand using register. The indirection is denoted by () sign around register.
 Effective Address of the Operand: Contents of a register that is specified in the instruction

ADD R2, R2, (R1) ; R2 ← R2 + [[R1]]

Before Executing the Instruction After Executing the Instruction
Addr Memory Contents Addr Memory Contents

0x2000 2 0x2000 2

R1 0x2000 R1 0x2000
R2 8 R2 10

January 21, 2025 CSE, BMSCE 130

Question
What will be the contents of the
Register R1
And Contents of the Memory location with address 0x1000 and 0x200
After executing the instruction ADD (R1), (R1), R2

ADD (R1) , (R1), R2 ; [[R1]] ← [[R1]] + [R]

Before Executing the Instruction After Executing the Instruction
Addr Memory Contents Addr Memory Contents

LOCA 0x1000 8 LOCA 0x1000 ??

0x2000 2 0x2000 ??
R1 0x2000 R1 ??
R2 10 R2 ??

January 21, 2025 CSE, BMSCE 131

Answer
What will be the contents of the
Register R1
And Contents of the Memory location with address 0x1000 and 0x200
After executing the instruction ADD (R1), (R1), R2

ADD (R1) , (R1), R2 ; [[R1]] ← [[R1]] + [R2]

Before Executing the Instruction After Executing the Instruction
Addr Memory Contents Addr Memory Contents

LOCA 0x1000 8 LOCA 0x1000 8

0x2000 2 0x2000 12
R1 0x2000 R1 0x2000
R2 10 R2 10

January 21, 2025 CSE, BMSCE 132

Question

What does the symbol '#' represent in the instruction

MOVE R0 , #55H ?
a. Direct datatype
b. Indirect datatype
c. Immediate datatype
d. Indexed datatype

January 21, 2025 CSE, BMSCE 133

Immediate

What does the symbol '#' represent in the instruction

MOVE R0 , #55H?
a. Direct datatype
b. Indirect datatype
c. Immediate datatype
d. Indexed datatype

January 21, 2025 CSE, BMSCE 134

Question

In which addressing mode, the operand is fetched from

memory
a. Immediate addressing
b. Direct addressing
c. Register addressing
d. None of these

January 21, 2025 CSE, BMSCE 135

Answer

In which addressing mode, the operand is fetched from

memory
a. Immediate addressing
b. Direct addressing
c. Register addressing
d. None of these

January 21, 2025 CSE, BMSCE 136

Index Addressing Mode
 The effective address of the operand is generated by adding a constant value to the contents of a
register specified in the instruction. The register in this case is called as Index register.
 The operation is indicated as X(Ri).
 Effective Address of the Operand: X+Ri where X is a constant value (signed integer) and Ri is the
index register.

LOAD R2, 5(R1) ; R2 ← [5+[R1]]

Before Executing the Instruction After Executing the Instruction

Addr Memory Contents Addr Memory Contents

0x2005 2 0x2005 2

R1 0x2000 R1 0x2000
R2 8 R2 2

January 21, 2025 CSE, BMSCE 137

Base with Index Addressing Mode
 The effective address of the operand is generated by adding two registers specified in the instruction.
 The operation is indicated as (Ri , Rj).
 Effective Address of the Operand: Ri + Rj where Ri is used to contain offset and Rj is the base register

LOAD R2, (R1, R3) ; R2 ← [[R1]+[R3]]

Before Executing the Instruction After Executing the Instruction

Addr Memory Contents Addr Memory Contents

0x2005 6 0x2005 6

R1 0x2000 R1 0x2000
R2 8 R2 6
R3 5 R3 5

January 21, 2025 CSE, BMSCE 138

Question
The addressing mode used in the instruction
Move R1, 8(R2) is
a.Register and Index
b.Register and Direct
c.Register and Immediate

January 21, 2025 CSE, BMSCE 139

Answer
The addressing mode used in the instruction
Move R1, 8(R2) is
a.Register and Index
b.Register and Direct
c.Register and Immediate

January 21, 2025 CSE, BMSCE 140

Question
Register R1 of the computer contain decimal value 1200. What is the effective address
of the source operand for the instruction Load 20(R1),R5 . Assume instruction Format
“Load SourceOperand, DestinationOperand”.

January 21, 2025 CSE, BMSCE 141

Answer
Register R1 of computer contain decimal value 1200. What is the effective address of
the source operand for the instruction Load 20(R1),R5 . Assume instruction Format
“Load SourceOperand, DestinationOperand”.

Effective Address: 1220

January 21, 2025 CSE, BMSCE 142

Question
Register R1 and R2 of computer contains the decimal value 1200 and 4600. What is the
effective address of the destination operand for the instruction
Store R5,30(R1,R2)
Assume instruction Format
“Store SourceOperand, DestinationOperand”

January 21, 2025 CSE, BMSCE 143

Answer
Register R1 and R2 of computer contains the decimal value 1200 and 4600. What is the
effective address of the destination operand for the instruction
Store R5,30(R1,R2)
Assume instruction Format
“Store SourceOperand, DestinationOperand”

Effective Address: 5830=30+1200+4600

January 21, 2025 CSE, BMSCE 144

Summarizing Addressing Modes

January 21, 2025 CSE, BMSCE 145

Question
Registers R4 and R5 contain the decimal numbers 2000 and 3000 before each of
the following addressing modes is used to access a memory operand. What is
the effective address (EA) in each case?
i. 12(R4)
ii. (R4,R5)
iii. 28(R4,R5)

January 21, 2025 CSE, BMSCE 146

Question
Registers R4 and R5 contain the decimal numbers 2000 and 3000 before each of the following
addressing modes is used to access a memory operand. What is the effective address (EA) in
each case?
i. 12(R4)
EA=[R4]+12
2012=2000+12

ii. (R4,R5)
EA=[R4]+[R5]
5000=2000+3000

iii. 28(R4,R5)
EA= [28]+[R4]+[R5]
5028= 28+2000+3000
January 21, 2025 CSE, BMSCE 147
Index Addressing Mode used in accessing Test Scores
Move R2, #LIST ; Get the address LIST.
Clear R3
Clear R4
Clear R5
Load R6, N ; Load the value n.
LOOP: Load R7, 4(R2) ; Add the mark for next student's
Add R3, R3, R7 ; Test 1 to the partial sum.
Load R7, 8(R2) ; Add the mark for that student's
Add R4, R4, R7 ; Test 2 to the partial sum.
Load R7, 12(R2) ; Add the mark for that student's
Add R5, R5, R7 ; Test 3 to the partial sum.
Add R2, R2, #16 ; Increment the pointer.
Subtract R6, R6, #1 ; Decrement the counter.
Branch_if_[R6]>0 LOOP ; Branch back if not finished.
Store R3, SUM1 ; Store the total for Test 1.
Store R4, SUM2 ; Store the total for Test 2.
Store R5, SUM3 ; Store the total for Test 3.

January 21, 2025 CSE, BMSCE 148

 Program to find sum of Test1, Test2 and Test3 marks of all students
Memory
4 Bytes Address

N 2 1000

List BM01 1004 Student ID

1 1008 Test1 Marks

2 1012 Test2 Marks

3 1016 Test3 Marks

BM02 1020 Student ID

10 1024 Test1 Marks

20 1028 Test2 Marks

30 1032 Test3 Marks

Sum1 1036

Sum2 1040

Sum3 1044

January 21, 2025 CSE, BMSCE 149

 Move R2, #List 3000

Clear R3 3004
Program to find sum of Test1, Test2 and Test3 marks of all students
Clear R4 3008
Memory
4 Bytes Address Clear R5 3012

N 2 1000 Load R6, N 3016

List BM01 1004 Student ID Loop: Load R7, 4(R2) 3020

1 1008 Test1 Marks Add R3, R3, R7 3024

2 1012 Test2 Marks Load R7, 8(R2) 3028
3 1016 Test3 Marks Add R4, R4, R7 3032
BM02 1020 Student ID Load R7, 12(R2) 3036
10 1024 Test1 Marks Add R5, R5, R7 3040
20 1028 Test2 Marks Add R2, R2, #16 3044
30 1032 Test3 Marks Subtract R6, R6, #1 3048
Sum1 1036 Branch_if_[R6] >0 Loop 3052
Sum2 1040 Store R3, Sum1 3056
Sum3 1044 Store R4, Sum2 3060

Store R5, Sum3 3064

January 21, 2025 CSE, BMSCE 150

 Move R2, #List 3000

Clear R3 3004
After executing the program
Clear R4 3008
Memory
4 Bytes Address Clear R5 3012

N 2 1000 Load R6, N 3016

List BM01 1004 Student ID Loop: Load R7, 4(R2) 3020

1 1008 Test1 Marks Add R3, R3, R7 3024

2 1012 Test2 Marks Load R7, 8(R2) 3028
3 1016 Test3 Marks Add R4, R4, R7 3032
BM02 1020 Student ID Load R7, 12(R2) 3036
10 1024 Test1 Marks Add R5, R5, R7 3040
20 1028 Test2 Marks Add R2, R2, #16 3044
30 1032 Test3 Marks Subtract R6, R6, #1 3048
Sum1 11 1036 Branch_if_[R6] >0 Loop 3052
Sum2 22 1040 Store R3, Sum1 3056
Sum3 33 1044 Store R4, Sum2 3060

Store R5, Sum3 3064

January 21, 2025 CSE, BMSCE 151

Question
The list of student marks shown in Figure 2.10 is changed to contain j test scores for each student. Assume that there are n students.
Write a RISC-style program for computing the sums of the scores on each test and store these sums in the memory word locations at
addresses SUM, SUM + 4, SUM + 8,.... The type of program shown in Figure 2.11 for the 3-test case cannot be used. Use two nested
loops. The inner loop should accumulate the sum for a particular test, and the outer loop should run over the number of tests, j. Assume
that the memory area used to store the sums has been cleared to zero initially.

January 21, 2025 CSE, BMSCE 152

Solution Approach
Memory word location J contains the number of tests, j, and memory word location N contains the number of students, n. The list of
student marks begins at memory word location List in the format as shown in figure. The parameter Stride = 4(j+1) is the distance in
bytes between scores on a particular test for adjacent students in the list. The Based with index addressing mode (R1, R2) is used to
access the scores on a particular test. Register R1 points to the test score for student-1 , and R2 is incremented by Stride in the inner loop
to access scores on the sum test by successive students in the list.

January 21, 2025 CSE, BMSCE 153

Solution Approach
Memory word location J contains the number of tests, j, and memory word location N contains the number of students, n. The list of
student marks begins at memory word location List in the format as shown in figure. The parameter Stride = 4(j+1) is the distance in
bytes between scores on a particular test for adjacent students in the list. The Based with index addressing mode (R1, R2) is used to
access the scores on a particular test. Register R1 points to the test score for student-1 , and R2 is incremented by Stride in the inner loop
to access scores on the sum test by successive students in the list.

January 21, 2025 CSE, BMSCE 154

Program Move R4, J
Add R4, R4, #1
Multply R4, R4, #4
Move R1, #List
Add R1, R1, #4
Move R3, #Sum
Move R10, J
OUTER: Move R11, N
Clear R2
Clear R0
INNER: Add R0, R0, (R1, R2)
Add R2, R2, R4
Subtract R11, R11, #1
Branch_if_[R11] > 0 INNER
Load (R3), R0
Add R3, R3, #4
Add R1, R1, #4
Subtract R10, R10, #1
Branch_if_[R10] > 0 OUTER

January 21, 2025 CSE, BMSCE 155

Question
Can the program given will work to find the sum of test scores of all students if we increase the
number of tests to four

January 21, 2025 CSE, BMSCE 156

Answer
Can the program given will work find the sum of test scores of all students if we increase the
number of tests to four: Yes

January 21, 2025 CSE, BMSCE 157

Assembler Directives
 Assembler Directive: a statement to give direction to the
assembler to perform task of the assembly process.
 Instructions: translated to the machine code by the
assembler
 Assembler Directives: are not translated to the machine
codes

January 21, 2025 CSE, BMSCE 158

List of Assembler Directives
1. ORIGIN directive tells the assembler where to load instructions and data into
memory. It changes the program counter to the value specified by the
expression in the operand field.
2. RESERVE directives are used for reserving space for uninitialized data. The
reserve directives take a single operand that specifies the number of units of
space to be reserved
3. DATAWORD directives are used to initialize the memory location with
specified value
4. EQU: The equate directive is used to substitute values for symbols or labels.

January 21, 2025 CSE, BMSCE 159

 Memory
Assembly Language with Assembler directives: 4 Bytes
Address
To add n numbers Load R2, N 100

ORIGIN 100 Clear R3 104

Load R2, N Move R4, #Num1 108
Clear R3
Loop: Load R5, (R4) 112
Move R4, #Num1
Add R3, R3, R5 116
LOOP: Load R5, (R4)
ADD R3, R3, R5 Add R4, R4, #4 120

ADD R4, R4, #4 Subtract R2, R2, #1 124

Subtract R2, R2, #1 Branch_if_[R2] > 0 LOOP 128
Branch_if_[R2] > 0 LOOP
Store R3, SUM 132
Store R3, SUM
………… …
ORIGIN 200
SUM: RESERVE 4 SUM 200

N : DATAWORD 3 N 3 204
NUM: DATAWORD 10, 20, 30 NUM 10 208
END
20 212

30 216

January 21, 2025 CSE, BMSCE 160

Question
Write a RISC-style program that finds the number of negative integers in a list of n 32-bit
integers and stores the count in location NEGNUM. The value n is stored in memory location N,
and the first integer in the list is stored in location NUMBERS. Include the necessary assembler
directives and a sample list that contains six numbers, some of which are negative.

January 21, 2025 CSE, BMSCE 161

 Thanks for Listening

END of Unit-1

January 21, 2025 CSE, BMSCE 162