Logic and Computer Design Fundamentals

Chapter 6 – Sequential
Circuits
Part 2 – Sequential Circuit Design

Charles Kime & Thomas Kaminski

© 2004 Pearson Education, Inc.
Terms of Use
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Overview
 Part 1
• Types of Sequential Circuits
• Storage Elements
 Latches
 Flip-Flops
• Sequential Circuit Analysis
 State Tables
 State Diagrams

 Part 2
• Sequential Circuit Design
 Specification
 Formulation
 State Assignment
 Flip-Flop Input and Output Equation Determination
 Optimization
 Verification

Chapter 6 - Part 2 2
The Design Procedure

 Specification
 Formulation - Obtain a state diagram or state table
 State Assignment - Assign binary codes to the states
 Flip-Flop Input Equation Determination - Select flip-flop
types and derive flip-flop equations from next state entries in the
table
 Output Equation Determination - Derive output equations
from output entries in the table
 Optimization - Optimize the equations
 Technology Mapping - Find circuit from equations and map
to flip-flops and gate technology
 Verification - Verify correctness of final design

Chapter 6 - Part 2 3
Specification

 Component Forms of Specification

• Written description
• Mathematical description
• Hardware description language*
• Tabular description*
• Equation description*
• Diagram describing operation (not just structure)*
 Relation to Formulation
• If a specification is rigorous at the binary level
(marked with * above), then all or part of
formulation may be completed

Chapter 6 - Part 2 4
Formulation: Finding a State Diagram

 A state is an abstraction of the history of the past

applied inputs to the circuit (including power-up reset
or system reset).
• The interpretation of “past inputs” is tied to the synchronous
operation of the circuit. E. g., an input value (other than an
asynchronous reset) is measured only during the setup-hold
time interval for an edge-triggered flip-flop.
 Examples:
• State A represents the fact that a 1 input has occurred among
the past inputs.
• State B represents the fact that a 0 followed by a 1 have
occurred as the most recent past two inputs.

Chapter 6 - Part 2 5
Formulation: Finding a State Diagram
 In specifying a circuit, we use states to remember
meaningful properties of past input sequences that are
essential to predicting future output values.
 A sequence recognizer is a sequential circuit that
produces a distinct output value whenever a prescribed
pattern of input symbols occur in sequence, i.e,
recognizes an input sequence occurence.
 We will develop a procedure specific to sequence
recognizers to convert a problem statement into a state
diagram.
 Next, the state diagram, will be converted to a state
table from which the circuit will be designed.

Chapter 6 - Part 2 6
Sequence Recognizer Procedure
 To develop a sequence recognizer state diagram:
• Begin in an initial state in which NONE of the initial portion of
the sequence has occurred (typically “reset” state).
• Add a state that recognizes that the first symbol has occurred.
• Add states that recognize each successive symbol occurring.
• The final state represents the input sequence (possibly less the
final input value) occurence.
• Add state transition arcs which specify what happens when a
symbol not in the proper sequence has occurred.
• Add other arcs on non-sequence inputs which transition to
states that represent the input subsequence that has occurred.
 The last step is required because the circuit must recognize the
input sequence regardless of where it occurs within the overall
sequence applied since “reset.”.

Chapter 6 - Part 2 7
State Assignment
 Each of the m states must be assigned a
unique code
 Minimum number of bits required is n
such that
n ≥ log2 m
where x is the smallest integer ≥ x
 There are useful state assignments that use
more than the minimum number of bits
 There are 2n - m unused states

Chapter 6 - Part 2 8
Sequence Recognizer Example

 Example: Recognize the sequence 1101

• Note that the sequence 1111101 contains 1101 and "11" is a
proper sub-sequence of the sequence.
 Thus, the sequential machine must remember that the
first two one's have occurred as it receives another
symbol.
 Also, the sequence 1101101 contains 1101 as both an
initial subsequence and a final subsequence with some
overlap, i. e., 1101101 or 1101101.
 And, the 1 in the middle, 1101101, is in both
subsequences.
 The sequence 1101 must be recognized each time it
occurs in the input sequence.

Chapter 6 - Part 2 9
Example: Recognize 1101
 Define states for the sequence to be recognized:
• assuming it starts with first symbol,
• continues through each symbol in the sequence to be recognized,
and
• uses output 1 to mean the full sequence has occurred,
• with output 0 otherwise.
 Starting in the initial state (Arbitrarily named "A"):
• Add a state that recognizes
the first "1." 1/0
A B
• State "A" is the initial state, and state "B" is the state which
represents the fact that the "first" one in the input subsequence
has occurred. The output symbol "0" means that the full
recognized sequence has not yet occurred.

Chapter 6 - Part 2
Example: Recognize 1101 (continued)
 After one more 1, we have:
• C is the state obtained
1/0
when the input sequence
has two "1"s. A 1/0 B C
 Finally, after 110 and a 1, we have:

1/0 0/0
A 1/0 B C D
1/1

• Transition arcs are used to denote the output function (Mealy Model)
• Output 1 on the arc from D means the sequence has been recognized
• To what state should the arc from state D go? Remember: 1101101 ?
• Note that D is the last state but the output 1 occurs for the input
applied in D. This is the case when a Mealy model is assumed.

Chapter 6 - Part 2
Example: Recognize 1101 (continued)

A 1/0 B
1/0 0/0 1/1
C D
 Clearly the final 1 in the recognized sequence
1101 is a sub-sequence of 1101. It follows a 0
which is not a sub-sequence of 1101. Thus it
should represent the same state reached from the
initial state after a first 1 is observed. We obtain:

1/0 1/0 0/0

A B C D

1/1
Chapter 6 - Part 2
Example: Recognize 1101 (continued)

1/0 1/0 0/0

A B C D

1/1
 The state have the following abstract meanings:
• A: No proper sub-sequence of the sequence has
occurred.
• B: The sub-sequence 1 has occurred.
• C: The sub-sequence 11 has occurred.
• D: The sub-sequence 110 has occurred.
• The 1/1 on the arc from D to B means that the last 1
has occurred and thus, the sequence is recognized.
Chapter 6 - Part 2
Example: Recognize 1101 (continued)

 The other arcs are added to each state for

inputs not yet listed. Which arcs are missing?
1/0 1/0 0/0
A B C D

 Answer: 1/1
"0" arc from A
"0" arc from B
"1" arc from C
"0" arc from D.

Chapter 6 - Part 2
Example: Recognize 1101 (continued)

 State transition arcs must represent the fact

that an input subsequence has occurred. Thus
we get:
0/0 1/0

1/0 1/0 0/0

A B C D

0/0 1/1
0/0
 Note that the 1 arc from state C to state C
implies that State C means two or more 1's have
occurred.
Chapter 6 - Part 2
 Formulation: Find State Table
 From the State Diagram, we can fill in the State Table.
 There are 4 states, one 0/0 1/0
input, and one output.
1/0 1/0 0/0
We will choose the form A B C D
with four rows, one for
each current state. 0/0 1/1

 From State A, the 0 and 0/0

1 input transitions have

Present Next State Output
been filled in along with State x=0 x=1 x=0 x=1
the outputs. A A B 0 0
B
C
D

Chapter 6 - Part 2
Formulation: Find State Table

 From the state diagram, we complete the

state table. 0/0 1/0

1/0 1/0 0/0

A B C D

0/0 1/1
0/0
Present Next State Output
State x=0 x=1 x=0 x=1
A A B 0 0
B A C 0 0
C D C 0 0
D A B 0 1
 What would the state diagram and state table
look like for the Moore model?
Chapter 6 - Part 2
Example: Moore Model for Sequence 1101

 For the Moore Model, outputs are associated with

states.
 We need to add a state "E" with output value 1
for the final 1 in the recognized input sequence.
• This new state E, though similar to B, would generate
an output of 1 and thus be different from B.
 The Moore model for a sequence recognizer
usually has more states than the Mealy model.

Chapter 6 - Part 2
Example: Moore Model (continued)
 We mark outputs on 0 1
states for Moore model 1 1 0
A/0 B/0 C/0 D/0
 Arcs now show only
state transitions 0 1
1
 Add a new state E to
produce the output 1 0 E/1
 Note that the new state,
0
E produces the same behavior
in the future as state B. But it gives a different output
at the present time. Thus these states do represent a
different abstraction of the input history.

Chapter 6 - Part 2
Example: Moore Model (continued)

 The state table is shown 0 1

below 1 0
A/0 B/0 1 C/0 D/0
 Memory aid re more
0 1
state in the Moore model: 1
0
“Moore is More.” E/1

0
Present Next State Output
State x=0 x=1 y
A A B 0
B A C 0
C D C 0
D A E 0
E A C 1
Chapter 6 - Part 2
State Assignment – Example 1

Present Next State Output

State x=0 x=1 x=0 x=1
A A B 0 0
B A B 0 1

 How may assignments of codes with a

minimum number of bits?
• Two – A = 0, B = 1 or A = 1, B = 0
 Does it make a difference?
• Only in variable inversion, so small, if any.

Chapter 6 - Part 2
State Assignment – Example 2

Present Next State Output

State x=0 x=1 x=0 x=1
A A B 0 0
B A C 0 0
C D C 0 0
D A B 0 1
 How may assignments of codes with a
minimum number of bits?
• 4  3  2  1 = 24
 Does code assignment make a difference in
cost?

Chapter 6 - Part 2
State Assignment – Example 2 (continued)
 Assignment 1: A = 0 0, B = 0 1, C = 1 0, D = 1 1
 The resulting coded state table:

Present Next State Output

State x = 0 x = 1 x = 0 x = 1

00 00 01 0 0
01 00 10 0 0
10 11 10 0 0
11 00 01 0 1

Chapter 6 - Part 2
State Assignment – Example 2 (continued)
 Assignment 2: A = 0 0, B = 0 1, C = 1 1, D = 1 0
 The resulting coded state table:
Present Next State Output
State x = 0 x = 1 x = 0 x = 1
00 00 01 0 0
01 00 11 0 0
11 10 11 0 0
10 00 01 0 1

Chapter 6 - Part 2
Find Flip-Flop Input and Output
Equations: Example 2 - Assignment 1
 Assume D flip-flops
 Interchange the bottom two rows of the state
table, to obtain K-maps for D1, D2, and Z:
D1 D2 Z
X X X
0 0 0 1 0 0
0 1 0 0 0 0
Y2 Y2 Y2
0 0 0 1 0 0
Y1 Y1 Y1
1 1 1 0 0 1

Chapter 6 - Part 2
Optimization: Example 2: Assignment 1

 Performing two-level optimization:

D1 D2 Z
X X X
0 0 0 1 0 0
0 1 0 0 0 0
Y2 Y2 Y2
0 0 0 1 0 0
Y1 Y1 Y1
1 1 1 0 0 1
D1 = Y1Y2 + XY1Y2
D2 = XY1Y2 + XY1Y2 + XY1Y2
Z = XY1Y2 Gate Input Cost = 22
Chapter 6 - Part 2
Find Flip-Flop Input and Output
Equations: Example 2 - Assignment 2
 Assume D flip-flops
 Obtain K-maps for D1, D2, and Z:

D1 D2 Z
X X X
0 0 0 1 0 0
0 1 0 1 0 0
Y2 Y2 Y2
1 1 0 1 0 0
Y1 Y1 Y1
0 0 0 1 0 1

Chapter 6 - Part 2
Optimization: Example 2: Assignment 2

 Performing two-level optimization:

D1 D2 Z
X X X
0 0 0 1 0 0
0 1 0 1 0 0
Y2 Y2 Y2
1 1 0 1 0 0
Y1 Y1 Y1
0 0 0 1 0 1
D1 = Y1Y2 + XY2 Gate Input Cost = 9
D2 = X Select this state assignment for
Z = XY1Y2 completion of the design
Chapter 6 - Part 2
 Map Technology
 Library:  Initial Circuit:
• D Flip-flops
with Reset
Y1
(not inverted) D

• NAND gates
C
with up to 4 R
inputs and Z
inverters
Y2
X D

Clock C
R
Reset

Chapter 6 - Part 2
Mapped Circuit - Final Result

Y1
D

C
R

Y2
X D

Clock C
R
Reset

Chapter 6 - Part 2
Sequential Design: Example 3

 Design a sequential modulo 3 accumulator for 2-

bit operands
 Definitions:
• Modulo n adder - an adder that gives the result of the
addition as the remainder of the sum divided by n
 Example: 2 + 2 modulo 3 = remainder of 4/3 = 1
• Accumulator - a circuit that “accumulates” the sum of
its input operands over time - it adds each input
operand to the stored sum, which is initially 0.
 Stored sum: (Y1,Y0), Input: (X1,X0), Output:
(Z1,Z0)

Chapter 6 - Part 2
Example 3 (continued)

 Complete the state diagram:

00
Reset A/00

01

C/10 B/01

Chapter 6 - Part 2
Example 3 (continued)
 Complete the state table
X1X0 00 01 11 10 Z1Z0
Y1Y0

Y1(t+1), Y1(t+1), Y1(t+1), Y1(t+1),

Y0(t+1) Y0(t+1) Y0(t+1) Y0(t+1)
A (00) 00 X 00
B (01) X 01
- (11) X X X X 11
 C (10)
State Assignment: (Y1,Y0) = (Z1,Z0) X 10
 Codes are in gray code order to ease use of K-maps in the next step

Chapter 6 - Part 2
 Example 3 (continued)
 Find optimized flip-flop input equations for D flip-flops
D1 X1 D0 X1
X X
X X
Y0 Y0
X X X X X X X X
Y1 Y1
X X
X0 X0
 D1 =
 D0 =

Chapter 6 - Part 2
 Circuit - Final Result with AND, OR, NOT

X1 Y1
D Z1
X0

C
R

Y0
D Z0

C
R
Reset
Clock

Chapter 6 - Part 2
Other Flip-Flop Types
 J-K and T flip-flops
• Behavior
• Implementation
 Basic descriptors for understanding and
using different flip-flop types
• Characteristic tables
• Characteristic equations
• Excitation tables
 For actual use, see Reading Supplement - Design
and Analysis Using J-K and T Flip-Flops
Chapter 6 - Part 2
J-K Flip-flop
 Behavior
• Same as S-R flip-flop with J analogous to S and K
analogous to R
• Except that J = K = 1 is allowed, and
• For J = K = 1, the flip-flop changes to the opposite
state
• As a master-slave, has same “1s catching” behavior
as S-R flip-flop
• If the master changes to the wrong state, that state
will be passed to the slave
 E.g., if master falsely set by J = 1, K = 1 cannot reset it
during the current clock cycle

Chapter 6 - Part 2
J-K Flip-flop (continued)
 Implementation  Symbol
• To avoid 1s catching
behavior, one solution
used is to use an J
edge-triggered D as
the core of the flip-flop C
K
J D

K
C

Chapter 6 - Part 2
T Flip-flop
 Behavior
• Has a single input T
 For T = 0, no change to state
 For T = 1, changes to opposite state
 Same as a J-K flip-flop with J = K = T
 As a master-slave, has same “1s catching”
behavior as J-K flip-flop
 Cannot be initialized to a known state using the
T input
• Reset (asynchronous or synchronous) essential

Chapter 6 - Part 2
T Flip-flop (continued)
 Implementation  Symbol
• To avoid 1s catching
behavior, one solution
used is to use an T
edge-triggered D as
the core of the flip-flop

C
D
T

Chapter 6 - Part 2
Basic Flip-Flop Descriptors
 Used in analysis
• Characteristic table - defines the next state of
the flip-flop in terms of flip-flop inputs and
current state
• Characteristic equation - defines the next state
of the flip-flop as a Boolean function of the
flip-flop inputs and the current state
 Used in design
• Excitation table - defines the flip-flop input
variable values as function of the current state
and next state
Chapter 6 - Part 2
D Flip-Flop Descriptors

 Characteristic Table
D Q(t+1) Operation
0 0 Reset
1 1 Set

 Characteristic Equation
Q(t+1) = D
 Excitation Table
Q(t+1) D Operation
0 0 Reset
1 1 Set

Chapter 6 - Part 2
T Flip-Flop Descriptors

 Characteristic Table
T Q(t+1) Operation

0 Q(t) No change
1 Q(t) Complement

 Characteristic Equation
Q(t+1) = T  Q
 Excitation Table

Q(t 1) T Operation
+
Q(t) 0 No change
Q(t) 1 Complement

Chapter 6 - Part 2
S-R Flip-Flop Descriptors
 Characteristic Table
S R Q(t+1) Operation

0 0 Q(t) No change
0 1 0 Reset
1 0 1 Set
1 1 ? Undefined
 Characteristic Equation
Q(t+1) = S + R Q, S.R = 0
 Excitation Table
Q(t) Q(t+1) S R Operation

0 0 0 X No change
0 1 1 0 Set
1 0 0 1 Reset
1 1 X 0 No change
Chapter 6 - Part 2
J-K Flip-Flop Descriptors
 Characteristic Table
J K Q(t+1) Operation

0 0 Q(t) No change
0 1 0 Reset
1 0 1 Set
1 1 Q(t) Complement
 Characteristic Equation
Q(t+1) = J Q + K Q
 Excitation Table
Q(t) Q(t+1) J K Operation

0 0 0 X No change
0 1 1 X Set
1 0 X 1 Reset
1 1 X 0 No Change

Chapter 6 - Part 2
 Flip-flop Behavior Example
 Use the characteristic tables to find the output waveforms
for the flip-flops shown:
Clock

D,T

D QD
C

T QT

Chapter 6 - Part 2
 Flip-Flop Behavior Example
(continued)
 Use the characteristic tables to find the output waveforms
for the flip-flops shown:
Clock

S,J

R,K

S QSR ?
C
R

J QJK
C
K

Chapter 6 - Part 2
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Chapter 6 - Part 2