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System Verilog

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12 views

System Verilog

Uploaded by

As Venkivenkatesh
Copyright
© © All Rights Reserved
Available Formats
Download as PPTX, PDF, TXT or read online on Scribd
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Randomization and

coverage
Connecting the Testbench and
Design
• There are several steps needed to verify a design: generate stimulus,
capture responses, determine correctness, and measure progress.
• Testbench wraps around the design, sending in stimulus and capturing
the design’s response.
• The key concept is that the testbench simulates everything not in the
design under test.
• Your testbench needs a higher-level way to communicate with the
design than Verilog’s ports and the error-prone pages of connections.
Communication between the
testbench and DUT
• Here is a diagram of the top level design including a testbench,
arbiter, clock generator, and the signals that connect them.
• This is a trivial design, so you can concentrate on the SystemVerilog
concepts and not get bogged down in the design.
Communication with ports

Grant <= 2’b01;


The Interface Construct
• Designs are so complex that even the communication between them
may need to be separated out into separate entities.
• To model this, SystemVerilog uses the interface construct.
• Interface construct helps in connectivity, synchronization, and
optionally, the functionality of the communication between two or
more blocks.
• They connect design blocks and/or testbenches.
Using an interface to simplify
connections
Connecting interfaces and ports
Interface trade-offs
• The advantages to using an interface are as • The disadvantages of using an interface are as
follows. follows.
• An interface is ideal for design reuse. When two • For point-to-point connections, interfaces with
blocks communicate with a specified protocol modports are almost as verbose as using ports with
lists of signals. But all the declarations are still in one
using two or more signals, use an interface. If central location, reducing the chance for making an
signals are repeated over and over, as in a error.
networking switch, use a virtual interface. • You must now use the interface name in addition to
• The interface takes the jumble of signals that the signal name, possibly making the modules more
you declare over and over in every module or verbose.
program and puts it in a central location, • In the scenario of connecting two design blocks with a
reducing the possibility of misconnecting signals. unique protocol that will not be reused, interfaces
• To add a new signal, you just have to declare it may be more work than just wiring together the ports.
once in the interface, not in higher-level • It is difficult to connect two different interfaces. A new
modules, once again reducing errors. interface (bus_if) may contain all the signals of an
existing one (arb_if), plus new signals (address, data,
• Modports allow a module to easily tap a subset etc.). But since interfaces cannot be hierarchical, you
of signals from an interface. You can specify have to break out the individual signals and drive
signal direction for additional checking. them appropriately.
Stimulus Timing
• Controlling timing of synchronous signals with a clocking block
• @(posedge clk) or @(posedge clk1 or negedge clk2).
• Default
• @my_interface.cb
Cont...
• Timing problems in Verilog
• Testbench – design race condition
The program block and timing
regions
Interface Driving and Sampling
• Interface synchronization
• Interface signal sample
• Interface signal drive
The clock generator
SystemVerilog Assertions
• Procedural assertions
• Customizing the assertion actions
• Concurrent assertions

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