Session 6: Additional features

● Task and

Function
automatic
Parameter Overloading
defparam and #
operator
Compiler directives
`define and its
variant Disable
 Task and Functions

□ Tasks and functions provide the ability to reuse the

common piece of code from several different places in
a design

□They are analogous to subroutines in other

languages
Verilog HDL Task
● Must be declared within a module, and are local to that module.
● Tasks are declared with the keywords task and endtask
● Must be called from an initial procedure, an always procedure or
another task.
● May have any number of input, output or inout ports, including none.
● Tasks may contain time controls/Delays) (#, @, or wait).
● Ifa variable is declared within the task, it is local to the task
and can’t be used outside the task.
● Tasks can drive global variables if no local variables are
declared.
● Tasks are called with statements and cannot be
used in an expression.
Task Syntax
A task doesn’t need to have arguments in port list, and there are different types of
task declaration:

The task name is like a module name

task [name]; task [name] (in/out [port_list]); task [name] ();

input [port_list]; begin begin
inout [port_list]; [statements] [statements]
output [port_list]; end end
begin endtask endtask
[statements]
Calling the task:
end Correspond to the
……. ports of the task
endtask [name] ([arguments]);
…….
 Types of
Tasks
❖ static task: declared with task … endtask.
❖ automatic (reentrant, dynamic) : declared with task automatic …
endtask.

❖ Features of static tasks

✔ All declared items are statically allocated.
✔ Static tasks items can be shared across all uses of the task executing concurrently
within a module.

❖ Features of automatic (reentrant, dynamic) tasks

✔ All declared items are dynamically allocated for each invocation.
✔ They are deallocated at the end of the task invocation
Verilog HDL: static Task
example 1
/ /an example illustrating how to count the zeros
in a byte. module zero_count_task (data, out);
input [7:0] data;
output reg [3:0] out; // output declared as
register always @(data)
count_0s_in_byte(data, out); // calling
the task

task count_0s_in_byte(input [7:0] data, output reg [3:0] count); // task

declaration from here. integer i;
begin // task
body count =
0;
for (i = 0; i <=
7; i = i + 1)
if (data[i] == 0) count=
count + 1; end endtask
endmodule
Verilog HDL: static Task example 2
module task_calling(adc_a, adc_b, adc_a_conv, adc_b_conv);
input [7:0] adc_a, adc_b;
output [7:0] adc_a_conv, adc_b_conv;
reg [7:0] adc_a_conv, adc_b_conv;
task convert;
input [7:0] adc_in;
output [7:0] out;
begin
out = ( 9/5 ) * (adc_in + 32)
end
The declaration of the
endtask task
always @ (adc_a)
begin
convert(adc_a, adc_a_conv);
end
endmodule This is how we call the
task
Static task example
Automatic Task Example
Verilog :
Functions
Must be declared within a module, and are local to that module
Functions are declared with the keywords function and endfunction.
It has no delay or timing control constructs (any statement introduced with #, @, or wait).
It returns a single value
It has at least one input argument.
It has no output or inout arguments
It has no non-blocking
assignments
The variables declared within the
function are local to that function.
The order of declaration within the function are considered and have to be the same as the
caller.
Functions can use and modify global variables, when no local variables are used.
May be called any place an expression value can be used
Functions can call other functions but cannot call tasks.
 Types of Functions

❖ Features of (static) functions

✔ All declared items are statically allocated.

❖ Features of automatic (recursive, dynamic) functions

✔ All function items are allocated dynamically for each recursive
call.
✔ Automatic function items cannot be accessed by hierarchical
references.
✔ Automatic functions can be invoked through use of their
hierarchical name
Verilog HDL: Function Syntax
The function name is like a module name

function name; function name (input/output/inout [port_list]);

[statements] [statements]
endfunction endfunction

Calling the function:

…….
var = [name] ([arguments]);
…….

! The function definition will implicitly create an internal variable

of the same name as the function.
Verilog HDL: Static Function Example
Function Declaration Function Calling

module simple_function (); `include "myfunction.v"

function myfunction;
input a, b, c, d; module function_calling (a, b, c, d, e, f);
begin input a, b, c, d, e ;
myfunction = ((a+b) + (c-d)); output f;
end wire f;
endfunction
endmodule assign f = (myfunction (a,b,c,d)) ? e :0;
endmodule
Automatic (Recursive) Functions: Example
// to illustrate the use of reentrant function

module factorial(input [7:0] n, output [15:0]

result); assign result = fact(7); // instantiate
the fact function

function automatic [15:0] fact; // define fact

function input [7:0] N;

// the body of
function if (N ==
1)
fact = 1;
Else
fact = N * fact(N -
1); endfunction
endmodule
 Parameter
Overloading
❑ Parameters can be defined in a module definition
❑ During compilation of Verilog modules, parameter values can be altered
separately for each module instance. This allows us to pass a
distinct set of parameter values to each module during
compilation regardless of predefined parameter values is called
parameter overloading/overriding
❑ Two ways to override a module parameter value during a module
instantiation.
1) defparam keyword (can modify only at the compilation time)
2) module instance parameter value assignment.
 defparam
●Statement
Parameter values can be changed in any module instance in
the design
● Multiple defparam statements can appear in a module.
● Any parameter can be overridden with the defparam
statement.

module hello-world;
parameter id-num = 0; //define a module identification number = 0
initial
Sdisplay("Disp1aying hello-world id number = %dM, id-num);
endmodule

module top; //change parameter values in the instantiated modules .Use defparam statement
defparam
endmodulewl.id-num = 1, w2.id-num = 2; //simulated output
hello-world wl0;
Displaying hello-world id number = 1
hello-world w2 () ;
Displaying hello-world id number = 2
Module-Instance Parameter Values
● Parameter values can be overridden when a module is
instantiated
● Parameter values can also be modified using #delay
specification with module instantiation.
● If multiple parameters are defined in the module, during
module instantiation they can be overridden by specifying the
new values in the same order as the parameter declarations in
the module.
● If an overriding value is not specified, the default parameter
declaration values are taken
Module Instance Parameter Values:
Example
//define module with
delays module bus-
master; parameter
delay1 = 2; parameter
delay2 = 3; parameter
delay3 = 7;
...
<module internals>
...
endmodule

//top-level module; instantiates two bus-master

modules module top; //Instantiate the modules with
new delay values
bus-master # (4, 5, bl ( ) ; //bl : delay1 = 4, delay2 = 5, delay3 = 6
6)
bus-master # (9,4) b2 () ; //b2: delayl1= 9, delay2 = 4, delay3 = 7
(default)
endmodule
Verilog Compiler
Directives
Conditional Compilation and Execution
Conditional Compilation :
✔ to specify that the particular portion of the code be compiled only if a certain
flag is set.
✔ Conditional compilation can be accomplished by using compiler directives
'ifdef, 'else, and 'endif..
Conditional Execution:
✔ to execute certain parts of the Verilog design only when a flag is set at run time.
✔ Conditional execution flags can be used only for behavioral statements
✔ system task keyword $teet$plusargs is used for conditional execution
Verilog Compiler directives
Verilog Compiler directives: define
Verilog Compiler directives: ifdef, else,
endif
● ' ifdef statement:
○ can appear anywhere in the design.
○ conditionally compile statements, modules, blocks, declarations, and
other compiler directives
○ 'ifdef is always closed by a corresponding ' endif

● ‘ else statement:
○ It is optional
○ A maximum of one 'else statement can accompany the 'ifdef.
● ‘ define statement:
○ used to set the conditional compilation flag in Verilog file.
▪ The Verilog compiler simply skips the portion if the conditional
compile flag is not set
▪ boolean expression is not allowed with the ' ifdef statement.
 Conditional compilation : Example
//Example 1 //Example 2
'ifdef TEST module top;
//compile module test only if text macro TEST is bus-master bl0; //instantiate module unconditionally
defined 'ifdef ADD-B2
module test; bus-master b2 () ; //b2 is instantiated conditionally if text
... macro ADD-B2 is defined
endmodule ' endif
endmodule
'else //compile the module stimulus as default

module stimulus;
...
...
endmodule

'endif //completion of 'ifdef statement

Verilog Compiler directives: undef
 Disable statement
The disable statement stops the execution of a labeled block and
skips to the end of the block

EXAMPLE:
begin :
block_name rega
= regb;
disable
block_name;
regc = rega; // this assignment will never
execute end
Session 6: End(Additional
Features)