SiC632, SiC632A

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Vishay Siliconix

50 A VRPower® Integrated Power Stage

DESCRIPTION FEATURES
The SiC632 and SiC632A are integrated power stage • Thermally enhanced PowerPAK® MLP55-31L
solutions optimized for synchronous buck applications to package
offer high current, high efficiency, and high power density • Vishay’s Gen IV MOSFET technology and a low
performance. Packaged in Vishay’s proprietary 5 mm x 5 side MOSFET with integrated Schottky diode
mm MLP package, SiC632 and SiC632A enables • Delivers up to 50 A continuous current
voltage regulator designs to deliver up to 50 A continuous
• High efficiency performance
current per phase.
• High frequency operation up to 1.5 MHz
The internal power MOSFETs utilizes Vishay’s
state-of-the-art Gen IV TrenchFET technology that delivers • Power MOSFETs optimized for 19 V input stage
industry benchmark performance to significantly reduce • 3.3 V (SiC632A) / 5 V (SiC632) PWM logic with tri-state
switching and conduction losses. and hold-off
The SiC632 and SiC632A incorporate an advanced • Zero current detect control for light load efficiency
MOSFET gate driver IC that features high current driving improvement
capability, adaptive dead-time control, an integrated • Low PWM propagation delay (< 20 ns)
bootstrap Schottky diode, a thermal warning (THWn) that • Faster disable
alerts the system of excessive junction temperature, and
• Thermal monitor flag
zero current detection to improve light load efficiency. The
drivers are also compatible with a wide range of PWM • Under voltage lockout for VCIN
controllers and supports tri-state PWM, 3.3 V (SiC632A) / • Material categorization: for definitions of compliance
5 V (SiC632) PWM logic. please see www.vishay.com/doc?99912

APPLICATIONS
• Multi-phase VRDs for computing, graphics card and memory
• Intel IMVP-8 VRPower delivery
-VCORE, VGRAPHICS, VSYSTEM AGENT Skylake, Kabylake platforms
-VCCGI for Apollo Lake platforms
• Up to 24 V rail input DC/DC VR modules

TYPICAL APPLICATION DIAGRAM

5V
VIN
V
VDR

V IN

BOOT

PHASE
VCIN
ZCD_EN#
VSWH
DSBL# Gate
PWM VOUT
PWM driver
controller
THWn
GL
CGND

D
PGN

Fig. 1 - SiC632 and SiC632A Typical Application Diagram

S17-1564-Rev. C, 09-Oct-17 1 Document Number: 62992

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PINOUT CONFIGURATION
L#

n
THW
V
DSB

VSWH

THW
VSWH

VDRV

DSB
PGN
VDR

VSW

VSW

PGN
VSW

VSW
GL

GL

L#
33

n
H

D
H

H
31 30 29 28 27 26 25 24 GL 24 25 26 27 28 29 30 31

PWM 1 23 VSWH VSWH 23 1 PWM

GL GL
ZCD_EN# 2 2 ZCD_EN#
CGND 22 VSWH 32
VSWH 22
VCIN 3 21 VSWH CGND 3 VCIN
VSWH 21
CGND 4 20 VSWH
VSWH 20 35 4 CGND
PGND
BOOT 5 19 VSWH 5 BOOT
18 VSWH VSWH 18 PGND
VSWH 19
N.C. 6 34 6 N.C.
VIN 17 VSWH VSWH 17
VIN 7 PHASE
PHAS 16 VSWH
E7 VSWH 16
8 VIN
VIN 8 9 10 11 12 13 14 15 15 14 13 12 11 10 9
D

PGN

PGN

D
PGN
N

VI
N

VGN
N
VI

PGN

PGN

PGN

PGN
D VI

VI
VI
N

N
I

D
Top view Bottom view

Fig. 2 - SiC632 and SiC632A Pin Configuration

PIN CONFIGURATION
PIN NUMBER NAME FUNCTION
1 PWM PWM input logic
2 ZCD_EN# ZCD control. Active low
3 VCIN Supply voltage for internal logic circuitry
4, 32 CGND Signal ground
5 BOOT High side driver bootstrap voltage
6 N.C. Not connected internally, can be left floating or connected to ground
7 PHASE Return path of high side gate driver
8 to 11, 34 VIN Power stage input voltage. Drain of high side MOSFET
12 to 15, 28, 35 PGND Power ground
16 to 26 VSWH Phase node of the power stage
27, 33 GL Low side MOSFET gate signal
29 VDRV Supply voltage for internal gate driver
30 THWn Thermal warning open drain output
31 DSBL# Disable pin. Active low

ORDERING INFORMATION
PART NUMBER PACKAGE MARKING CODE OPTION
SiC632CD-T1-GE3 PowerPAK MLP55-31L SiC632 5 V PWM optimized
SiC632ACD-T1-GE3 PowerPAK MLP55-31L SiC632A 3.3 V PWM optimized
SiC632DB / SiC632ADB Reference board

S17-1564-Rev. C, 09-Oct-17 2 Document Number: 62992

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PART MARKING INFORMATION

= Pin 1 Indicator

P/N = Part Number Code

P/N = Siliconix Logo

= ESD Symbol
LL F = Assembly Factory Code

FY Y = Year Code

WW = Week Code
W LL = Lot Code
W
ABSOLUTE MAXIMUM RATINGS
ELECTRICAL PARAMETER CONDITIONS LIMIT UNIT
Input voltage VIN -0.3 to +28
Control logic supply voltage VCIN -0.3 to +7
Drive supply voltage VDRV -0.3 to +7
Switch node (DC voltage) -0.3 to +28
Switch node (AC voltage) (1) VSWH -7 to +33
BOOT voltage (DC voltage) 35 V

BOOT voltage (AC voltage) (2) VBOOT 40

BOOT to PHASE (DC voltage) -0.3 to +7
BOOT to PHASE (AC voltage) (3) VBOOT-PHASE -0.3 to +8
All logic inputs and outputs
-0.3 to VCIN + 0.3
(PWM, DSBL#, and THWn)
Max. operating junction temperature TJ 150
Ambient temperature TA -40 to +125 °C
Storage temperature Tstg -65 to +150
Human body model, JESD22-A114 3000
Electrostatic discharge protection V
Charged device model, JESD22-C101 1000

Notes
• Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the
specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability
(1) The specification values indicated “AC” is V
SWH to PGND -8 V (< 20 ns, 10 μJ), min. and 33 V (< 50 ns), max.
(2) The specification value indicates “AC voltage” is V
BOOT to PGND, 40 V (< 50 ns) max.
(3) The specification value indicates “AC voltage” is V
BOOT to VPHASE, 8 V (< 20 ns) max.

RECOMMENDED OPERATING RANGE

ELECTRICAL PARAMETER MINIMUM TYPICAL MAXIMUM UNIT
Input voltage (VIN) 4.5 - 24
Drive supply voltage (VDRV) 4.5 5 5.5
V
Control logic supply voltage (VCIN) 4.5 5 5.5
BOOT to PHASE (VBOOT-PHASE, DC voltage) 4 4.5 5.5
Thermal resistance from junction to ambient - 10.6 -
°C/W
Thermal resistance from junction to case - 1.6 -

S17-1564-Rev. C, 09-Oct-17 3 Document Number: 62992

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ELECTRICAL SPECIFICATIONS
(DSBL# = ZCD_EN# = 5 V, VIN = 12 V, VDRV and VCIN = 5 V, TA = 25 °C)
LIMITS
PARAMETER SYMBOL TEST CONDITION UNIT
MIN. TYP. MAX.
POWER SUPPLY
VDSBL# = 0 V, no switching, VPWM = FLOAT - 10 -
Control logic supply current IVCIN VDSBL# = 5 V, no switching, VPWM = FLOAT - 300 - μA
VDSBL# = 5 V, fS = 300 kHz, D = 0.1 - 525 -
fS = 300 kHz, D = 0.1 - 10 15
mA
fS = 1 MHz, D = 0.1 - 35 -
Drive supply current
IVDRV - 15 -
VDSBL# = 0 V, no switching
μA
VDSBL# = 5 V, no switching - 55 -
BOOTSTRAP SUPPLY
Bootstrap diode forward voltage VF IF = 2 mA 0.4 V
PWM CONTROL INPUT (SiC632)
Rising threshold VTH_PWM_R 3.4 3.8 4.2
Falling threshold VTH_PWM_F 0.72 0.9 1.1
Tri-state voltage VTRI VPWM = FLOAT - 2.3 - V
Tri-state rising threshold VTRI_TH_R 0.9 1.15 1.38
Tri-state falling threshold VTRI_TH_F 3 3.3 3.6
Tri-state rising threshold hysteresis VHYS_TRI_R - 225 -
mV
Tri-state falling threshold hysteresis VHYS_TRI_F - 325 -
VPWM = 5 V - - 350
PWM input current IPWM
μA
VPWM = 0 V - - -350
PWM CONTROL INPUT (SiC632A)
Rising threshold VTH_PWM_R 2.2 2.45 2.7
Falling threshold VTH_PWM_F 0.72 0.9 1.1
Tri-state Voltage VTRI VPWM = FLOAT - 1.8 - V
Tri-state rising threshold VTRI_TH_R 0.9 1.15 1.38
Tri-state falling threshold VTRI_TH_F 1.95 2.2 2.45
Tri-state rising threshold hysteresis VHYS_TRI_R - 250 -
mV
Tri-state falling threshold hysteresis VHYS_TRI_F - 300 -
VPWM = 3.3 V - - 225
PWM input current IPWM
μA
VPWM = 0 V - - -225
TIMING SPECIFICATIONS
Tri-state to GH/GL rising - 30 -
propagation delay tPD_TRI_R
Tri-state hold-off time tTSHO - 130 -
GH - turn off propagation delay tPD_OFF_GH - 15 -
GH - turn on propagation delay No load, see fig. 4
- 10 -
(dead time rising) tPD_ON_GH
ns
GL - turn off propagation delay tPD_OFF_GL - 13 -
GL - turn on propagation delay
- 10 -
(dead time falling) tPD_ON_GL

DSBL# Lo to GH/GL falling Fig. 5 - 15 -

propagation delay tPD_DSBL#_F
PWM minimum on-Time tPWM_ON_MIN 30 - -

S17-1564-Rev. C, 09-Oct-17 4 Document Number: 62992

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DOCUMENT ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000
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ELECTRICAL SPECIFICATIONS
(DSBL# = ZCD_EN# = 5 V, VIN = 12 V, VDRV and VCIN = 5 V, TA = 25 °C)
LIMITS
PARAMETER SYMBOL TEST CONDITION UNIT
MIN. TYP. MAX.
DSBL# ZCD_EN# INPUT
VIH_DSBL# Input logic high 2 - -
DSBL# logic input voltage
VIL_DSBL# Input logic low - - 0.8
V
VIH_ZCD_EN# Input logic high 2 - -
ZCD_EN# logic input voltage
VIL_ZCD_EN# Input logic low - - 0.8
PROTECTION
VCIN rising, on threshold - 3.7 4.1
Under voltage lockout VUVLO
V
VCIN falling, off threshold 2.7 3.1 -
Under voltage lockout hysteresis VUVLO_HYST - 575 - mV
THWn flag set (2) TTHWn_SET - 160 -
THWn flag clear (2) TTHWn_CLEAR - 135 - °C
THWn flag hysteresis (2) TTHWn_HYST - 25 -
THWn output low VOL_THWn ITHWn = 2 mA - 0.02 - V
Notes
(1) Typical limits are established by characterization and are not production tested

(2) Guaranteed by design

DETAILED OPERATIONAL DESCRIPTION

PWM Input with Tri-state Function Diode Emulation Mode (ZCD_EN#)
The PWM input receives the PWM control signal from the When ZCD_EN# pin is driven below VIL_ZCD_EN#. diode
VR controller IC. The PWM input is designed to be emulation mode is enabled. If the PWM signal switches
compatible with standard controllers using two state logic below VTH_PWM_F then the LS MOSFET is under control of
(H and L) and advanced controllers that incorporate tri- the ZCD (zero crossing detect) comparator. If, after the
state logic (H, L and tri-state) on the PWM output. For internal blanking delay, the inductor current becomes less
two state logic, the PWM input operates as follows. When than or = 0 the low side is turned OFF. Light load efficiency
PWM is driven above VPWM_TH_R the low side is turned OFF is improved by avoiding discharge of output capacitors. If
and the high side is turned ON. When PWM input is driven both high side and low side MOSFETs are required to be
below VPWM_TH_F the high side is turned OFF and the low turned off, regardless of inductor current, the PWM input
side is turned ON. For tri-state logic, the PWM input should be tri-stated.
operates as previously stated for driving the MOSFETs
Thermal Shutdown Warning (THWn)
when PWM is logic high and logic low. However, there is a
third state that is entered as the PWM output of tri-state The THWn pin is an open drain signal that flags the
compatible controller enters its high impedance state presence of excessive junction temperature. Connect
during shut-down. The high impedance state of the with a maximum of 20 k, to VCIN. An internal
controller’s PWM output allows the SiC632 and SiC632A to temperature sensor detects the junction temperature.
pull the PWM input into the tri-state region (see definition The temperature threshold is 160 °C. When this
of PWM logic and Tri-State, fig. 4). If the PWM input junction temperature is exceeded the THWn flag is
stays in this region for the Tri-state Hold-Off Period, set. When the junction temperature drops below 135
tTSHO, both high side and low side MOSFETs are turned °C the device will clear the THWn signal. The SiC632
OFF. The function allows the VR phase to be disabled and SiC632A do not stop operation when the flag is
without negative output voltage swing caused by inductor set. The decision to shutdown must be made by an
ringing and saves a Schottky diode clamp. The PWM and external thermal control function.
tri-state regions are separated by hysteresis to prevent false Voltage Input (VIN)
triggering. The SiC632A incorporates PWM voltage
thresholds that are compatible with 3.3 V logic and the This is the power input to the drain of the high side power
SiC632 thresholds are compatible with 5 V logic. MOSFET. This pin is connected to the high power
intermediate BUS rail.
Disable (DSBL#)
In the low state, the DSBL# pin shuts down the driver IC
and disables both high side and low side MOSFETs. In this
state, standby current is minimized. If DSBL# is left
unconnected, an internal pull-down resistor will pull the
pin to CGND and shut down the IC.
S17-1564-Rev. C, 09-Oct-17 5 Document Number: 62992
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Switch Node (VSWH and PHASE) Bootstrap Circuit (BOOT)
The switch node, VSWH, is the circuit power stage output. The internal bootstrap diode and an external bootstrap
This is the output applied to the power inductor and output capacitor form a charge pump that supplies voltage to the
filter to deliver the output for the buck converter. The BOOT pin. An integrated bootstrap diode is incorporated so
PHASE pin is internally connected to the switch node VSWH. that only an external capacitor is necessary to complete the
This pin is to be used exclusively as the return pin for bootstrap circuit. Connect a boot strap capacitor with one
the BOOT capacitor. A 20 k resistor is connected leg tied to BOOT pin and the other tied to PHASE pin.
between GH (the high side gate) and PHASE to provide a Shoot-Through Protection and Adaptive Dead Time
discharge path for the HS MOSFET in the event that VCIN The SiC632 and SiC632A have an internal adaptive logic to
goes to zero while VIN is still applied. avoid shoot through and optimize dead time. The shoot
Ground Connections (CGND and PGND) through protection ensures that both high side and low side
MOSFETs are not turned ON at the same time. The adaptive
PGND (power ground) should be externally connected dead time control operates as follows. The high side and
to CGND (signal ground). The layout of the printed circuit low side gate voltages are monitored to prevent the
board should be such that the inductance separating CGND MOSFET turning ON from tuning ON until the other
and PGND is minimized. Transient differences due to MOSFET's gate voltage is sufficiently low (< 1 V). Built in
inductance effects between these two pins should not delays also ensure that one power MOSFET is completely
exceed 0.5 V OFF, before the other can be turned ON. This feature helps
to adjust dead time as gate transitions change with respect
Control and Drive Supply Voltage Input (VDRV, VCIN) to output current and temperature.
VCIN is the bias supply for the gate drive control IC. VDRV is Under Voltage Lockout (UVLO)
the bias supply for the gate drivers. It is recommended to
separate these pins through a resistor. This creates a low During the start up cycle, the UVLO disables the gate
pass filtering effect to avoid coupling of high frequency gate drive holding high side and low side MOSFET gates low
drive noise into the IC. until the supply voltage rail has reached a point at which
the logic circuitry can be safely activated. The SiC632,
SiC632A also incorporates logic to clamp the gate drive
signals to zero when the UVLO falling edge triggers the
shutdown of the device. As an added precaution, a 20 k
resistor is connected between GH (the high side gate) and
PHASE to provide a discharge path for the HS MOSFET.

FUNCTIONAL BLOCK DIAGRAM

THWn BOOT
VIN

VDRV
Thermal monitor
& warning

VCIN UVLO

DISB#

VCIN - 20K
+ PHASE
PWM logic Anti-cross Vref = 1 V
control & conduction G
PWM state control L
machine logic - VSWH
+
Vref = 1 V
VDRV

CGND

VSWH
PGND

ZCD_EN# PGND

GL

Fig. 3 - SiC632 and SiC632A Functional Block Diagram

S17-1564-Rev. C, 09-Oct-17 6 Document Number: 62992
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DEVICE TRUTH TABLE

DSBL# ZCD_EN# PWM GH GL
Open X X L L
L X X L L
H, IL > 0 A
H L L L
L, IL < 0 A
H L H H L
H L Tri-state L L
H H L L H
H H H H L
H H Tri-state L L

PWM TIMING DIAGRAM

VTH_PWM_R
VTH_TRI_F
VTH_TRI_R
VTH_PWM_F
PWM
t PD_OFF_GL
t TSHO

GL
t PD_ON_GL
t PD_TRI_R

t TSHO
t PD_ON_GH t PD_OFF_GH

t PD_TRI_R

GH

Fig. 4 - Definition of PWM Logic and Tri-state

DSBL# PROPAGATION DELAY

PWM PWM

DSBL# Disable DSBL#

GH GH

GL GL

t t

DSBL#Low to GH Falling Propagation Delay DSBL# Low to GL Falling Propagation Delay

Fig. 5 - DSBL# Falling Propagation Delay

S17-1564-Rev. C, 09-Oct-17 7 Document Number: 62992

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ELECTRICAL CHARACTERISTICS
Test condition: VIN = 13 V, DSBL# = VDRV = VCIN = 5 V, ZCD_EN# = 5 V, VOUT = 1 V, LOUT = 250 nH (DCR = 0.32 m), TA = 25 °C,
natural convection cooling (All power loss and normalized power loss curves show SiC632 and SiC632A losses only unless otherwise stated)

94 55

90 50

86 45
500 kHz
750 kHz 500 kHz

Output Current, IOUT (A)

82 40
Efficiency (%)

1 MHz
1 MHz
78 35

74 30

70 25
Complete converter efficiency
66 PIN = [(VIN x IIN) + 5 V x (IVDRV + IVCIN)] 20
POUT = VOUT x IOUT, measured at output capacitor
62 15
0 5 10 15 20 25 30 35 40 45 50 0 15 30 45 60 75 90 105 120 135 150
Output Current, IOUT (A) PCB Temperature, TPCB (°C)

Fig. 6 - Efficiency vs. Output Current (VIN = 12.6 V) Fig. 9 - Safe Operating Area

5.0 16.0
IOUT = 25A
4.5 14.0

4.0 12.0
Power Loss, PL (W)

Power Loss, PL (W)

3.5 10.0
1 MHz

3.0 8.0

2.5 6.0 750 kHz

2.0 4.0

1.5 2.0 500 kHz

1.0 0.0
200 300 400 500 600 700 800 900 1000 1100 0 5 10 15 20 25 30 35 40 45
Switching Frequency, fs (KHz) Output Current, IOUT (A)

Fig. 7 - Power Loss vs. Switching Frequency (VIN = 12.6 V) Fig. 10 - Power Loss vs. Output Current (VIN = 12.6 V)

98 94
500 kHz
500 kHz
94 90

90
86
86
Efficiency (%)

82
Efficiency (%)

82 750 kHz 750 kHz

1 MHz 78 1 MHz
78
74
74
70
70
Complete converter efficiency Complete converter efficiency
PIN = [(VIN x IIN) + 5 V x (IVDRV + IVCIN)] 66 PIN = [(VIN x IIN) + 5 V x (IVDRV + IVCIN)]
66
POUT = VOUT x IOUT, measured at output capacitor POUT = VOUT x IOUT, measured at output capacitor
62 62
0 5 10 15 20 25 30 35 40 45 50 0 5 10 15 20 25 30 35 40 45 50
Output Current, IOUT (A) Output Current, IOUT (A)

Fig. 8 - Efficiency vs. Output Current (VIN = 9 V) Fig. 11 - Efficiency vs. Output Current (VIN = 19 V)

S17-1564-Rev. C, 09-Oct-17 8 Document Number: 62992

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ELECTRICAL CHARACTERISTICS
Test condition: VIN = 13 V, DSBL# = VDRV = VCIN = 5 V, ZCD_EN# = 5 V, VOUT = 1 V, LOUT = 250 nH (DCR = 0.32 m), TA = 25 °C,
natural convection cooling (All power loss and normalized power loss curves show SiC632 and SiC632A losses only unless otherwise stated)

4.2 0.40

4.0 0.35
IF = 2 mA

BOOT Diode Forward Voltage, VF (V)

Control Logic Supply Voltage, VCIN (V)

3.8 VUVLO_RISING 0.30

3.6 0.25

3.4 0.20

3.2 0.15

3.0 0.10
VUVLO_FALLING

2.8 0.05

2.6 0.00
-60 -40 -20 0 20 40 60 80 100 120 140 -60 -40 -20 0 20 40 60 80 100 120 140
Temperature (°C) Temperature (°C)
Fig. 12 - UVLO Threshold vs. Temperature Fig. 15 - Boot Diode Forward Voltage vs. Temperature

3.20 3.20

2.85 2.85
Control Logic Supply Voltage, VPWM (V)

PWM Threshold Voltage, VPWM (V)

VTH_PWM_R VTH_PWM_R
2.50 2.50
VTRI_TH_F
2.15 VTRI_TH_F 2.15

1.80 1.80
VTRI VTRI
1.45 1.45
VTRI_TH_R
VTRI_TH_R
1.10 1.10

0.75 0.75
VTH_PWM_F VTH_PWM_F
0.40 0.40
-60 -40 -20 0 20 40 60 80 100 120 140 4.5 4.6 4.7 4.8 4.9 5.0 5.1 5.2 5.3 5.4 5.5
Temperature (°C) Driver Supply Voltage, VCIN (V)
Fig. 13 - PWM Threshold vs. Temperature (SiC632A) Fig. 16 - PWM Threshold vs. Driver Supply Voltage (SiC632A)

5.0 5.00

4.5 4.50
VTH_PWM_R
PWM Threshold Voltage, VPWM (V)

4.0 VTH_PWM_R 4.00

Control Logic Supply Voltage, VPWM (V)

3.5 3.50
VTRI_TH_F
3.0 VTRI_TH_F 3.00

2.5 VTRI 2.50 VTRI

2.0 2.00

1.5 1.50
VTRI_TH_R VTRI_TH_R
1.0 1.00

0.5 VTH_PWM_F 0.50 VTH_PWM_F

0.0 0
-60 -40 -20 0 20 40 60 80 100 120 140 4.5 4.6 4.7 4.8 4.9 5.0 5.1 5.2 5.3 5.4 5.5
Temperature (°C) Driver Supply Voltage, VCIN (V)

Fig. 14 - PWM Threshold vs. Temperature (SiC632) Fig. 17 - PWM Threshold vs. Driver Supply Voltage (SiC632)

S17-1564-Rev. C, 09-Oct-17 9 Document Number: 62992

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ELECTRICAL CHARACTERISTICS
Test condition: VIN = 13 V, DSBL# = VDRV = VCIN = 5 V, ZCD_EN# = 5 V, VOUT = 1 V, LOUT = 250 nH (DCR = 0.32 m), TA = 25 °C,
natural convection cooling (All power loss and normalized power loss curves show SiC632 and SiC632A losses only unless otherwise stated)

1.7 2.20

1.6 2.00
VIH_DSBL#
DSBL# Threshold Voltage, VDSBL# (V)

ZCD_EN# Threshold Voltage, VZCD_EN# (V)

1.5 1.80

VIH_ZCD_EN#_R
1.4 1.60

1.3 1.40

1.2 1.20

1.1 1.00 VIL_ZCD_EN#_F

1.0 VIL_DSBL# 0.80

0.9 0.60
-60 -40 -20 0 20 40 60 80 100 120 140 4.5 4.6 4.7 4.8 4.9 5.0 5.1 5.2 5.3 5.4 5.5
Temperature (°C) Driver Supply Voltage, VCIN (V)
Fig. 18 - DSBL# Threshold vs. Temperature Fig. 21 - ZCD_EN# Threshold vs. Driver Supply Voltage

1.7 80

1.6 VIH_DSBL# 70
DSBL# Threshold Voltage, VDSBL# (V)

VDSBL# = 0 V
Driver Supply Current, IVDVR & IVCIN (V)

1.5 60

1.4 50

1.3 40

1.2 30

1.1 20

1.0 VIL_DSBL# 10

0.9 0
4.5 4.6 4.7 4.8 4.9 5.0 5.1 5.2 5.3 5.4 5.5 -60 -40 -20 0 20 40 60 80 100 120 140
Driver Supply Voltage, VCIN (V) Temperature (°C)

Fig. 19 - DSBL# vs. Driver Input Voltage Fig. 22 - Driver Shutdown Current vs. Temperature

10.8 390

10.7 380
DSBL# Pull-Down Current, IDSBL# (uA)

Driver Supply Current, IVDVR & IVCIN (V)

10.6 370

10.5 360

10.4 350 VPWM = FLOAT

10.3 340

10.2 330

10.1 320

10.0 310
-60 -40 -20 0 20 40 60 80 100 120 140 -60 -40 -20 0 20 40 60 80 100 120 140
Temperature (°C) Temperature (°C)

Fig. 20 - DSBL# Pull-Down Current vs. Temperature Fig. 23 - Driver Supply Current vs. Temperature

S17-1564-Rev. C, 09-Oct-17 10 Document Number: 62992

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PCB LAYOUT RECOMMENDATIONS
Step 1: VIN/GND Planes and Decoupling Step 3: VCIN/VDRV Input Filter

VSWH

P CVDRV
G
N
D

PGND

VIN CVCIN
CGND

VIN plane
PGND plane

1. Layout VIN and PGND planes as shown above 1. The VCIN/VDRV input filter ceramic cap should be placed
2. Ceramic capacitors should be placed right between VIN very close to IC. It is recommended to connect two
caps separately.
and PGND, and very close to the device for
best decoupling effect 2. CVCIN cap should be placed between pin 3 and pin 4
3. Difference values / packages of ceramic capacitors (CGND of driver IC) to achieve best noise filtering.
should be used to cover entire decoupling spectrum 3. CVDRV cap should be placed between pin 28 (PGND of
e.g. 1210, 0805, 0603 and 0402 driver IC) and pin 29 to provide maximum
4. Smaller capacitance value, closer to device VIN pin(s) instantaneous driver current for low side MOSFET
- better high frequency noise absorbing during switching cycle
Step 2: VSWH Plane 4. For connecting CVCIN analog ground, it is recommended
to use large plane to reduce parasitic inductance.
Step 4: BOOT Resistor and Capacitor Placement
VSWH
VSWH
Snubber

Cboot

Rboot

PPGND Plane
GND plane

1. Connect output inductor to DrMOS with large plane to

lower the resistance 1. These components need to be placed very close to IC,
2. If any snubber network is required, place the right between PHASE (pin 7) and BOOT (pin 5).
components as shown above and the network can 2. To reduce parasitic inductance, chip size 0402 can be
be placed at bottom used.

S17-1564-Rev. C, 09-Oct-17 11 Document Number: 62992

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Step 5: Signal Routing
1. Thermal relief vias can be added on the VIN and PGND
CGND pads to utilize inner layers for high current and
thermal dissipation.
2. To achieve better thermal performance, additional vias
CGND
can be put on VIN plane and PGND plane.
3. VSWH pad is a noise source and not recommended to
put vias on this plane.
4. 8 mil drill for pads and 10 mils drill for plane can be the
optional via size. Vias on pad may drain solder
during assembly and cause assembly
issue. Please consult with the assembly
house for guideline.
Step 7: Ground Connection

PGND CGND

VSWH

1. Route the PWM / ZCD_EN# / DSBL# / THWn signal

traces out of the top left corner next DrMOS pin 1.
2. PWM signal is very important signal, both signal and PGND
return traces need to pay special attention of not
letting this trace cross any power nodes on
any layer.
3. It is best to “shield” traces form power switching nodes,
e.g. VSWH, to improve signal integrity.
4. GL (pin 27) has been connected with GL pad internally
and does not need to connect externally.
Step 6: Adding Thermal Relief Vias 1. It is recommended to make single connection between
CGND and PGND and this connection can be done on
top layer.
2. It is recommended to make the whole inner 1 layer (next
to top layer) ground plane and separate them into
CGND and PGND plane.

VSWH 3. These ground planes provide shielding between noise

source on top layer and signal trace on bottom
layer.

CGND

PGND

PGND
VIN
plane

VIN plane

S17-1564-Rev. C, 09-Oct-17 12 Document Number: 62992

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 SiC632, SiC632A
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Multi-Phases VRPower PCB Layout
Following is an example for 6 phase layout. As can be seen, all the VRPower stages are lined in X-direction compactly with
decoupling caps next to them. The inductors are placed as close as possible to the SiC632 and SiC632A to minimize the PCB
copper loss. Vias are applied on all PADs (VIN, PGND, CGND) of the SiC632 and SiC632A to ensure that both electrical and thermal
performance are excellent. Large copper planes are used for all the high current loops, such as VIN, VSWH, VOUT and PGND. These
copper planes are duplicated in other layers to minimize the inductance and resistance. All the control signals are routed from
the SiC632 and SiC632A to a controller placed to the north of the power stage through inner layers to avoid the overlap of high
current loops. This achieves a compact design with the output from the inductors feeding a load located to the south of the
design as shown in the figure.

VIN

PGND

VOUT

Fig. 24 - Multi - Phase VRPower Layout Top View

VIN

PGND

VOUT

Fig. 25 - Multi - Phase VRPower Layout Bottom View

S17-1564-Rev. C, 09-Oct-17 13 Document Number: 62992

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 SiC632, SiC632A
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RECOMMENDED LAND PATTERN POWERPAK MLP55-31L

Package outline top view, transparent Land pattern for MLP55-31L

(D2-4) 5

0.75
3.4

0.3
0.33
(D2-1) (D2-5) 1.35 0.57
31 0.5
1 24
31 1.03 1.05 24
0.75
1 (D3) 0.3
23 1.13 0.4
1 23

0.55
0.3

1.6
(E3

0.4
5

0.35
(E2-2)

1.15

1.42
1.32

(e)

0.15
0.5

0.1

0.33
(K2) 0.22 2.02

1.2
1.75 0.3

(E2-1)

0.4
4.2
(K1) 0.67

3.5
5

3.05
0.07
0.25

2.15
(E2-3)

(b)

2.08
1.98

0.5
8 16 8 0.35 0.18 16

0.58

0.65
(L) 15 (L) 0.3
0.4
9
(D2-2) (D2-3) 0.4 9
0.35 0.35 0.5 15
1.92

0.3
1.03 0.75
0.5 0.65

31 24

1 23
33
32 All dimensions in millimeters

35
33

8 16

9 15

S17-1564-Rev. C, 09-Oct-17 14 Document Number: 62992

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 SiC632, SiC632A
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PACKAGE OUTLINE DRAWING MLP55-31L

0.08 C
5 6 D2-5 K12
Pin 1 dot A K7
2x K1 D2- 1
by marking 0.1 C A A1
A
D K4
2x A2 D2-4

K8
0.1 C B 24 31

E2-4

K11
23 1

K5 E2- 1
0.1 M C A B

K6
K3
MLP55-31L

K10

e ref.
(Nd-1) x
(5 mm x 5 mm)
E

E2- 3

E2-
e
4

2
16 8

b
B

L
15 K2 9
C D2-3 D2-2
K9
(Nd-1) x e
ref.
Top view Side view Bottom view

MILLIMETERS INCHES
DIM.
MIN. NOM. MAX. MIN. NOM. MAX.

A (8) 0.70 0.75 0.80 0.027 0.029 0.031

A1 0.00 - 0.05 0.000 - 0.002
A2 0.20 ref. 0.008 ref.

b (4) 0.20 0.25 0.30 0.008 0.010 0.012

D 5.00 BSC 0.196 BSC
e 0.50 BSC 0.019 BSC
E 5.00 BSC 0.196 BSC
L 0.35 0.40 0.45 0.013 0.015 0.017

N (3) 32 32

Nd (3) 8 8

Ne (3) 8 8
D2-1 0.98 1.03 1.08 0.039 0.041 0.043
D2-2 0.98 1.03 1.08 0.039 0.041 0.043
D2-3 1.87 1.92 1.97 0.074 0.076 0.078
D2-4 0.30 BSC 0.012 BSC
D2-5 1.00 1.05 1.10 0.039 0.041 0.043
E2-1 1.27 1.32 1.37 0.050 0.052 0.054
E2-2 1.93 1.98 2.03 0.076 0.078 0.080
E2-3 3.75 3.80 3.82 0.148 0.150 0.152
E2-4 0.45 BSC 0.018 BSC
K1 0.67 BSC 0.026 BSC
K2 0.22 BSC 0.008 BSC
K3 1.25 BSC 0.049 BSC

S17-1564-Rev. C, 09-Oct-17 15 Document Number: 62992

For technical questions, contact: [email protected]
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DOCUMENT ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000
 SiC632, SiC632A
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MILLIMETERS INCHES
DIM.
MIN. NOM. MAX. MIN. NOM. MAX.

K4 0.05 BSC 0.002 BSC

K5 0.38 BSC 0.015 BSC
K6 0.12 BSC 0.005 BSC
K7 0.40 BSC 0.016 BSC
K8 0.40 BSC 0.016 BSC
K9 0.40 BSC 0.016 BSC
K10 0.85 BSC 0.033 BSC
K11 0.40 BSC 0.016 BSC
K12 0.40 BSC 0.016 BSC

Vishay Siliconix maintains worldwide manufacturing capability. Products may be manufactured at one of several qualified locations. Reliability data for Silicon
Technology and Package Reliability represent a composite of all qualified locations. For related documents such as package / tape drawings, part marking, and
reliability data, see www.vishay.com/ppg?62992.

S17-1564-Rev. C, 09-Oct-17 16 Document Number: 62992

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DOCUMENT ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000
 Package Information
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Vishay Siliconix

PowerPAK® MLP55-31L Case Outline

5 6 0.08 C K12
2x D2-5
Pin 1 dot A K7
K1 D2- 1
by marking 0.10 C A A1
A
D K4

F2
2x D2-4
A2

F1

K8
0.10 C 24 31

E2-4
B

K11
23 1

K5 E2- 1
0.10 m C A B

(Nd-1) xe
K6
K3

K10
MLP55-31L

ref.
(5 mm x 5 mm)
E

E2- 3

E2- 2
e
4
16 8

b
B

L
15 9
K2
C D2- 3 D2- 2
K9
(Nd-1) x e
ref.
Top view Side view Bottom view

MILLIMETERS INCHES
DIM.
MIN. NOM. MAX. MIN. NOM. MAX.
A (8) 0.70 0.75 0.80 0.027 0.029 0.031
A1 0.00 - 0.05 0.000 - 0.002
A2 0.20 ref. 0.008 ref.
b (4) 0.20 0.25 0.30 0.008 0.010 0.012
D 4.90 5.00 5.10 0.193 0.196 0.200
e 0.50 BSC 0.019 BSC
E 4.90 5.00 5.10 0.193 0.196 0.200
L 0.35 0.40 0.45 0.013 0.015 0.017
N (3) 32 32
Nd (3) 8 8
Ne (3) 8 8
D2-1 0.98 1.03 1.08 0.039 0.041 0.043
D2-2 0.98 1.03 1.08 0.039 0.041 0.043
D2-3 1.87 1.92 1.97 0.074 0.076 0.078
D2-4 0.30 BSC 0.012 BSC
D2-5 1.00 1.05 1.10 0.039 0.041 0.043
E2-1 1.27 1.32 1.37 0.050 0.052 0.054
E2-2 1.93 1.98 2.03 0.076 0.078 0.080
E2-3 3.75 3.80 3.82 0.148 0.150 0.152
E2-4 0.45 BSC 0.018 BSC
F1 0.20 BSC 0.008 BSC
F2 0.20 BSC 0.008 BSC
K1 0.67 BSC 0.026 BSC
K2 0.22 BSC 0.008 BSC
K3 1.25 BSC 0.049 BSC
K4 0.05 BSC 0.002 BSC
K5 0.38 BSC 0.015 BSC
K6 0.12 BSC 0.005 BSC

Revision: 24-Oct-16 1 Document Number: 64909

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 Package Information
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Vishay Siliconix
MILLIMETERS INCHES
DIM.
MIN. NOM. MAX. MIN. NOM. MAX.

K7 0.40 BSC 0.016 BSC

K8 0.40 BSC 0.016 BSC
K9 0.40 BSC 0.016 BSC
K10 0.85 BSC 0.033 BSC
K11 0.40 BSC 0.016 BSC
K12 0.40 BSC 0.016 BSC
ECN: T16-0644-Rev. E, 24-Oct-16
DWG: 6025
Notes
1. Use millimeters as the primary measurement
2. Dimensioning and tolerances conform to ASME Y14.5M. - 1994
3. N is the number of terminals,
Nd is the number of terminals in X-direction, and
Ne is the number of terminals in Y-direction
4. Dimension b applies to plated terminal and is
measured between 0.20 mm and 0.25 mm from
terminal tip
5. The pin #1 identifier must be existed on the top
surface of the package by using indentation
mark or other feature of package body
6. Exact shape and size of this feature is optional
7. Package warpage max. 0.08 mm
8. Applied only for terminals

Revision: 24-Oct-16 2 Document Number: 64909

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 PAD Pattern
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Vishay Siliconix

Recommended Land Pattern

PowerPAK® MLP55-31L for SiC620, SiC620A

Top side transparent view

(not bottom view) Land pattern for MLP55-31L
(D2-4) 5

0.75
3.4

0.3
0.33
(D2-1) (D2-5) 1.35 0.57
31 0.5
1 24
31 1.03 1.05 24
0.75
1 (D3) 0.3
23 1.13
1 23

1.6
0.3

0.85
(E3

0.4

1.15
5

0.35
(E2-2)

1.42
1.32

(e)

0.15
0.5

0.33
(K2) 0.22 2.02
1.75 0.3
(E2-1)

0.4
4.2

(K1) 0.67

3.5
5

3.05
0.07
0.25

2.15
(E2-3)

(b)

2.08
1.98

0.5
8 16 8 0.35 0.18 16

0.58

0.65
(L) 15 (L) 0.3
0.4
9
(D2-2) (D2-3) 0.4 9
0.35 0.35 0.5 15
1.92

0.3
1.03 0.75
0.5 0.65

All dimensions in millimeters

31 24

1 23
33
Component for MLP55-31L
32

35 Land pattern for MLP55-31L

33

8 16

9 15

Revision: 24-Jul-17 1 Document Number: 66944

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 Legal Disclaimer Notice
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Disclaimer

ALL PRODUCT, PRODUCT SPECIFICATIONS AND DATA ARE SUBJECT TO CHANGE WITHOUT NOTICE TO IMPROVE
RELIABILITY, FUNCTION OR DESIGN OR OTHERWISE.

Vishay Intertechnology, Inc., its affiliates, agents, and employees, and all persons acting on its or their behalf (collectively,
“Vishay”), disclaim any and all liability for any errors, inaccuracies or incompleteness contained in any datasheet or in any
other disclosure relating to any product.

Vishay makes no warranty, representation or guarantee regarding the suitability of the products for any particular purpose or
the continuing production of any product. To the maximum extent permitted by applicable law, Vishay disclaims (i) any and all
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Statements regarding the suitability of products for certain types of applications are based on Vishay’s knowledge of
typical requirements that are often placed on Vishay products in generic applications. Such statements are not binding
statements about the suitability of products for a particular application. It is the customer’s responsibility to validate that a
particular product with the properties described in the product specification is suitable for use in a particular application.
Parameters provided in datasheets and / or specifications may vary in different applications and performance may vary over
time. All operating parameters, including typical parameters, must be validated for each customer application by the
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of purchase, including but not limited to the warranty expressed therein.

Except as expressly indicated in writing, Vishay products are not designed for use in medical, life-saving, or life-sustaining
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Revision: 08-Feb-17 1 Document Number: 91000