MEMORY

INTERFACING OF
8085

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Introduction to 8085

It was introduced in 1977.

It is 8-bit microprocessor.
Its actual name is 8085 A.
It is single NMOS device.
It contains 6200 transistors
approx.
Its dimensions are
164 mm x 222 mm.
It is having 40 pins Dual-
Inline-Package (DIP).
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Classification of Memory

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 Types of Semiconductor Memory
Devices
Read Only Memory (ROM) Random Access Memory (RAM)
 A memory device that maintains its data • A memory device that can be
permanently (or until the device is read and written.
reprogrammed). – Volatile: It looses its data when
◦ Non-volatile: It maintains its data the power supply is switched-off
even without power supply. – When the supply is switched-on it
 Used to store contains random data
◦ Programs such as the BIOS. • Used to store
◦ Data such as look tables – User programs that are loaded
 e.g. the bit pattern of the from a secondary memory (disk)
characters in a dot matrix printer. – Temporary data used by programs
 A ROM device can be such as variables and arrays.
1. Masked ROM (Programmed by the • A RAM device can be
manufacturer) 1. Static
2. Programmable ROM (can be 2. dynamic
program-erased-reprogrammed
many times
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 RAM Cells
Static RAM (SRAM): Dynamic RAM (DRAM):
 The basic element of a static RAM cell is the D- • DRAM stores data in the form of
Latch. electric charges in capacitors.
 Data remains stored in the cell until it is • Charges leak out, thus need to refresh
intentionally modified.
data every few ms.
 SRAM is fast (Access time: 1ns).
• DRAM is slow (Access time: 60ns).
 SRAM needs more space on the semiconductor
chip than DRAM. • DRAM needs less space on the
◦ SRAM more expensive than DRAM semiconductor chip than SRAM.
◦ SRAM needs more space than DRAM – DRAM less expensive than SRAM
 SRAM consumes power only when accessed. – DRAM needs less space than SRAM
 SRAM is used as a Cache • DRAM needs to be refreshed
• DRAM is used as the main memory

Bit Select Bit Select

Data In D Q Data Out

Data In Data Out

Write En
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RAM Cell DRAM Cell
 Basic Concepts
• A memory device can be viewed as a
single column table. Memory Address Memory
• Table index (row number) refers to the Binary Hex Contents
address of the memory. 00-0000-0000 000 10011001
• Table entries refer to the memory 00-0000-0001 001 00111000
contents or data. 00-0000-0010 002 11001001
• Each table entry is referred as a 00-0000-0011 003 00111011
memory location or as a word.
• Both the memory address and the
memory contents are binary numbers,
expressed in most cases in Hex format. 11-1111-1100 3FC 01101000
• The size of a memory device is specified 11-1111-1101 3FD 10111001
as the number of memory locations X 11-1111-1110 3FE 00110100
width or word size (in bits). 11-1111-1111 3FF 00011000
• For example a 1K X 8 memory device
has 1024 memory locations, with a 1024 X 8 (or 1KX8) Memory
width of 8 bits.

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 Address Lines
A memory device or memory chip must have three
Y00 Location 000
types of lines or connections: Address, Data, and Y01 Location 001
Control.
Y02 Location 002
Address Lines: The input lines that select a A00 Y03 Location 003
memory location within the memory device. A01
 Decoders are used, inside the memory chip, to
select a specific location An-2
 The number of address pins on a memory chip An-1 YFC Location 0FC
specifies the number of memory locations. YFD Location 0FD
 If a memory chip has 13 address pins YFE Location 0FE
YFF Location 0FF
(A0..A12), then it has:
 213 = 23 X 210 = 8K locations.
 If a memory chip has 4K locations, then it
should have N pins:
 2N = 4K = 22 X 210 = 212  N=12
address pins (A0..A11)

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 Data Lines
Data Connections: All memory devices have a set of data output pins
(for ROM devices), or input/output pins (for RAM devices).
 Most RAM chips have common bi-directional I/O connections.
 Most memory devices have 1, 8 or 16 data lines.

Data Input Lines

(DI0..DIn-1)
k- address lines k- address lines
(A0..Am-1) 2m words (A0..Am-1) 2m words
k- address lines
(A0..Am-1) 2m words
Read/Write (R/W) n-bits per Output Enable (OE) n-bits per
Read (RD) n-bits per word word
Chip Select (CS) Chip Select (CS)
Write (WR) word
Chip Select (CS)
Data Output Lines
Data Input/Output (D0..Dn-1)
Data Output Lines Lines (D0..Dn-1)
(DO0..DOn-1) (2m X n) ROM with only O/P Data
(2m X n) RAM with common I/P
(2m X n) RAM with separate I/P lines
and O/P Data lines
and O/P Data lines

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 Control Lines
Enable Connections:
 All memory devices have at least one Chip Select (CS) or Chip
Enable (CE) input, used to select or enable the memory device.
 If a device is not selected or enabled then no data can be read
from, or written into it.
 The CS or CE input is usually controlled by the microprocessor
through the higher address lines via an address decoding circuit.
Control Connections:
 RAM chips have two control input signals that specify the type of
memory operation: the Read (RD) and the Write (WR) signals.
 Some RAM chips have a common Read/ Write (R/W) signal.
 ROM chips can perform only memory read operations, thus there is
no need for a Write (WR) signal.
 In most real ROM devices the Read signal is called the Output
Enable (OE) signal.

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Requirement and structure of memory

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 Interfacing Memory
• Accessing memory can be summarized into the following three steps:
• Select the chip.
• Identify the memory register.
• Enable the appropriate buffer.

• Translating this to microprocessor domain:

• The microprocessor places a 16-bit address on the address bus.
• Part of the address bus will select the chip and the other part
will go through the address decoder to select the register.
• The signals IO/M and RD combined indicate that a memory
read operation is in progress. The MEMR signal can be used to
enable the RD line on the memory chip.

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Address decoding

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Memory Map

Maninder Kaur 13
Design a minimum system to interface the following specification.
1.32K of RAM using 2x16kb RAM Ic
2.32kB of RAM using 2x16kb ROM ic

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Memory Read operation

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Memory Read operation

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 Memory Write operation
The following sequence of event occurs when
microprocessor writes into a particular memory location.

The microprocessor sends an address of memory

location into MAR using address bus.

The microprocessor also send the data into MBR.

At the same time, microprocessor sends write signal to

activate memory for write operation.

The memory device will store the data stored into MBR
into the location whose address is in MAR.
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TIMING DIAGRAM
 Timing Diagram is a graphical
representation.
 It represents the execution time taken by

each instruction in a graphical format.

 The execution time is represented in

T-states.
CONTROL SIGNALS
INSTRUCTION CYCLE
 The time required to execute an
instruction is called instruction cycle.
MACHINE CYCLE
 The time required to access the memory
or input/output devices is called machine
cycle.
T-STATE
 The machine cycle and instruction cycle
takes multiple clock periods.
 A portion of an operation carried out in

one system clock period is called as T-

state.
MACHINE CYCLES OF 8085
The 8085 microprocessor has 5 basic machine
cycles.
They are
1. Opcode fetch cycle (4T)
2. Memory read cycle (3 T)
3. Memory write cycle (3 T)
4. I/O read cycle (3 T)
5. I/O write cycle (3 T)
MACHINE CYCLES OF 8085
 The processor takes a definite time to
execute the machine cycles. The time
taken by the processor to execute a
machine cycle is expressed in T-states.
 One T-state is equal to the time period of
the internal clock signal of the processor.
 The T-state starts at the falling edge of a
clock.
 Representation of signals in
Timing Diagram
1.Clock Signals:-As we know that the microprocessor operates with reference to clock
signals provided to it. At pins X1 and X2 we provide clock signals and this frequency
is divided by two. This frequency is called as the operating frequency.

2.Single Line Signal:-The status of single line will be either LOW or HIGH. But the
change from one state to another state is not possible in zero time.

3.Multiple Line Signals:-In Microprocessor we have multiple lines. These signals

are also called as bus signals. If a single line changes occur then we have to show a
crossing to indicate change in contents

Tri-
change Valid state Valid
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 Representation of signals in
Timing Diagram
4. Single line and single effect single:- because of single line the other signal also
changes. A changes cause change in other signal it is shown with an arrow.

5. Multiple line and single effect single:- if changes in multiple lines cause change
in other signal it is shown with an arrow.

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Op code fetching Machine cycle

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 Op-code fetching Machine
cycle
 In T1 state, the 8085 places the contents of program counter on the address bus.
 The high-order byte of the PC is placed on the A8-A15 lines. The low-order byte of
the PC is placed on the AD0 – AD7 lines which stays on only during T1.
 Microprocessor activates ALE (Address Latch Enable) which is used to latch the
low-order byte of the address in external latch before it disappears.
 In T1, 8085 also sends status signals IO/M, S1, and S0. IO/M specifies whether it is
a memory or I/O operation,
 In T2, low-order address disappears from the AD0 – AD7 lines. (However Ao –
A7remain available as they were latched during T1). In T2, 8085 sends RD signal
low to enable the addressed memory location. The memory device then places the
contents of addressed memory location on the data bus (ADo – AD7).
 During T3, 8085 loads the data from the data bus in its Instruction Register and
raises RD to high which disables the memory device.

 In T4, microprocessor decodes the opcode, and on the basis of the instruction
received, it decides whether to enter state T5 or to enter state T1 of the next
machine cycle One byte instructions those operate on eight bit data (8 bit
operand) are executed in T4.
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Memory read Machine cycle

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 Memory read Machine cycle

 The MP places the 16-bit memory address from the program

counter on address bus. At time period T1, the higher order
memory address is placed on the address lines A15 – A8. When
ALE is high, the lower address is placed on the bus AD7 – AD0.
The status signal IO/M(bar) goes low indicating the memory
operation and two status signals S1 = 1, S0 = 0 to indicate memory
read operation.
 At time period T2, the MP sends RD(bar) control line to enable the
memory read. When memory is enabled with RD(bar) signal, the
data from the addressed memory location is placed on the data bus
with ALE low.
 The data is reached at processor register during T3 state. When
data is arrived, the RD(bar) signal goes high. It causes the bus to
go into high impedance state.
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Memory Write Machine cycle

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 Memory Write Machine cycle

 In T1 state, the 8085 places the address on the address lines from stack pointer or
general purpose register pair and activates ALE signal in order to latch low-order
byte of address. During T1, 8085 sends status signals : IO/M = 0, S1 = 0 and S0 = 1
for memory write machine cycle.

 In T2, 8085 places data on the data bus and sends WR signal low for writing into
the addressed memory location.

 During T3, WR signal goes high, which disables the memory device and
terminates the write operation.

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Interfacing I/O devices with
8085

I/O I/O
Interface Devices

System Bus
8085

Memory Memory
Interface Devices
Classification of I/O devices

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 Techniques for I/O
Interfacing
• Memory-mapped I/O
• Peripheral-mapped I/O
 Memory-mapped I/O
8085 uses its 16-bit address bus to identify a
memory location
Memory address space: 0000H to FFFFH
8085 needs to identify I/O devices also
I/O devices can be interfaced using addresses from
memory space
8085 treats such an I/O device as a memory
location
This is called Memory-mapped I/O
 Peripheral-mapped I/O

8085 has a separate 8-bit addressing scheme for I/O

devices
I/O address space: 00H to FFH
This is called Peripheral-mapped I/O or I/O-mapped I/O
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8085 Communication with I/O
devices
Involves the following three steps
Identify the I/O device (with address)
Generate Timing & Control signals
Data transfer takes place
8085 communicates with a I/O device only if there is
a Program Instruction to do so
 1.Identify the I/O device (with
address)
1.Memory-mapped I/O (16-bit address)
2.Peripheral-mapped I/O (8-bit address)

2.Generate Timing & Control Signals

• Memory-mapped I/O
Reading Input: IO/M = 0, RD = 0
Write to Output: IO/M = 0, WR = 0
• Peripheral-mapped I/O
Reading Input: IO/M = 1, RD = 0
Write to Output: IO/M = 1, WR = 0

3. Data transfer takes

place
 Peripheral I/O Instructions
• IN Instruction
• Inputs data from input device into the
accumulator
• It is a 2-byte instruction
• Format: IN 8-bit port address
• Example: IN 01H

• OUT Instruction
• Outputs the contents of accumulator to an
output device
• It is a 2-byte instruction
• Format: OUT 8-bit port address
• Example: OUT 02H
----------Example
Program----------
• WAP to read a number from input port (port address 01H)
and display it on ASCII display connected to output port
(port address 02H)
IN 01H ;reads data value 03H (example)into
;accumulator, A = 03H
MVI B, 30H ;loads register B with 30H
ADD B ;A = 33H, ASCII code for 3
OUT 02H ;display 3 on ASCII display
 Memory-mapped I/O
Instructions
• I/O devices are identified by 16-bit addresses
• 8085 communicates with an I/O device as if it were one of
the memory locations
• Memory related instructions are used
• For e.g. LDA, STA
• LDA 8000H
• Loads A with data read from input device with 16-bit
address 8000H
• STA 8001H
• Stores (Outputs) contents of A to output device with 16-
bit address 8001H
 ----------Example
Program----------
• WAP to read a number from input port (port address
8000H) and display it on ASCII display connected to output
port (port address 8001H)
LDA 8000H ;reads data value 03H (example)into
;accumulator, A = 03H
MVI B, 30H ;loads register B with 30H
ADD B ;A = 33H, ASCII code for 3
STA 8001H ;display 3 on ASCII display
 I/O read/write Machine cycle

The I/O read and I/O write machine cycles

are similar to the memory read and memory
write machine cycles, respectively, except
that the I0/M signal is high for I/O read and
I/O write machine cycles. High IO/M signal
indicates that it is an I/O operation.

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I/O read Machine cycle

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I/O Write Machine cycle

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IN 8-bit port address

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Out 8bit port address

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I/O device selection
the 8085 gives 8 bit I/O address. This means it can select one of the 256 I/O ports. To
select an appropriate I/O device, it is necessary to do following things.

1. Decode the address to generate unique signal corresponding to the device address
on the bus.
2. When device address signal and control signal (IOR or IOW) both are low, generate
device select signal.
3. Use device select signal to activate the Input Output Interfacing Techniques.

device select signal

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Input device

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Output device

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Memory mapped I/O

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Maninder Kaur 64
 Th
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