Unit - 3

Input/output – I/O
Interface
to 8086

Presented By
M. Mahesh Babu
Microprocessor-Based Systems

2
Assembly Language

Prepared by M. Mahesh Babu Assistan

t-Professor.
Microprocessor Architecture
 MPU communicates with Memory and I/O
using the System Bus
 Address bus
 Unidirectional
 Memory and I/O Addresses

 Data bus
 Bidirectional
 Transfers Binary Data and Instructions

 Control lines
 Read and Write timing signals
4
Primary function of MPU
 Read Instruction from memory
 Execute instruction
 Read/Write data to memory
 Some time send result to output device
 LEDs, Monitor, Printer
 Interfacing a peripheral
 Why: To enable MPU to communicate with I/O
 Designing logic circuit H/W for a I/O
 Writing instruction (S/W)
Assembly Language Programming

 The 8086 microcomputers can employ two

types of input/output (I/O):
 1. Isolated I/O.
 2. Memory-mapped I/O.
 These I/O methods differ in how I/O ports
are mapped into the 8086's address
spaces. We will only consider isolated I/O.

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Prepared by M. Mahesh Babu Assistan
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Memory mapped I/O
Isolated Input/Output:
 In this scheme, the I/O devices are treated
separate from memory (see Fig. 8-44).
I/O ports are organized as bytes of
data;
 the memory address space contains 1M
consecutive byte addresses in the range
00000H, through FFFFFH; and the I/O
address space contains 64K consecutive
byte addresses in the range 0000H
Prepared by M. Mahesh Babu Assistan
t-Professor.
 Fig. 8-45 shows that bytes of data in two
consecutive I/O addresses could be accessed
as word-wide data. For instance, I/O
addresses 0000H, 0001H, 0002H, and 0003H
can be treated as independent byte-wide I/O
ports: ports 0, 1, 2 and 3, or as word-wide
ports 0 and 1. Prepared by M. Mahesh Babu Assistan
t-Professor.
Memory-Mapped Input/Output
 I/O devices can be placed in the memory
address space of the microcomputer.

 In this case, the MPU looks at the I/O port

as though it is a storage location in
memory.

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t-Professor.
Memory-Mapped I/O
 I/O Devices and memory share the same
address space.
 Each I/O Device is assigned a unique set of
addresses.
 When the processor places a particular address
on the address lines, the device recognizing this
address responds to the commands on the control
lines.
 The processor requests either a read or a write
operation, and the requested data is transferred
over the data lines.
 Any machine instruction that can access memory
can be used to transfer data to/from I/O devices.
 Mov datain, R0
Prepared by M. Mahesh Babu Assistan
t-Professor.
Compare between isolated I/O and
memory-mapped I/O.
isolated I/O memory-mapped I/O
 Use only the special  All memory instructions
input/output instructions. and addressing modes
(IN and OUT) are available to perform
 Faster because I/O I/O operation. (MOV, AND
instructions is specifically XCHG, SUB …….)
designed to run faster  Slower because memory
than memory instructions. instructions execute
 The memory address slower than the special
space is not affected. I/O instructions.
 Part of the memory
address space is lost.
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t-Professor.
 Parallel I/O
 I/O devices connect to processor through
PORTS
 Ports are:

registers (part of the I/O interface)

8, 16, or 32 bits wide
 Addressed in the range 0000-FFFFh

 Accessed with 2 instructions – IN, OUT

 Modes of I/O Instructions
 Direct I/O – the port address is one of the operands.
 Address must be 00-FFh.
 IN AL, 27h
 Data flows through the accumulator
 MOV AX, BX
 OUT 26h, AX ; move 16-bit data from AX to port
; 26h (AL to 26h and AH to 27h)
 Indirect I/O – the port address is preloaded into DX
 Address can be 0000-FFFFh
 String I/O – allows data to pass directly through the
accumulator (from I/O device to memory)
 80x86 I/O Instructions
Type Instruction Description
Direct IN AL, port input data to accumulator
IN AX, port port must be in range 00-FFh
IN EAX, port

OUT port, AL output data from accumulator

OUT port, AX port must be in range 00-FFh
OUT port, EAX

Indirect IN AL, DX input data to accumulator

IN AX, DX port address in DX must be in range 0000-FFFFh
IN EAX, DX

OUT DX, AL output data from accumulator

OUT DX, AX port address in DX must be in range 0000-FFFFh
OUT DX, EAX

String INSB input data to memory location DS:SI or DS:ESI

INSW port address in DX must be in range 0000-FFFFh
INSD

OUTSB output data from memory location DS:SI or DS:ESI

OUTSW port address in DX must be in range 0000-FFFFh
OUTSD
Ways to Drive Hardware
Devices using Parallel Buses
 Thereare three ways of transferring
data between the microprocessor and
a physical I/O device.
 Programmed I/O
 Interrupt driven I/O
 Direct Memory Access (DMA)
 The microprocessor executes a program to
communicate with an external device via a register
called I/O port for programmed I/O.
  An external device requests microprocessor to transfer
data by activating a signal on the microprocessor’s
interrupt line during interrupt I/O. In response, the
microprocessor executes a program called the interrupt-
service routine to carry out the function desired by the
external device.
  Data transfer between microcomputer’s memory and
an external device occurs without microprocessors
involvement in Direct Memory Access.
Prepared by M. Mahesh Babu Assistan
t-Professor.
I/O Device Speeds
 Processors can operate at speeds that are
vastly different than I/O speeds.
 When a human is entering characters on a
keyboard, the processor can execute millions of
instructions between successive character
entries.

So, how does the processor handle I/O

inputs…..
Three types of I/O Strategies
 Polled I/O

 Interrupt Driven I/O

 DMA I/O
Polled IO versus Interrupt Driven I/O
 Polled IO – processor continually checks IO
device to see if it is ready for data transfer
 Inefficient, processor wastes time checking for ready
condition
 Interrupt Driven IO – IO device interrupts
processor when it is ready for data transfer
 Processor can be doing other tasks while waiting for
last data transfer to complete – very efficient.
Rate of Transmission
 For parallel transmission, all of the bits are
sent at once.
 For serial transmission, the bits are sent
one at a time. Therefore, there needs to
be agreement on how “long” each bit stays
on the line.
 The rate of transmission is usually
measured in bits/second or baud.
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 Given a certain baud rate, how long
should each bit last?
 Baud = bits / second.
 Seconds / bits = 1 /baud.
 At 1200 baud, a bit lasts 1/1200 = 0.83 m
Sec.

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Comparison of transfer rates
 Polled waiting loops provide data rates that are
a bit slower, but still quite reasonable.
 Interrupt-driven I/O requires overhead of saving
and restoring the machine state (significantly
degrades data rates unless more than one byte
can be transferred per interrupt.
 DMA has fastest transfer rates (additional
hardware complexity needed.
disadvantage of programmed I/O
 The microcomputer needs to check the status bit
(BUSY signal for the A/D converter) by waiting in
a loop.
 This type of I/O transfer is dependent on the
speed of the external device.
 For a slow device, this waiting may slow down
the capability of the microprocessor to process
other data.

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Interrupt Driver I/O
 Interrupt I/O is a device-initiated I/O transfer. The
external device is connected to a pin called the
interrupt (INT) pin on the processor chip.
 When the device needs an I/O transfer with the
microcomputer, it activates the interrupt pin of
the processor chip.
 The microcomputer usually completes the
current instruction and saves at least the
contents of the current program counter on the
stack.
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 The microcomputer then automatically loads an address
into the program counter to branch to a subroutine like
program called the interrupt service routine.
 This program is written by the user. The external device
wants the microcomputer to execute this program to
transfer data.
 The last instruction of the service routine is a RETURN,
which is typically the same instruction used at the end of
a subroutine.
 This instruction normally loads the address (saved in the
stack before going to the service routine) in the program
counter. Then, the microcomputer continues executing
the main program.Prepared by M. Mahesh Babu Assistan
t-Professor.
Direct Memory Access (DMA)
 DMA is a technique that transfers data
between a microcomputer’s memory and
I/O device without involving the
microprocessor.
 DMA is widely used in transferring large
blocks of data between a peripheral device
and the microcomputer’s memory.
 The DMA technique uses a DMA controller
chip for the data transfer operation.
Prepared by M. Mahesh Babu Assistan
t-Professor.
 The main functions of a typical DMA controller are
summarized as follows:
 The I/O devices request DMA operation via the DMA
request line of the controller chip.
 The controller chip activates the microprocessor HOLD
pin, requesting the CPU to release the bus.
 The processor sends HLDA (hold acknowledge) back to
the DMA controller, indicating that the bus is disabled.
The DMA controller places the current value of its
internal registers, such as the address register and
counter, on the system bus and sends a DMA
acknowledge to the peripheral device. The DMA
controller completes the DMA transfer.
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 There are three basic types of DMA:
 block transfer,
 cycle stealing, and
 interleaved DMA.

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block transfer DMA
 For block transfer DMA, the DMA
controller chip takes the bus from the
microcomputer to transfer data between
the memory and I/O device. The
microprocessor has no access to the bus
until the transfer is completed. During this
time, the microprocessor can perform
internal operations that do not need the
bus. This method is popular with
microprocessors. Using this technique,
blocks of data can be transferred.
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cycle stealing DMA
 Data transfer between the microcomputer memory and an I/O
device occurs on a wordby- word basis with cycle stealing. Typically,
the microprocessor clock is enabled by ANDing an INHIBIT signal
with the system clock. The system clock has the same frequency as
the microprocessor clock. The DMA controller controls the INHIBIT
line. During normal operation, the INHIBIT line is HIGH, providing
the microprocessor clock.
 When DMA operation is desired, the controller makes the INHIBIT
line LOW for one clock cycle. The microprocessor is then stopped
completely for the cycle. Data transfer between the memory and I/O
takes place during this cycle. This method is called cycle stealing
because the DMA controller takes away or steals a cycle without
microprocessor recognition. Data transfer takes place over a period
of time.

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interleaved DMA
 With interleaved DMA, the DMA controller chip
takes over the system bus when the
microprocessor is not using it. For example, the
microprocessor does not use the bus while
incrementing the program counter or performing
an ALU operation. The DMA controller chip
identifies these cycles and allows transfer of
data between the memory and I/O device. Data
transfer takes place over a period for time for
this method.
Prepared by M. Mahesh Babu
Assistant-Professor.
 Peripheral Controllers
 Intel has developed several peripheral controller chips
designed to support its processors.
 The goal is to give a complete I/O interface in one chip.
 Examples:
 8255 is Programmable Peripheral Interface (PPI).
 8259 is Programmable Interrupt Controller (PIC)
 8253/8254 is Programmable Interval Timer (PIT)
 8237 is Programmable DMA controller.
 In PC/XT computers these chips are built into the system board
and can be seen by inspection.
 In modern Computers the functionality of these chips has been
built into the system board chipset.
 8255A
 Is one of the peripheral controller chips
designed to support its processors.
 8255 is Programmable Peripheral Interface
(PPI).
 It is a general purpose parallel I/O Interfacing
device.
 8255 PPI
 The parallel input-output port chip 8255 is also called
as programmable peripheral input-output port.
 The Intel’s 8255 is designed for use with Intel’s 8-bit,
16-bit and higher capability microprocessors.
 The 8255A is LSI peripheral designed to permit easy
implementation of parallel I/0 in the 8086 micro-
computer systems.
 It provides a flexible parallel interface, which
includes features such as single-bit, 4-bit, and byte-
wide input and output ports.

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 8255 PPI
 It has 24 input/output lines which may be individually
programmed in two groups of twelve lines each, or three
groups of eight lines.
 The two groups of I/O pins are named as Group A and
Group B. Each of these two groups contains a subgroup of
eight I/O lines called as 8-bit port and another subgroup of
four lines or a 4-bit port.
 Thus Group A contains an 8-bit port A along with a 4-bit
port C upper. The port A lines are identified by symbols
PA0-PA7 while the port C lines are identified as PC4-PC7.

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 8255 PPI
 Similarly, Group B contains an 8-bit port B, containing lines
PB0-PB7 and a 4-bit port C with lower bits PC0- PC3.
 The port C upper and port C lower can be used in combination
as an 8-bit port C.
 Both the port C are assigned the same address. Thus one may
have either three 8-bit I/O ports or two 8-bit and two 4-bit
ports from 8255.
 All of these ports can function independently either as input or
as output ports.
 This can be achieved by programming the bits of an internal
register of 8255 called as control word register (CWR).

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Block Diagram of 8255

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Pin Configuration of 8255
PA0
D0
PA1
D1 PA2
D2 PA3 PORT A
D3 PA4
D4 PA5
D5 PA6
D6 PA7
D7
PB0
PB1
8255 PB2
Mode 2 Control Signals
RD PB3
PB4
PORT B
WR PB5
PB6
PB7
A0
A1
PC0
RESET PC1
PC2
PC3
CS
PC4
PORT C
PC5
PC6
PC7

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 8255 PPI
 Control Logic of 8255:
 D0-D7 : These are the data bus lines those carry data or control word to/from
the microprocessor.
 RESET : A logic high on this line clears the control word register of 8255. All
ports are set as input ports by default after reset.
 PA7-PA0: These are eight port A lines that acts as either latched output or
buffered input lines depending upon the control word loaded into the control
word register.
 PC7-PC4 : Upper nibble of port C lines. They may act as either output latches
or input buffers lines. This port also can be used for generation of handshake
lines in mode 1 or mode 2.
 PC3-PC0 : These are the lower port C lines, other details are the same as PC7-
PC4 lines.
 PB0-PB7 : These are the eight port B lines which are used as latched output
lines or buffered input lines in the same way as port A.

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 8255 PPI
 Control Logic of 8255:
 RD : This is the input line driven by the microprocessor and should be low to
indicate read operation to 8255.
 WR : This is an input line driven by the microprocessor. A low on this line
indicates write operation.
 CS : This is a chip select line. If this line goes low, it enables the 8255 to
respond to RD and WR signals, otherwise RD and WR signal are neglected.
 A1-A0 : These are the address input lines and are driven by the microprocessor.
These lines A1-A0 with RD, WR and CS from the following operations for
8255. These address lines are used for addressing any one of the four registers,
i.e. three ports and a control word register as given in table below.
 In case of 8086 systems, if the 8255 is to be interfaced with lower order data
bus, the A0 and A1 pins of 8255 are connected with A1 and A2 respectively.

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 8255 PPI
 Control Logic.
 CS signal is a Master Chip Select, whereas A0 and A1 determine
the input/output ports or control registers as tabulated in Table 1.
Table 1: The function of CS, A0 and A1
CS A1 A0 Selection
0 0 0 port A

0 0 1 port B

0 1 0 port C

0 1 1 Control
Register
1 X X 8255 is
disabled

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 8255 PPI
 There are 3 ports in 8255 from user’s point of view - Port
A, Port B and Port C.
 Port C is composed of two independent 4-bit ports :
PC7-4 (PC Upper) and PC3-0 (PC Lower)
 Selection of Ports:

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t-Professor.
 Intel 8255 PPI
 Chip Select Circuit

A7=0, A6=1, A5=1, A4=1, A3=1, A2=1, & M/IO*= 0

47
 Intel 8255 PPI
 There is also a Control port from the Processor point
of view. Its contents decides the working of 8255.
 When CS (Chip select) is 0, 8255 is selected for
communication by the processor. The chip select
circuit connected to the CS pin assigns addresses to
the ports of 8255.
 For the chip select circuit shown, the chip is selected
when A7=0, A6=1, A5=1, A4=1, A3=1, A2=1, and
M/IO*= 0.
 Port A, Port B, Port C and Control port will have the
addresses as 7CH, 7DH, 7EH, and 7FH respectively.
48
 8255 PPI

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 8255 PPI
 Three main concept is communicate to
8255:
 Determine the port address of A, B and C using
CS, A1 and A0.
 Write control word in control register.
 Write I/O instructions to communicate with ports.

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8255 Control Word
 8255 PPI-Operation modes
 Figure shows the function of 8255, categorized in two mode:
 Set/Reset Bit (BSR) mode
 I/O mode.
 The BSR mode is used to set or reset bit at port C by sending
OUT instruction to the CONTROL registers.
 Whereas the I/O is divided into 3 groups:
 Mode 0, Mode 1 and Mode 2.
 Mode 0, all ports function as input or output (I/O function).
 Mode 1, is handshake mode, where port A and/or port B used
port C as handshake bit.
 Mode 2, port A can be used as bi-directional data transfer port
with port C as handshake port and port B will be in mode 1 or
mode 2.

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 8255 PPI-Operation modes
 Bit Set/Reset (BSR) mode:

 The BSR mode is used to set or reset bit at port C by sending

OUT instruction to the CONTROL registers.
 In this mode any of the 8-bits of port C can be set or reset
depending on D0 of the control word. The bit to be set or reset
is selected by bit select flags D3, D2 and D1 of the CWR.
 BSR command word is used for enabling / disabling interrupts
from Ports A and B when they are configured in mode 1 or
mode 2.

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 8255 PPI-Operation modes
 I/O mode:
 The I/O mode is further divided into 3 modes: mode 0, mode 1
and mode 2.
 In mode 0, all ports function as simple I/O ports.
 Mode 1 is a handshake mode whereby Port A and/or Port B
use bits from Port C as handshake signals. In the handshake
mode, two types of I/O data transfer can be implemented:
status check and interrupt.
 In mode 2, Port A can be set up for bidirectional data transfer
using handshake signals from Port C, and Port B can be set up
either in mode 0 or mode 1.

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 Programming 8255
 8255 has three operation modes: mode 0, mode 1, and mode 2

11-57
Basic Mode Definitions and Bus
Int

 Mode 0
 Basic I/O
 Mode 1
 Strobe I/O
 Mode 2
 Bi-Dir Bus
 8255 PPI Mode selection:
 There are 3 basic modes of operation that can
be selected by the system software for the
8255:
 Mode 0 - Basic Input/Output
 Mode 1 – Input/output with Handshake (Strobed
I/O)
 Mode 2 - Bidirectional Data Transfer

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8255 PPI - Mode Definition Format

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 8255 PPI

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8255 PPI - Bit Set/Reset Format

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 8255 PPI - Mode 0
 Mode 0 (Basic Input/Output):
 This functional configuration provides simple input and output operations
for each of the three ports. No ``handshaking‘’ is required, data is simply
written to or read from a specified port.
 It is used for interfacing an i/p device or an o/p device.
 In this mode, Port A and Port B are used as two simple 8-bit I/O ports and
Port C as two 4-bit I/O ports can be combinedly used as a third 8-bit port.
Each port (or half-port, in case of Port C) can be programmed to function
as simply an input port or an output port.
 Output ports are latched. Input ports are not latched.
 All these modes can be selected by programming a register internal to
8255 known as CWR.
 Ports do not have handshake or interrupt capability.
 16 different Input/Output configurations are possible in this Mode.
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Assistant-Professor.
 8255 PPI

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 8255 PPI
 MODE 1 (Strobed Input/Output):
 This functional configuration provides a means for transferring
I/O data to or from a specified port in conjunction with strobes or
``handshaking'' signals. In mode 1, Port A and Port B use the lines
on Port C to generate or accept these ``handshaking'' signals.
 Two groups –
 Group A
 This group including port A and PC3-PC5. Thus port C is utilized for
generating handshake signals.
 Group B
 This group which includes port B and PC0-PC2. Port C provides strobe or
handshake lines for port B.
 The 8-bit data port can be either used as input and output port.
The inputs and outputs both are latched and Interrupt logic is
supported. Prepared by M. Mahesh Babu Assistan
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 Mode 1 -Input Control Signal Definition
 STB (Strobe Input): A ``low'' on this input loads data into the input latch.
 IBF (Input Buffer Full F/F):
 A ``high'' on this output indicates that the data has been loaded into the input
latch; in essence, an acknowledgement. IBF is set by STB input being low and
is reset by the rising edge of the RD input.
 INTR (Interrupt Request):
 A ``high'' on this output can be used to interrupt the CPU when an input device
is requesting service. INTR is set by the STB is a ``one'', IBF is a ``one‘’ and
INTE is a ``one''. It is reset by the falling edge of RD. This procedure allows an
input device to request service from the CPU by simply strobing its data into
the port.
 INTE A
 Controlled by bit set/reset of PC4.
 INTE B
 Controlled by bit set/reset of PC2.
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Mode 1 - Input

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 8255 PPI

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 8255 PPI Output Control Signal Definition
 OBF (Output Buffer Full F/F).
 The OBF output will go ``low'' to indicate that the CPU has written data out to the
specified port. The OBF F/F will be set by the rising edge of the WR input and reset
by ACK Input being low.
 ACK (Acknowledge Input).
 A ``low'' on this input informs the 82C55A that the data from Port A or Port B has
been accepted. In essence, a response from the peripheral device indicating that it
has received the data output by the CPU.
 INTR (Interrupt Request).
 A ``high'' on this output can be used to interrupt the CPU when an output device has
accepted data transmitted by the CPU. INTR is set when ACK is a ``one'', OBF is a
``one‘’ and INTE is a ``one''. It is reset by the falling edge of WR.
 INTE A
 Controlled by bit set/reset of PC6.
 INTE B
 Controlled by bit set/reset of PC2.
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Assistant-Professor.
Mode 1 Output

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 8255 PPI

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 MODE 2 (Strobed Bidirectional Bus I/O):
 This functional configuration provides a means for
communicating with a peripheral device or structure on a single 8-
bit bus for both transmitting and receiving data (bidirectional bus
I/O). ``Handshaking'' signals are provided to maintain proper bus
flow discipline in a similar manner to MODE 1. Interrupt
generation and enable/disable functions are also available.
 The single 8-bit port in group A is available.
 The 8-bit port is bidirectional and additionally a 5-bit control port
is available.
 Three I/O lines are available at port C.(PC2 – PC0)
 Inputs and outputs are both latched.
 The 5-bit control port C (PC3-PC7) is used for generating /
accepting handshake signals for the 8-bit data transfer on port A.
Prepared by M. Mahesh Babu Assistan
t-Professor.
 8255 PPI

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t-Professor.
Mode 2 - Input Operations
 STB (Strobe Input). A ``low'' on this input loads data into the
input latch.
 IBF (Input Buffer Full F/F). A ``high'' on this output indicates
that data has been loaded into the input latch.
 INTE 2 (The INTE Flip-Flop Associated with IBF). Controlled
by bit set/reset of PC4.

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t-Professor.
 Mode 2 - Output Operations
 OBF (Output Buffer Full). The OBF output will go ``low'' to
indicate that the CPU has written data out to port A.
 ACK (Acknowledge). A ``low'' on this input enables the tri-
state output buffer of Port A to send out the data. Otherwise,
the output buffer will be in the high impedance state.
 INTE 1 (The INTE Flip-Flop Associated with OBF).
Controlled by bit set/reset of PC6.

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t-Professor.
 8255 PPI

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t-Professor.
 8255 PPI

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t-Professor.
 8255 PPI

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t-Professor.
 8255 PPI

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t-Professor.
8255 PPI mode 1-input control

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t-Professor.
8255 PPI mode 1-out control

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t-Professor.
8255 PPI- Mode 2 Control Signals

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t-Professor.
FIGURE 8-11 8255 programmable peripheral interface (PPI). Twenty-four I/O pins are provided grouped as three 8-bit I/O
ports. There is one 8-bit control port. (Courtesy of Intel Corporation.)
 Programming modes
 Mode 0: the 8255A is programmed to look like three
simple I/O ports.
 Mode 1: the 8255A is programmed to have two
handshaking I/O ports.
 Mode 1: the 8255A is programmed to have one
bidirectional port with five handshaking signals.
 The modes can be intermixed, for example, port A is
programmed to operate in mode 2, while port B
operates in mode 0.
 bit set/reset mode allows individual bits of port C to
be set or reset for control purposes.
Continued ...

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t-Professor.
Continued ...

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t-Professor.
 The 8255 is a widely used, programmable parallel I/O
device. It can be programmed to transfer data under data
under various conditions, from simple I/O to interrupt I/O.
 It is flexible, versatile and economical (when multiple I/O
ports are required). It is an important general purpose I/O
device that can be used with almost any microprocessor.
 The 8255 has 24 I/O pins that can be grouped primarily into
two 8 bit parallel ports: A and B, with the remaining 8 bits as
Port C.
 The 8 bits of port C can be used as individual bits or be
grouped into two 4 bit ports : CUpper (CU) and CLower
(CL). The functions of these ports are defined by writing a
control word in thePrepared
control register.
by M. Mahesh Babu Assistan
t-Professor.
 8255 PPI

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t-Professor.