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8thjan Task

The document discusses various scenarios involving FIFO (First In, First Out) operations, including writing to and reading from FIFO under different conditions. It also covers the fork-join concept in Verilog for parallel execution, and introduces new data types in SystemVerilog such as logic, bit, and integer types, along with their usage. Additionally, it highlights advanced features like enums, structs, unions, arrays, classes, interfaces, events, strings, and user-defined types.

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Ruturaj Nakum
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2 views15 pages

8thjan Task

The document discusses various scenarios involving FIFO (First In, First Out) operations, including writing to and reading from FIFO under different conditions. It also covers the fork-join concept in Verilog for parallel execution, and introduces new data types in SystemVerilog such as logic, bit, and integer types, along with their usage. Additionally, it highlights advanced features like enums, structs, unions, arrays, classes, interfaces, events, strings, and user-defined types.

Uploaded by

Ruturaj Nakum
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
Available Formats
Download as PPTX, PDF, TXT or read online on Scribd
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TASK

Himani vandara
Guided by Aditi Paradkar
Q.1) Confirm for more complicated conditions if above
conclusion fits for it.
1: FIFO Written to All Locations (No Read)
• Wr_count = 0, Rd_count = 0
• fifo_wr = 1 (FIFO full after writing all locations)
• fifo_rd = 0 (No read performed)
• FIFO is full.
2: FIFO Written to All Locations, Then Read Out
• Wr_count = 0, Rd_count = 0
• fifo_wr = 1 (FIFO full after writing)
• fifo_rd = 1 (FIFO empty after reading all locations)
• FIFO is empty.
Continue....

Complex Conditions:

• FIFO behaves similarly with alternating write/read operations.


• fifo_wr = 1 when full (Wr_count = 15).
• fifo_rd = 1 when empty (Rd_count = 15).
Q.2)Write synchronous FIFO code and testbench.

• Code write in EDA playground


Q.3) Fork join concept in verilog and apply it to write and
read parallely from fifo.

• fork and join constructs allow for parallel execution of code.


• fork: Begins multiple parallel processes.
• join: Waits for all parallel processes within the fork block to complete.

The code is in the EDA Playground.


Q.4)Try to write and read from fifo more than 70 times.

• Code is in the EDA playground.


Q.5) Go through sv added data types.

SystemVerilog is an extension of Verilog that introduces new data types


to enhance the design and verification process.
Data types:
Logic:
- used to represent signals in SystemVerilog.
- replaces both the reg and wire types from Verilog.
- represent both combinational and sequential signals.
- Ex: logic a;
Continue....

Bit:
- represents 2-state logic values (0 and 1).
- used for synthesizable designs where only binary values are needed.
- Ex; bit a;
bit [3:0] b;
Continue....

Integer Types (int, shortint, longint):


- int: 32-bit signed integer.
- shortint:16-bit signed integer.
- longint: 64-bit signed integer.
- Used for numeric values.
- Ex; int a;
shortint b;
longint c;
Continue...
Real:
- used for floating-point numbers.
- 64-bit representation.
- useful for high precision in calculations.
- Ex; real a;
time:
-used to represent time values and for simulation timing.
-64-bit value.
-Ex; time t;
Continue....
Enum:
- defines a set of named constants.
- Ex;typedef enum {january,february,march,april,....}
Struct:
- used to group multiple variables of different types into a single
entity.
- Ex;typedef struct {
logic [7:0] data;
logic valid; } ;
Continue....

Union:
- Allows multiple variables to share the same memory.
- Ex:union { type1 var1; type2 var2; }
Array:
- A collection of elements, can be fixed, dynamic,or associative.
- Ex;type array_name[size];
type array_name[];
type array_name[index];
Continue....

Class:
- Groups data ,properties and methods.
- Ex: class class_name;
type property;
function type method();
endfunction
endclass
Continue....

Interface:
- Groups related signals for easy module connections.
- Ex: interface interface_name(input signal1, signal2);
type signal;
endndinterface
Event:
- Used for synchronization between processes.
- Ex; event my_event;
Continue....

String:
- Used to handle text.
- Ex; string msg = "Hello, SystemVerilog!";
Type:
- Allows the creation of user-defined data types using typedef.
Void:
- Represents a function or task that does not return a value.
- Ex;function void my_function();
- endfunction

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