lecture_11_K_maps4
lecture_11_K_maps4
CLOs 2
AB
CD 00 01 11 10
00
0 4 12 8
01
1 5 13 9
11
3 7 15 11
10
2 6 14 10
AB
CD 00 01 11 10
00
0 4 12 8
01
1 5 13 9
11
3 7 15 11
10
2 6 14 10
AB
CD 00 01 11 10
00
0 4 12 8
01
1 5 13 9
11
3 7 15 11
10
2 6 14 10
AB
CD 00 01 11 10
00
0 4 12 8
01
1 5 13 9
11
3 7 15 11
10
2 6 14 10
AB
CD 00 01 11 10
00
0 4 12 8
01
1 5 13 9
11
3 7 15 11
10
2 6 14 10
AB
CD 00 01 11 10
00
0 4 12 8
01
1 5 13 9
11
3 7 15 11
10
2 6 14 10
f ACD AB
AB D
AB
CD 00 01 11 10 AB
CD 00
00 01
01 11
11 10
10
00
0 4 12 8 00
00 1 1 1 1
01
1 5 13 9 01
01 1
11
3 7 15 11 11
11 1 1 1
10
2 6 14 10 10
10 1 1 1 1
f m(1,3, 4,5,10,12,13)
AB
CD 00 01 11 10
00 1 1
0 4 12 8
01 1 1 1
1 5 13 9
11 1
3 7 15 11
10 1
2 6 14 10
f C BD ABD
f AD CD
01 0 0 0 0 01 1 1 1 1
11 1 0 1 1 11 0 1 0 0
10 1 0 0 1 10 0 1 1 0
f f
BC BC
DE 00 01 11 10 DE 00 01 11 10
00 1 00 1
01 1 1 1 01 1
A 0 A 1
11 1 11
10 10
f BCDE
Monday, February 02 DLD 200 Digital Logic Design Slide 16 of 11
Karnaugh Maps
An Example From CEC 222 Lab 4