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GMR Institute of Technology

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Mini Project Review

Department of ECE

Feb 8, 2025
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Feb 8, 2025
 Mini Project
Title of the Mini Project
FPGA implementation of 4-bit Vedic Multiplier using adders
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S.No Name JNTU no

1. A. Divya 22341A0402
2. A. Rohith Kumar 22341A0409
3. B. Aparna 22341A0418
4. B. Murali Krishna 22341A0419
5. B. Sailesh Gupta 22341A0424

Under the guidance of

Dr. Yogesh Mishra
Professor
Department of ECE
GMR Institute of Technology
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 Objective

The objective of this project is to implement a 4-bit Vedic Multiplier using adders in
FPGA.
• To design, simulate, analyze and implementation of a 4-bit Vedic multiplier using
Ripple Carry Adder (RCA) and Carry Look Ahead (CLA) adders .
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• Based on the parameters like Speed, Complexity, Area, Power Consumption,

Propagation Delay, Fan-out, Scalability and Latency to analyze which adder is
suitable for designing an efficient Vedic multiplier.

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 Abstract

• This research paper is about the performance of the Vedic multiplier when
integrated with two different adder architectures: Carry Look-Ahead Adder (CLA)
and Ripple Carry Adder (RCA). Vedic multiplication, known for its efficient
multiplication process, is evaluated in terms of speed, latency, area, and power
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consumption, depending on the choice of adder. While RCA is simpler and easier to
implement, it suffers from slower carry propagation, leading to higher latency for
larger bit-width operations. On the other hand, CLA improves speed by reducing
carry propagation delays at the cost of increased circuit complexity and area. The
analysis explores the trade-offs between these adders, considering their impact on
the performance and scalability of the Vedic multiplier, particularly in real-world
applications like Digital Signal Processing, cryptography, and hardware
acceleration.

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 Introduction
Multiplier:

A logic circuit which is combinational in nature and employed in a digital

circuits to perform the multiplication operation can be called a multiplier. The
multiplier has a significant scope in the area of digital signal processing. The
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multiplication operation in contrast with the addition and subtraction is more

complicated. The adder circuits are comprised inside a multiplier architecture which
will in turn perform the multiplication operation.

Vedic multipliers:
The Vedic multiplier is a multiplication algorithm commonly used in digital
circuits that is known for its speed and efficiency. This algorithm is based on the
principles of Vedic mathematics, an ancient Indian mathematical system that has been
adapted for modern computing applications. The Vedic multiplier works by breaking
down the numbers Vedic multipliers are digital circuits that use ancient Indian Vedic
mathematics to perform multiplication operations.
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 Introduction

2-bit Vedic Multiplier 4-bit Vedic Multiplier

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Paper [2]

Paper [2]

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 Introduction

4-bit adders:

A 4-bit adder is a digital circuit that performs arithmetic operations by adding two 4-bit
binary numbers, producing a 5-bit sum. This circuit is essential in digital computers,
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digital signal processing, and embedded systems. The 4-bit adder consists of four full
adders connected in a chain, with each full adder handling three binary digits and
producing sum and carry outputs.
There are main types of 4-bit adders:

1. Ripple Carry Adder.

2. Carry Lookahead Adder .

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 Introduction
Ripple Carry Adder:

A Ripple Carry Adder (RCA) is a digital adder that uses a simple, serial
approach to perform addition. It consists of a chain of full adders, where each full
adder handles one bit of the input numbers and produces a sum and carry output. The
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carry output from each full adder is then passed to the next full adder in the chain,
creating a "ripple" effect.

Carry Lookahead Adder:

A Carry Lookahead Adder (CLA) is a digital adder that employs a parallel

approach to perform addition, thereby reducing the delay associated with the ripple
carry mechanism. By using a separate circuit to generate carry signals in parallel, CLA
enables faster addition and is particularly suitable for high-speed applications.

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 Literature Survey

Paper Title :Comparative analysis of Vedic multiplier using Vedic sutras with

existing multipliers in biomedical application.

Journal Title : Elsevier

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Year of Publication : 2024

Keywords : Vedic multipliers ,Urdhva Tiryakbhyam, Ekanyunena Purvena,

Ekadhikena Purvena, Nikhilam, Array multipliers, Booth

multipliers, Wallace multiplier Carry-save adders. .

Summary :Arithmetic Logic Units (ALU) and Multiply-Accumulate

(MAC)
are the fundamental parts of these circuits and are necessary for

their effective and rapid operation. The most significant

prevalent part of digital signal processing devices is multi pliers.

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 Literature Survey

Paper Title :Design and implementation of Vedic Multiplier using carry

increment adder

Journal Title : IEEE

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Year of Publication : 2023

Keywords : Verilog HDL, Vedic multiplier carry increment adder, look

up table, ripple carry adder.

Summary : Vedic multiplier uses adders as its fundamental building

block. One of the crucial performance criteria for many

digital circuits is the circuit’s operating speed, which

ultimately depends on the basic adder unit’s delay.

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 Literature Survey

Paper Title : Design and analysis of 8-bit Vedic Multiplier.

Journal Title : IEEE

Year of Publication : 2023

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Keywords :Vedic multiplier, Array multiplier, Wallace tree multiplier,

Xilinx ISE, Verilog.

Summary :Multipliers are utilized in a wide range of DSP appli

cations

nowadays, including vector product, filtering, convolution

operations, matrix multiplication, etc. The parameters

which are important to consider with precision are speed

of

operation, chip space occupied, ease of design, high noise

immunity, and so on. 11

 Gap Analysis

Paper Abstract
[1] R.Karthi Kumar, S.P. Vimal Vedic multipliers, based on ancient
“Comparative analysis of Vedic Indian mathematics, offer a
multiplier using Vedic sutras with promising solution for high-speed,
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existing multipliers in low-power multiplication in digital

biomedical application” 2024. signal processing and
other applications.
[2] A. Lavanya, S. Nagaraj, A 16-bit Vedic multiplier using Carry
M. Lekhya “Design and Increment Adder (CIA) with Carry
implementation of Vedic Lookahead Adder (CLA) achieves
Multiplier using carry 1% lesser area but 10% greater delay
increment adder” 2023. compared to Ripple Carry Adder
(RCA) implementation.

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 Gap Analysis

Paper Abstract
[3] Saylee Gharge, Shrutika Patel, This paper presents a comparative
Aditi Patil, Nidhi Mundhada, analysis of an 8-bit Vedic multiplier
Vaishnavi Shetty with Wallace tree, array multipliers in
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“Design and analysis of 8-bit Vedic terms of latency, area, and

Multiplier” 2023. power consumption.

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 Applications

1. Digital Signal Processing: Vedic multipliers can be used to accelerate image, video
and audio processing.

2. Artificial Intelligence and Machine Learning : Vedic multipliers can be used to

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accelerate neural network , deep learning.

3. Cryptography : Vedic multipliers can be used to accelerate encryption, decryption

and secure data transmission protocols.

4. Biomedical Applications: Vedic multipliers can be used to accelerate medical

imaging, genomics, proteomics algorithms.

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 Advantages

1. Faster Multiplication.

2. High-Speed Calculations.

3. Low Power Consumption.

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4. Energy Efficiency.

5. High Accuracy.

6. Reliability

7. Small Area.

8. Flexible Design.
9. Low Cost.

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 References

[1] R.Karthi Kumar, S.P. Vimal “Comparative analysis of Vedic multiplier using Vedic
sutras with existing multipliers in biomedical application” 2024.
[2] A. Lavanya, S. Nagaraj, M. Lekhya “Design and implementation of Vedic
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Multiplier using carry increment adder” 2023.

[3] Saylee Gharge, Shrutika Patel, Aditi Patil, Nidhi Mundhada, Vaishnavi Shetty
“Design and analysis of 8-bit Vedic Multiplier” 2023.

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 GMR Institute of Technology

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