PRESIDENCY UNIVERISTY,

BENGALURU
School of Engineering

Microprocessors and Microcontroller

CSE 206

IV Semester 2018-19
 Module – 4

Programmable Peripheral
Interfacing
Intel 8255A – Programmable Peripheral
Interface
• The parallel input-output port chip 8255 is also called as
programmable peripheral input- output port.
• The Intel’s 8255 is designed for use with Intel’s 8-bit, 16-bit
and higher capability microprocessors.
• It has 24 input/output lines which may be individually
programmed in two groups of twelve lines each, or three
groups of eight lines.
• The two groups of I/O pins are named as Group A and
Group B. Each of these two groups contains a subgroup of
eight I/O lines called as 8-bit port and another subgroup of
four lines or a 4-bit port.
• Thus Group A contains an 8-bit port A along with a 4-bit
port. C upper.
Intel 8255A – Programmable Peripheral
Interface
• The port A lines are identified by symbols PA0-PA7 while
the port C lines are identified as PC4-PC7. Similarly, Group
B contains an 8-bit port B, containing lines PB0-PB7 and a
4-bit port C with lower bits PC0- PC3.
• The port C upper and port C lower can be used in
combination as an 8-bit port C. Both the port C are
assigned the same address.
• Thus one may have either three 8-bit I/O ports or two 8-bit
and two 4-bit ports from 8255. All of these ports can
function independently either as input or as output ports.
• This can be achieved by programming the bits of an
internal register of 8255 called as control word register
(CWR). This buffer receives or transmits data upon the
execution of input or output instructions by the
microprocessor.
• The control words or status information is also transferred
through the buffer.
Intel 8255A – Architecture
Intel 8255A – Pin Description

•PA0 – PA7 – Pins of port A

•PB0 – PB7 – Pins of port B
•PC0 – PC7 – Pins of port C
•D0 – D7 – Data pins for the
transfer of data
•RESET – Reset input
•RD’ – Read input
•WR’ – Write input
•CS’ – Chip select
•A1 and A0 – Address pins
Intel 8255A – Pin Description
It is a 40 pin IC which operates on +5V power supply. These 40
pins are described in the following sections.
1. D0-D7 (Data bus): These are 8-bit bidirectional data bus,
connected to system data bus for data transfer between 8086
and 8255. On these data lines 8086 will send control word data
to initialize 8255, send data or read data.
2. RD- (Read): This is for read operation. It is active low signal
which is input to the 8255. A low on this input pin enables the
8255 to send the data or status information to the CPU on the
data bus. In essence, it allows the processor to read from the
8255.
3. WR- (Write): This is for write operation. It is active low signal
which is input to the 8255. A low on the input pin enables the
CPU to write data or control words into the 8255.
Intel 8255A – Pin Description
4. RESET: This signal is used to reset the 8255. A high on this input
signal clears the control register and all ports (A, B, C) are set to
the input mode. This signal is connected to the reset out of 8085
and reset signal of the clock generator of 8086.
5. Ports A, B, and C: The 8255A contains three 8-bit ports (A, B,
and C). All can be configured in a wide variety of functional
characteristics by the system software but each has its own
special features that further enhances the power and flexibility of
the 8255A.
Port A: One 8-bit data output latch/buffer and one 8-bit data
input latch.
Port B: One 8-bit data output latch/buffer and one 8-bit data
input buffer.
Port C: One 8-bit data output latch/buffer and one 8-bit data
input buffer (no latch for input).
Intel 8255A – Pin Description
Port C can be divided into two 4-bit ports under the mode
control. Each 4-bit port contains a 4-bit latch and it can be
used for the control signal outputs and status signal inputs in
conjunction with ports A and B.
6. A0 and A1 (Address lines): These two A1 A0 Port
input signals were connected with the A1 0 0 PA
and A0 address lines of the demultiplexed 0 1 PB
address lines. These two signals will give 1 0 PC
the addresses of the port addresses and the 1 1 CWR
CWR as follows:
7. cs- (Chip select): A low on this signal select the chip. The
chip select signal generated by the A2-A, address lines (in case
of IO mapped IO) or A2-A15 address lines (in case of Memory
mapped IO) is connected to this signal. The combination of
these address lines along with the A1-A0 generates the actual
8-bit or the 16-bit port addresses.
Operational Modes of 8255
There are two main operational modes of 8255:
• Bit set/reset mode
• Input/output mode
There are three types of the input/output mode.
• Mode 0
• Mode 1
• Mode 2
Bit Set/Reset (BSR) mode
• Any of the eight bits of port C can be set or reset using a
single output instruction. This feature reduces software
requirements in control-based applications.
• Each line of port C (PC0 - PC7) can be set/reset by
suitably loading the command word register. No effect
occurs in input output mode.
• The individual bits of port c can be set or reset by
sending the signal OUT instruction to the control register.
Control Word Register – BSR Mode
Bit Set/Reset (BSR) mode
EXAMPLE: Write programs to perform the following operations:
(i) Reset bit 7 of port C (ii) Set bit 5 of port C
Assume the address of the port A= 80H, port B = 82H, port C =
84H and CWR = 86H.
Solution 0 X X X 1 1 1 0
i. To reset bit 7 of port C, the bit pattern of the CWR will be
Assuming XXX as 111, we will have CWR = 01111110 = 7EH
MOV AL, 7EH
OUT 86 H, AL
ii. For setting the bit 5 of port C, the CWR bit pattern will be O
1111011 = 7BH the instructions for this operation are:
MOV AL, 7BH
OUT 86H, AL.
Control Word Register – I/O mode
Control Word Register – I/O Mode

1. Bit D7: This bit is used to select the IO or BSR mode.

When D7 is 0, then 8255 will work in BSR mode and
when, D7 is 1 then 8255 will work in IO mode. Hence in
:

all the IO modes, D7 is always being kept as high.

2. Bits D6 and D5: These bits are used to specify the

mode of group A. The port A can work in three different
modes, i.e. mode 0, mode 1 and mode 2, hence two bits
are required for the mode selection as shown in Figure
above.

3. Bit D4: This bit is used to specify whether port A acts as

an input port or as an output port. When this bit is 0, then
port A will act as output port otherwise input port.
Control Word Register – I/O Mode
4. Bit D3: This bit is used to specify whether port PC
(Upper) acts as an input port or as an output port. When
this bit is 1, then port PC (Upper) will act as input port
:
otherwise output port.
5. Bit D2: This bit is used to define the mode of group B.
As port B and port PC(Lower) can act only in two modes
so only one bit is sufficient to define the mode of group
B. When D2 = 0, group B ports will act in mode 0 and if
D2 =l, this group will function in mode 1.
6. Bits D1 and D0: These bits are used to specify whether
the group B ports will be in input mode or in output
mode. Again, as in case of group A port 0 is used for
output mode and port 1 for input mode.
Input / Output Mode
Mode 0 (Simple I/O Mode)
In this mode, the ports can be used for simple input/output
operations without handshaking.
If both port A and B are initialized in mode 0, the two halves of port
C can be either used together as an additional 8-bit port, or they
can be used as individual 4-bit ports.
Since the two halves of port C are independent, they may be used
such that one-half is initialized as an input port while the other half
is initialized as an output port.
The input output features in mode 0 are as follows:
• O/P are latched.
• I/P are buffered not latched.
• Port do not have handshake or interrupt capability.
Mode 0 (Simple I/O Mode)
Mode 1 (Strobe Mode / Handshake Mode)

When we wish to use port A or port B for handshake

(strobed) input or output operation, we initialize that port in
mode 1 (port A and port B can be initialized to operate in
different modes, ie, for eg., port A can operate in mode 0
and port B in mode 1). Some of the pins of port C function
as handshake lines.
For port B in this mode (irrespective of whether is acting as
an input port or output port), PC0, PC1 and PC2 pins
function as handshake lines. If port A is initialized as mode 1
input port, then, PC3, PC4 and PC5 function as handshake
signals.
Pins PC6 and PC7 are available for use as input/output lines.
Mode 1 (Strobe Mode / Handshake Mode)

The mode 1 which supports handshaking has following

features:
• Two ports i.e. port A and B can be used as 8-bit I/O port.
• Each port uses three lines of port c as handshake signal
and remaining two signals can be function as I/O port.
• Interrupt logic is supported.
• Input and Output data are latched.
Mode 1 (Strobe Mode / Handshake Mode)

8255 Handshake Input port (Mode 1)

Mode 1 (Strobe Mode / Handshake Mode)

8255 Handshake Output port (Mode 1)

Mode 2 (Bi-Directional mode)

• Only group A can be initialized in this mode.

• Port A can be used for bidirectional handshake data
transfer. This means that data can be input or output on
the same eight lines (PA0 - PA7).
• Pins PC3 - PC7 are used as handshake lines for port A.
• The remaining pins of port C (PC0 - PC2) can be used as
input/output lines if group B is initialized in mode 0.
• In this mode, the 8255 may be used to extend the system
bus to a slave microprocessor or to transfer data bytes to
and from a floppy disk controller.
Mode 2 (Bi-Directional mode)
Functions of Port C
The various functions (assignments) of port C during the different
operating modes of port A and B
Example
Interface an input port and an output port with 8086 through
8255 and write a program to read data from input port and
transfer it to the output port.
Solution Let us assume that the input port is interfaced with port
C and port B is interfaced with the display. The program is to
repeat indefinitely.
Required control word is shown in Figure 12.24 and the CWR
byte is 89H.
Example
The addresses of the ports A, B, C, and the CWR is
Even port Odd port
Port A ASH A9H
Port B AAH ABH
Port ACH ADH
C CWR AEH AFH
Program:
MOV AL, CWRBYTE ; Transfer control byte to AL
OUT AEH, AL ; Send the control byte to the CWR of even port
OUT AFH, AL ; Send the control byte to the CWR of odd port
LOOP: IN AX, ACH ; Read data from input port
OUT AAH, AL ; Send AL data to output port
JMP LOOP ; Jump to loop
Example
Find the control word of the 8255 for the following configurations:
1.All the ports of A, B, and C are output ports (mode 0).
2.PA = in, PB = out, PCL = out, and PCH = out.
Solution:
(a) 1000 0000 = 80H
(b) 1001 0000 = 90H

Configure 8255A in mode-0 with different ports in input output

mode as below:
PORT A: Input; PORT B: Output
PCU: Output; PCL: Input
Solution: The control word to programme 8255A as above will be
1 0 0 1 0 0 012 = 91H
The control word will be outputted to control word register having
add 03H.The relevant instruction will be follows:
MVI A, 91H
OUT 03H
Microcontroller
8051
 Microcontroller vs General Purpose
Microprocessor
General-purpose Microcontroller has
microprocessors • CPU (microprocessor)
contains • RAM
• No RAM • ROM
• No ROM • I/O ports
• No I/O ports • Timer
• ADC and other peripherals
 Microcontroller vs General Purpose
Microprocessor
General-purpose Microcontroller has
microprocessors Contains • The fixed amount of on-
• Must add RAM, ROM, I/O ports, chip ROM, RAM, and
and timers externally to make number of I/O ports makes
them functional them ideal for many
applications in which cost
• Make the system bulkier and and space are critical
much more expensive
• In many applications, the
• Have the advantage of space it takes, the power it
versatility on the amount of consumes, and the price
RAM, ROM, and I/O ports per unit are much more
critical considerations than
the computing power
 Microcontroller vs General Purpose
Microprocessor
Microprocessors Microcontroller
• A PC, in contrast with the • An embedded product
embedded system, can be uses a microcontroller to
used for any number of do one task and one task
applications only
• There is only one
• It has RAM memory and an
operating system that loads a application software that is
variety of applications into typically burned into ROM
RAM and lets the CPU run them
• A PC contains or is connected
to various embedded products
• Each one peripheral has a
microcontroller inside it that
performs only one task
 Microcontroller for Embedded Systems
Home
Appliances, intercom, telephones, security systems, garage door
openers, answering machines, fax machines, home computers,
TVs, cable TV tuner, VCR, camcorder, remote controls, video
games, cellular phones, musical instruments, sewing machines,
lighting control, paging, camera, pinball machines, toys, exercise
equipment
Office
Telephones, computers, security systems, fax machines,
microwave, copier, laser printer, colour printer, paging
Auto
Trip computer, engine control, air bag, ABS, instrumentation,
security system, transmission control, entertainment, climate
control, cellular phone, keyless entry
 X86 PC Embedded Applications
• Many manufactures of general-purpose microprocessors have
targeted their microprocessor for the high end of the embedded
market
• There are times that a microcontroller is inadequate for the task
• When a company targets a general purpose microprocessor for
the embedded market, it optimizes the processor used for
embedded systems
• Very often the terms embedded processor and microcontroller
are used interchangeably
• One of the most critical needs of an embedded system is to
decrease power consumption and space
 X86 PC Embedded Applications
• In high-performance embedded processors, the trend is to
integrate more functions on the CPU chip and let designer
decide which features he/she wants to use
• In many cases using x86 PCs for the high-end embedded
applications
• Saves money and shortens development time
• A vast library of software already written
• Windows is a widely used and well understood platform
 Choosing a Microcontroller
8-bit microcontrollers
• Motorola’s 6811
• Intel’s 8051
• Zilog’s Z8
• Microchip’s PIC
There are also 16-bit and 32-bit microcontrollers made by
various chip makers
 Criteria for Choosing a Microcontroller
Meeting the computing needs of the task at hand efficiently
and cost effectively
• Speed
• Packaging
• Power consumption
• The amount of RAM and ROM on chip
• The number of I/O pins and the timer on chip
• How easy to upgrade to higher performance or lower
power-consumption versions
• Cost per unit
 Criteria for Choosing a Microcontroller
• Availability of software development tools, such as
compilers, assemblers, and debuggers
• Wide availability and reliable sources of the microcontroller
• The 8051 family has the largest number of diversified
(multiple source) suppliers
• Intel (original)
• Atmel
• Philips/Signetics
• AMD
• Infineon (formerly Siemens)
• Matra
• Dallas Semiconductor/Maxim
 Intel 8051 - Microcontroller
• Intel introduced 8051, referred as MCS-51, in 1981
• The 8051 is an 8-bit processor
• The CPU can work on only 8 bits of data at a time
• The 8051 had
• 128 bytes of RAM
• 4K bytes of on-chip ROM
• Two timers
• One serial port
• Four I/O ports, each 8 bits wide
• 6 interrupt sources
• The 8051 became widely popular after allowing other
manufactures to make and market any flavor of the 8051,
but remaining code-compatible
Intel 8051 - Microcontroller
Basic 8051 Architecture
 Intel 8051 Family
• The 8051 is a subset of the 8052
• The 8031 is a ROM-less 8051
• Add external ROM to it
• You lose two ports, and leave only 2 ports for I/O
operations
Feature 8051 8052 8031
ROM (On Chip program Space
4k 8k 0k
(Bytes))
RAM in bytes 128 256 128
Timers 2 3 2
I/O Pins 32 32 32
Serial Port 1 1 1
Interrupt Sources 6 8 6
 Various 8051 Microcontrollers
• 8751 microcontroller
• UV-EPROM
• PROM burner
• UV-EPROM eraser takes 20 min to erase
• AT89C51 from Atmel Corporation
• Flash (erase before write)
• ROM burner that supports flash
• A separate eraser is not needed
• DS89C4x0 from Dallas Semiconductor, now part of
Maxim Corp.
• Flash
• Comes with on-chip loader, loading program to on-
chip flash via PC COM port
 Various 8051 Microcontrollers
• DS5000 from Dallas Semiconductor
• NV-RAM (changed one byte at a time),RTC (real-time
clock)
• Also comes with on-chip loader
• OTP (one-time-programmable) version of 8051
• 8051 family from Philips
• ADC, DAC, extended I/O, and both OTP and flash
8051 Assembly Programming
 8051 Assembly Programming
Registers
• Register are used to store information temporarily, while the
information could be
• a byte of data to be processed, or an address pointing to
the data to be fetched
• The vast majority of 8051 register are 8-bit registers
• There is only one data type, 8 bits
• The 8 bits of a register are shown from MSB D7 to the LSB D0
• With an 8-bit data type, any data larger than 8 bits must
be broken into 8-bit chunks before it is processed
 8051 Assembly Programming
Registers
• The most widely used registers
• A (Accumulator)
• For all arithmetic and logic instructions
• B, R0, R1, R2, R3, R4, R5, R6, R7
• DPTR (data pointer), and PC (program counter)
 Structure of Assembly Language
• Assembly language instruction includes
• a mnemonic (abbreviation easy to remember)
• the commands to the CPU, telling it what those to do
with those items
• optionally followed by one or two operands
• the data items being manipulated
• A given Assembly language program is a series of
statements, or lines
• Assembly language instructions
• Tell the CPU what to do
• Directives (or pseudo-instructions)
• Give directions to the assembler
 Steps to Execute Assembly Program
The step of Assembly language program are outlines as
follows:
1. First we use an editor to type a program, many
excellent editors or word processors are available
that can be used to create and/or edit the program
• Notice that the editor must be able to produce an ASCII
file
• For many assemblers, the file names follow the usual
DOS conventions, but the source file has the extension
“asm“ or “src”, depending on which assembly you are
using
 Steps to Execute Assembly Program
2. The “asm” source file containing the program code
created in step 1 is fed to an 8051 assembler
• The assembler converts the instructions into machine
code
• The assembler will produce an object file and a list file
• The extension for the object file is “obj” while the
extension for the list file is “lst”
3. Assembler require a third step called linking
• The linker program takes one or more object code files
and produce an absolute object file with the extension
“abs”
• This abs file is used by 8051 trainers that have a monitor
program
 Steps to Execute Assembly Program
4. Next the “abs” file is fed into a program called “OH” (object
to hex converter) which creates a file with extension “hex”
that is ready to burn into ROM
• This program comes with all 8051 assemblers
• Recent Windows-based assemblers combine step 2
through 4 into one step
Steps to Execute Assembly Program
 Addressing Modes
8051 addressing modes are classified as follows.
1. Immediate addressing.
2. Register addressing.
3. Direct addressing.
4. Indirect addressing.
5. Relative addressing.
6. Absolute addressing.
7. Long addressing.
8. Indexed addressing.
9. Bit inherent addressing.
10. Bit direct addressing.
 Addressing Modes
1. Immediate addressing.
In this addressing mode the data is provided as a part of instruction
itself. In other words data immediately follows the instruction.
Eg. MOV A,#30H
ADD A, #83 # Symbol indicates the data is immediate.
2. Register addressing.
In this addressing mode the register will hold the data. One of the
eight general registers (R0 to R7) can be used and specified as the
operand.
Eg. MOV A,R0
ADD A,R6
R0 – R7 will be selected from the current selection of register bank.
The default register bank will be bank 0.
 Addressing Modes
3. Direct addressing
There are two ways to access the internal memory. Using direct
address and indirect address. Using direct addressing mode we can
not only address the internal memory but SFRs also. In direct
addressing, an 8 bit internal data memory address is specified as part
of the instruction and hence, it can specify the address only in the
range of 00H to FFH. In this addressing mode, data is obtained
directly from the memory.
Eg. MOV A,60h
ADD A,30h
4. Indirect addressing
The indirect addressing mode uses a register to hold the actual
address that will be used in data movement. Registers R0 and R1 and
DPTR are the only registers that can be used as data pointers.
Indirect addressing cannot be used to refer to SFR registers. Both R0
and R1 can hold 8 bit address and DPTR can hold 16 bit address.
Eg. MOV A,@R0
ADD A,@R1
MOVX A,@DPTR
 Addressing Modes
5. Indexed addressing.
In indexed addressing, either the program counter (PC), or the data
pointer (DTPR)—is used to hold the base address, and the A is used
to hold the offset address. Adding the value of the base address to
the value of the offset address forms the effective address. Indexed
addressing is used with JMP or MOVC instructions. Look up tables are
easily implemented with the help of index addressing.
Eg. MOVC A, @A+DPTR // copies the contents of memory location
pointed by the sum of the
accumulator A and the DPTR into
accumulator A.
MOVC A, @A+PC // copies the contents of memory location
pointed by the sum of the
accumulator A and the program counter
into accumulator A.
 8051 Microcontroller – Instruction Set
• The 8051 has 255 instructions
• Every 8-bit opcode from 00 to FF is used except for
A5.
• The instructions are grouped into 5 groups
• Arithmetic
• Logic
• Data Transfer
• Boolean
• Branching
 8051 – Arithmetic Instructions
• ADD
• 8-bit addition between the accumulator (A) and a
second operand.
• The result is always in the accumulator.
• The CY flag is set/reset appropriately.
• ADDC
• 8-bit addition between the accumulator, a second
operand and the previous value of the CY flag.
• Useful for 16-bit addition in two steps.
• The CY flag is set/reset appropriately.
 Example – 16 Bit Addition

Add 1E44H to 56CAH

CLR C ; Clear the CY flag
MOV A, 44H ; The lower 8-bits of the 1st number
ADD A, CAH ; The lower 8-bits of the 2nd number
MOV R1, A ; The result 0EH will be in R1. CY = 1.
MOV A, 1EH ; The upper 8-bits of the 1st number
ADDC A, 56H ; The upper 8-bits of the 2nd number
MOV R2, A ; The result of the addition is 75H

The overall result: 750EH will be in R2:R1. CY = 0.

 8051 – Arithmetic Instructions
• DA
• Decimal adjust the accumulator.
• Format the accumulator into a proper 2 digit packed BCD
number.
• Operates only on the accumulator.
• Works only after the ADD instruction.
• SUBB
• Subtract with Borrow.
• Subtract an operand and the previous value of the borrow
(carry) flag from the accumulator.
• A ← A - <operand> - CY.
• The result is always saved in the accumulator.
• The CY flag is set/reset appropriately.
 Example – BCD addition
Add 34 to 49 BCD
CLR C ; Clear the CY flag
MOV A, #34H ; Place 1st number in A
ADD A, #49H ; Add the 2nd number.
; A = 7DH
DA A ; A = 83H
 8051 – Arithmetic Instructions
• INC
• Increment the operand by one.
• The operand can be a register, a direct address, an
indirect address, the data pointer.
• DEC
• Decrement the operand by one.
• The operand can be a register, a direct address, an
indirect address.
• MUL AB / DIV AB
• Multiply A by B and place result in A:B.
• Divide A by B and place result in A:B.
 8051 – Logical Instructions
• ANL / ORL
• Work on byte sized operands or the CY flag.
ANL A, Rn ANL A, direct ANL A, @Ri
ANL A, #data ANL direct, A ANL direct, #data
ANL C, bit ANL C, /bit
• XRL
• Works on bytes only.
• CPL / CLR
• – Complement / Clear.
• – Work on the accumulator or a bit.
CLR P1.2
 8051 – Logical Instructions
• RL / RLC / RR / RRC
• Rotate the accumulator.
• RL and RR without the carry
• RLC and RRC rotate through the carry.
• SWAP A
• Swap the upper and lower nibbles of the accumulator.
• No compare instruction.
• Built into conditional branching instructions.
 8051 – Data Transfer Instructions
• MOV
• 8-bit data transfer for internal RAM and the SFR.
MOV A, Rn MOV A, direct MOV
A, @Ri
MOV A, #data MOV Rn, A MOV
Rn, direct
MOV Rn, #data MOV direct, A MOV direct,
Rn
MOV direct, direct MOV direct, @Ri MOV
direct, #data
MOV @Ri, A MOV @Ri, direct MOV
@Ri, #data
• MOV
• 1-bit data transfer involving the CY flag
• MOV C, bit
• MOV bit, C
 8051 – Data Transfer Instructions
• MOV
• 16-bit data transfer involving the DPTR
• MOV DPTR, #data
• MOVC
• Move Code Byte
• Load the accumulator with a byte from program
memory.
• Must use indexed addressing
• MOVC A, @A+DPTR
• MOVC A, @A+PC
 8051 – Data Transfer Instructions
• MOVX
• Data transfer between the accumulator and a byte from
external data memory.
• MOVX A, @Ri
• MOVX A, @DPTR
• MOVX @Ri, A
• MOVX @DPTR, A
• PUSH / POP
• Push and Pop a data byte onto the stack.
• The data byte is identified by a direct address from the
internal RAM locations.
• PUSH DPL
• POP 40H
 8051 – Data Transfer Instructions
• XCH
• Exchange accumulator and a byte variable
XCH A, Rn XCH A, direct
XCH A, @Ri
• XCHD
• Exchange lower digit of accumulator with the lower digit
of the memory location specified.
• XCHD A, @Ri
• The lower 4-bits of the accumulator are exchanged
with the lower 4-bits of the internal memory location
identified indirectly by the index register.
• The upper 4-bits of each are not modified.
 8051 – Boolean Instructions
• This group of instructions is associated with the single-bit
operations of the 8051.
• This group allows manipulating the individual bits of bit
addressable registers and memory locations as well as the
CY flag.
• The P, OV, and AC flags cannot be directly altered.
• This group includes:
• Set, clear, and, or complement, move.
• Conditional jumps.
• CLR
• Clear a bit or the CY flag.
• CLR P1.1
• CLR C
 8051 – Boolean Instructions
• SETB
• Set a bit or the CY flag.
• SETB A.2
• SETB C
• CPL
• Complement a bit or the CY flag.
• CPL 40H ; Complement bit 40 of the bit
addressable ; memory
• JC / JNC
• Jump to a relative address if CY is set / cleared.
• JB / JNB
• Jump to a relative address if a bit is set / cleared.
• JB ACC.2, <label>
 8051 – Branching Instructions
• The 8051 provides four different types of unconditional
jump instructions:
• Short Jump – SJMP
• Uses an 8-bit signed offset relative to the 1st
byte of the next instruction.
• Long Jump – LJMP
• Uses a 16-bit address.
• 3 byte instruction capable of referencing any
location in the entire 64K of program memory.
 8051 – Branching Instructions
• Absolute Jump – AJMP
• Uses an 11-bit address.
• 2 byte instruction
• The upper 3-bits of the address combine with the
5-bit opcode to form the 1st byte and the lower
8-bits of the address form the 2nd byte.
• The 11-bit address is substituted for the lower 11-
bits of the PC to calculate the 16-bit address of the
target.
• The location referenced must be within the 2K
Byte memory page containing the AJMP
instruction.
• Indirect Jump – JMP
• JMP @A + DPTR
 8051 – Branching Instructions

• The 8051 provides 2 forms for the CALL instruction:

• Absolute Call – ACALL
• Uses an 11-bit address similar to AJMP
• The subroutine must be within the same 2K page.
• Long Call – LCALL
• Uses a 16-bit address similar to LJMP
• The subroutine can be anywhere.
• Both forms push the 16-bit address of the next
instruction on the stack and update the stack pointer.
 8051 – Branching Instructions

• The 8051 provides 2 forms for the return instruction:

• Return from subroutine – RET
• Pop the return address from the stack and continue
execution there.
• Return from ISV – RETI
• Pop the return address from the stack.
• Restore the interrupt logic to accept additional interrupts
at the same priority level as the one just processed.
• Continue execution at the address retrieved from the
stack.
• The PSW is not automatically restored.
 8051 – Branching Instructions
• The 8051 supports 5 different conditional jump instructions.
• ALL conditional jump instructions use an 8-bit signed offset.
• Jump on Zero – JZ / JNZ
• Jump if the A == 0 / A != 0
• The check is done at the time of the instruction
execution.
• Jump on Carry – JC / JNC
• Jump if the C flag is set / cleared.
• Jump on Bit – JB / JNB
• Jump if the specified bit is set / cleared.
• Any addressable bit can be specified.
• Jump if the Bit is set then Clear the bit – JBC
• Jump if the specified bit is set.
• Then clear the bit.
 8051 – Branching Instructions
• Compare and Jump if Not Equal – CJNE
• Compare the magnitude of the two operands and jump if
they are not equal.
• The values are considered to be unsigned.
• The Carry flag is set / cleared appropriately.
CJNE A, direct, rel CJNE A, #data, rel
CJNE Rn, #data, rel CJNE @Ri, #data, rel
• Decrement and Jump if Not Zero – DJNZ
• Decrement the first operand by 1 and jump to the location
identified by the second operand if the resulting value is not
zero.
DJNZ Rn, rel DJNZ direct, rel
• No Operation
• NOP
 8051 – Programming Examples
1. Program to add three 8 bit numbers and to store
the 16 bit result in internal RAM
ORG 0000H
MOV R0, #35H
MOV R1, #0F0H
MOV R2, #0E2H
MOV R3, #00H
MOV A, R0
ADD A, R1
JNC DOWN
INC R3
DOWN: ADD A, R2
JNC NEXT
INC R3
NEXT: MOV 51H, A
MOV 50H, R3
END
 8051 – Programming Examples
2. Program to add an array of 8 bit numbers and to
store the 16 bit result in internal RAM
ORG 0000H
MOV R0, #50H
MOV R1, #08H
MOV R2, #00H
BACK: MOV A, @R0
ADD A, B
JNC DOWN
INC R2
CLR C
DOWN: INC R0
MOV B, A
DJNZ R1, BACK
MOV 40H, R2
MOV 41H, A
END
 8051 – Programming Examples
3. Program to convert two digit packed BCD to
unpacked BCD
ORG 0000H
MOV R1, #45H
MOV A, R1
ANL A, #0F0H
SWAP A
MOV R2, A
MOV A, R1
ANL A, #0FH
MOV R3, A
END
 8051 – Programming Examples
4. Program to convert two digit unpacked BCD to
packed BCD
ORG 0000H
MOV R1, #04H
MOV R2, #05H
MOV A, R1
SWAP A
ADD A, R2
END
 8051 – Programming Examples
5. Program to convert two digit packed BCD to ASCII
ORG 0000H
MOV R1, #25H
MOV A, R1
ANL A, #0F0H
SWAP A
ORL A, #30H
MOV R2, A
MOV A, R1
ANL A, #0FH
ORL A, #30H
MOV R3, A
END
 8051 – Programming Examples
6. Program to convert ACSII to two digit packed BCD
ORG 0000H
MOV R1, #35H
MOV R2, #37H
MOV A, R1
ANL A, #0FH
SWAP A
MOV R3, A
MOV A, R2
ANL A, #0FH
ADD A, R3
MOV R4, A
END
Thank You