ADVANCED RISC

MACHINE
 Introduction to ARM Ltd
Programmers Model
Instruction Set
System Design
Development Tools
 Founded in November 1990
 Spun out of Acorn Computers

 Designs the ARM range of RISC processor cores

 Licenses ARM core designs to semiconductor
partners who fabricate and sell to their customers.
 ARM does not fabricate silicon itself

 Also develop technologies to assist with the design-

in of the ARM architecture
 Software tools, boards, debug hardware, application

software, bus architectures, peripherals etc

ARM Partnership Model
ARM Powered Products
 Intellectual Property

 ARM provides hard and soft views to licencees

 RTL and synthesis flows
 GDSII layout
 Licencees have the right to use hard or soft views of the IP
 soft views include gate level netlists
 hard views are DSMs
 OEMs must use hard views
 to protect ARM IP
 Introduction to ARM Ltd
 Programmers Model
Instruction Sets
System Design
Development Tools
 Data Sizes and Instruction Sets

 The ARM is a 32-bit architecture.

 When used in relation to the ARM:

 Byte means 8 bits
 Halfword means 16 bits (two bytes)
 Word means 32 bits (four bytes)

 Most ARM’s implement two instruction sets

 32-bit ARM Instruction Set
 16-bit Thumb Instruction Set

 Jazelle cores can also execute Java bytecode

 Processor Modes

 The ARM has seven basic operating modes:

 User : unprivileged mode under which most tasks run

 FIQ : entered when a high priority (fast) interrupt is raised

 IRQ : entered when a low priority (normal) interrupt is raised

 Supervisor : entered on reset and when a Software Interrupt

instruction is executed

 Abort : used to handle memory access violations

 Undef : used to handle undefined instructions

 System : privileged mode using the same registers as user mode

 The ARM Register Set

Current Visible Registers

r0
Abort
Undef
SVC
IRQ
FIQ
User Mode
Mode
Mode
Mode
Mode
r1
r2
r3 Banked out Registers
r4
r5
r6 User FIQ IRQ SVC Undef Abort
r7
r8 r8 r8
r9 r9 r9
r10 r10 r10
r11 r11 r11
r12 r12 r12
r13 (sp) r13 (sp) r13 (sp) r13 (sp) r13 (sp) r13 (sp) r13 (sp)
r14 (lr) r14 (lr) r14 (lr) r14 (lr) r14 (lr) r14 (lr) r14 (lr)
r15 (pc)

cpsr
spsr spsr spsr spsr spsr spsr
 Register Organization Summary
User FIQ IRQ SVC Undef Abort
r0
r1
User
r2 mode
r3 r0-r7,
r4 r15, User User User User
and mode mode mode mode Thumb state
r5
cpsr r0-r12, r0-r12, r0-r12, r0-r12, Low registers
r6
r15, r15, r15, r15,
r7 and and and and
r8 r8 cpsr cpsr cpsr cpsr
r9 r9
r10 r10 Thumb state
r11 r11 High registers
r12 r12
r13 (sp) r13 (sp) r13 (sp) r13 (sp) r13 (sp) r13 (sp)
r14 (lr) r14 (lr) r14 (lr) r14 (lr) r14 (lr) r14 (lr)
r15 (pc)

cpsr
spsr spsr spsr spsr spsr

Note: System mode uses the User mode register set

 The Registers

 ARM has 37 registers all of which are 32-bits long.

 1 dedicated program counter
 1 dedicated current program status register
 5 dedicated saved program status registers
 30 general purpose registers

 The current processor mode governs which of several banks is

accessible. Each mode can access
 a particular set of r0-r12 registers
 a particular r13 (the stack pointer, sp) and r14 (the link register, lr)
 the program counter, r15 (pc)
 the current program status register, cpsr

Privileged modes (except System) can also access

 a particular spsr (saved program status register)
 Program Status Registers
31 28 27 24 23 16 15 8 7 6 5 4 0

N Z C V Q J U n d e f i n e d I F T mode
f s x c
 Condition code flags  Interrupt Disable bits.
 N = Negative result from ALU  I = 1: Disables the IRQ.
 Z = Zero result from ALU  F = 1: Disables the FIQ.
 C = ALU operation Carried out
 V = ALU operation oVerflowed  T Bit
 Architecture xT only

 T = 0: Processor in ARM state
Sticky Overflow flag - Q flag  T = 1: Processor in Thumb state
 Architecture 5TE/J only
 Indicates if saturation has occurred
 Mode bits

 Specify the processor mode
J bit
 Architecture 5TEJ only
 J = 1: Processor in Jazelle state
 Program Counter (r15)

 When the processor is executing in ARM state:

 All instructions are 32 bits wide
 All instructions must be word aligned
 Therefore the pc value is stored in bits [31:2] with bits [1:0] undefined (as
instruction cannot be halfword or byte aligned).

 When the processor is executing in Thumb state:

 All instructions are 16 bits wide
 All instructions must be halfword aligned
 Therefore the pc value is stored in bits [31:1] with bit [0] undefined (as
instruction cannot be byte aligned).

 When the processor is executing in Jazelle state:

 All instructions are 8 bits wide
 Processor performs a word access to read 4 instructions at once
 Exception Handling

 When an exception occurs, the ARM:

 Copies CPSR into SPSR_<mode>
 Sets appropriate CPSR bits
 Change to ARM state 0x1C FIQ
 Change to exception mode
0x18 IRQ
 Disable interrupts (if appropriate)
0x14 (Reserved)
 Stores the return address in LR_<mode>
 Sets PC to vector address 0x10 Data Abort
0x0C Prefetch Abort
 To return, exception handler needs to: 0x08 Software Interrupt
 Restore CPSR from SPSR_<mode>
0x04 Undefined Instruction
 Restore PC from LR_<mode>
0x00 Reset
This can only be done in ARM state. Vector Table
Vector table can be at
0xFFFF0000 on ARM720T
and on ARM9/10 family
devices
 Development of the
ARM Architecture

Improved
5TE Jazelle
Halfword
and signed
4 ARM/Thumb
Interworking Java bytecode 5TEJ
1 halfword /
CLZ execution
byte support
System SA-110 Saturated maths ARM9EJ-S ARM926EJ-S
2 mode
DSP multiply-
SA-1110 ARM7EJ-S ARM1026EJ-S
accumulate
instructions
3 ARM1020E SIMD Instructions
Thumb
instruction 4T Multi-processing
6
set XScale
Early ARM V6 Memory
architectures architecture (VMSA)
ARM7TDMI ARM9TDMI ARM9E-S
Unaligned data
ARM720T ARM940T ARM966E-S support ARM1136EJ-S
 Agenda

Introduction to ARM Ltd

Programmers Model
 Instruction Sets
System Design
Development Tools
 Conditional Execution and Flags

 ARM instructions can be made to execute conditionally by postfixing

them with the appropriate condition code field.
 This improves code density and performance by reducing the number of
forward branch instructions.
CMP r3,#0 CMP r3,#0
BEQ skip ADDNE r0,r1,r2
ADD r0,r1,r2
skip

 By default, data processing instructions do not affect the condition code

flags but the flags can be optionally set by using “S”. CMP does not
need “S”.
loop
… decrement r1 and set flags
SUBS r1,r1,#1
BNE loop if Z flag clear then branch
 Condition Codes

 The possible condition codes are listed below:

 Note AL is the default and does not need to be specified

Suffix Description Flags tested

EQ Equal Z=1
NE Not equal Z=0
CS/HS Unsigned higher or same C=1
CC/LO Unsigned lower C=0
MI Minus N=1
PL Positive or Zero N=0
VS Overflow V=1
VC No overflow V=0
HI Unsigned higher C=1 & Z=0
LS Unsigned lower or same C=0 or Z=1
GE Greater or equal N=V
LT Less than N!=V
GT Greater than Z=0 & N=V
LE Less than or equal Z=1 or N=!V
AL Always
 Examples of conditional
execution
 Use a sequence of several conditional instructions
if (a==0) func(1);
CMP r0,#0
MOVEQ r0,#1
BLEQ func

 Set the flags, then use various condition codes

if (a==0) x=0;
if (a>0) x=1;
CMP r0,#0
MOVEQ r1,#0
MOVGT r1,#1

 Use conditional compare instructions

if (a==4 || a==10) x=0;
CMP r0,#4
CMPNE r0,#10
MOVEQ r1,#0
 Data processing Instructions
 Consist of :
 Arithmetic: ADD ADC SUB SBC RSB
RSC
 Logical: AND ORR EOR BIC
 Comparisons: CMP CMN TST TEQ
 Data movement: MOV MVN

 These instructions only work on registers, NOT memory.

 Syntax:

<Operation>{<cond>}{S} Rd, Rn, Operand2

 Comparisons set flags only - they do not specify Rd

 Data movement does not specify Rn

 Second operand is sent to the ALU via barrel shifter.

 The Barrel Shifter
LSL : Logical Left Shift ASR: Arithmetic Right Shift

CF Destination 0 Destination CF

Multiplication by a power of 2 Division by a power of 2,

preserving the sign bit

LSR : Logical Shift Right ROR: Rotate Right

...0 Destination CF Destination CF

Division by a power of 2 Bit rotate with wrap around

from LSB to MSB

RRX: Rotate Right Extended

Destination CF

Single bit rotate with wrap around

from CF to MSB
 Using the Barrel Shifter:
The Second Operand
Register, optionally with shift operation
Operand Operand  Shift value can be either be:
1 2  5 bit unsigned integer
 Specified in bottom byte of another
register.
 Used for multiplication by constant
Barrel
Shifter

Immediate value
 8 bit number, with a range of 0-255.
 Rotated right through even number of
positions
ALU  Allows increased range of 32-bit
constants to be loaded directly into
registers

Result
 ARM Branches and Subroutines
 B <label>
 PC relative. ±32 Mbyte range.
 BL <subroutine>
 Stores return address in LR
 Returning implemented by restoring the PC from LR
 For non-leaf functions, LR will have to be stacked
func1 func2
STMFD sp!, :
: {regs,lr}
:
: :
:
BL func1 BL func2
:
: :
:
: LDMFD sp!,
{regs,pc} MOV pc, lr
 Example ARM-based System

16 bit RAM 32 bit RAM

Interrupt
Controller
Peripherals I/O
nIRQ nFIQ

ARM
Core
8 bit ROM
 AMBA
Arbiter Reset

ARM
TIC
Remap/
External Bus Interface Timer
Pause
ROM External

Bridge
Bus
Interface
External
RAM On-chip Interrupt
Decoder RAM Controller

AHB or ASB APB

System Bus Peripheral Bus

 AMBA  ACT
 Advanced Microcontroller Bus  AMBA Compliance Testbench
Architecture
 PrimeCell
 ADK
 Complete AMBA Design Kit
 ARM’s AMBA compliant peripherals
 The RealView Product Families

Compilation Tools Debug Tools Platforms

ARM Developer Suite (ADS) – AXD (part of ADS) ARMulator (part of ADS)
Compilers (C/C++ ARM & Thumb), Trace Debug Tools Integrator™ Family
Linker & Utilities
Multi-ICE
Multi-Trace

RealView Compilation Tools (RVCT) RealView Debugger (RVD) RealView ARMulator ISS
(RVISS)
RealView ICE (RVI)
RealView Trace (RVT)
 ARM Debug Architecture
Ethernet

Debugger (+ optional
trace tools)

JTAG port Trace Port

 EmbeddedICE Logic
 Provides breakpoints and processor/system
access
TAP
 JTAG interface (ICE) controller
 Converts debugger commands to JTAG ETM
signals
EmbeddedICE
 Embedded trace Macrocell (ETM) Logic
 Compresses real-time instruction and data
access trace
 Contains ICE features (trigger & filter logic)
ARM
 Trace port analyzer (TPA) core
 Captures trace in a deep buffer
Thank you