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PD_Engineer_Interview_QA

The document is a compilation of interview questions and answers prepared by Mudragada Srinivas, detailing his experience and expertise in Physical Design and Static Timing Analysis with a focus on various technology nodes. It covers topics such as project experience, synthesis processes, timing optimization techniques, and key considerations for design handoff. The document emphasizes the importance of timing, power, and area in synthesis, along with specific methodologies for addressing timing issues.

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3 views

PD_Engineer_Interview_QA

The document is a compilation of interview questions and answers prepared by Mudragada Srinivas, detailing his experience and expertise in Physical Design and Static Timing Analysis with a focus on various technology nodes. It covers topics such as project experience, synthesis processes, timing optimization techniques, and key considerations for design handoff. The document emphasizes the importance of timing, power, and area in synthesis, along with specific methodologies for addressing timing issues.

Uploaded by

devisana4
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
Available Formats
Download as PPTX, PDF, TXT or read online on Scribd
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PD Engineer Interview Questions

& Answers
Prepared by Mudragada Srinivas
Introduce About Yourself
• My name is Mudragada Srinivas, and I have
over 4 years of experience in Synthesis,
Physical Design, and Static Timing Analysis
(STA). I have worked on 3nm, 7nm, and 28nm
technologies.
Tell Briefly About Your Projects
• Worked on Qualcomm (3nm), Broadcom
(7nm, 28nm), and Marvell (7nm) projects
involving STA, timing closure, and PNR.
Highest Frequency & Time Period
• Worked on 1 GHz designs with periods of 1ns
(1 GHz) and 3.2ns (312.5 MHz).
Corners Worked On
• SS, FF, TT, and PVT variations. SS is dominant
due to worst-case delay.
Hold Checking in Synthesis
• Hold violations are fixed post-route to avoid
over-constraining synthesis.
Main Inputs & Extra Inputs for
Synthesis
• Main: RTL, SDC, Libraries. Extra: SAIF, UPF.
Three Steps in Synthesis & Linking
• Translation, Optimization, Mapping. Linking
resolves cell dependencies before
optimization.
Uncertainty & Percentage Used
• Accounts for OCV, clock jitter. Typically 5-10%
of clock period.
Optimization Techniques for Timing
• Tool: Path balancing, buffer insertion. Manual:
ECO, skew balancing, cell upsizing.
Timing Issues & Fixes
• Hold violations fixed by buffers. Setup
violations fixed by reducing path delay.
Pre-PPA Checks
• Check congestion, DRC violations, and timing
closure.
Interesting Task in Project
• Manual ECOs for timing closure and
debugging challenging timing paths.
CCD & Prepone/Postpone Values
• CCD optimizes setup/hold. Values based on
timing margins and clock skews.
PPA Priority in Synthesis
• Timing > Power > Area.
VT Flavor Relations
• LVT: Speed, more power. HVT: Less power,
more delay.
LVT vs ULVT Selection Criteria
• Factors include leakage constraints, area
availability.
Netlist Checks Before PD Handoff
• Verify synthesis reports, timing constraints,
scan chain integrity, and clean DRC violations.

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