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unit3 io mapping

The document discusses I/O mapping and interfacing I/O devices with a microprocessor (MP), detailing the processes for reading from input devices and writing to output devices using specific signals and unique addresses. It explains the instructions used for input (IN) and output (OUT) operations, highlighting the 8-bit address range and the timing diagrams for these instructions. Additionally, it contrasts I/O mapped I/O with memory mapped I/O, noting that in the latter, I/O devices are treated as memory locations within a shared address space.

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27 views12 pages

unit3 io mapping

The document discusses I/O mapping and interfacing I/O devices with a microprocessor (MP), detailing the processes for reading from input devices and writing to output devices using specific signals and unique addresses. It explains the instructions used for input (IN) and output (OUT) operations, highlighting the 8-bit address range and the timing diagrams for these instructions. Additionally, it contrasts I/O mapped I/O with memory mapped I/O, noting that in the latter, I/O devices are treated as memory locations within a shared address space.

Uploaded by

pooja.geet11
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
Available Formats
Download as PPT, PDF, TXT or read online on Scribd
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I/O mapping

Interfacing I/O devices with MP


•Input device
•Output device
Example: -
When MP wants to read data from input device, the input buffer
should enable

Where the signal used to detect the input port


1. RD as IOR
2. Combinations of address lines
Similarly if Mp wants to write the data on output device, the out
put latch should active
Where the signal used to detect the input port
 1. WR as IOW
 2. Combinations of address lines
Concludes: - Here we can say that I/O devices should have
unique address
 Instruction used to input or output data
  IN 8 bit add
 * It is used to input data to accumulator from a port with 8 bit
address
 It is 2 byte instruction and no flags are modified
 * Here the 8 bit address is transferred to A0 –A7 and same as to
access the data from
 port A8 –A15
Example : - IN 20H
Timing Diagram of instruction IN 20H

NOTE : - Since the I/O address is 8 bit so the range of I/O


address is from 00 H to FF H
Hence total 256 address may possible for I/O mapping
 Q.1 What is the status of A8 –A15 while the 3rd T state of In
instruction
 Ans We have 16 bit of address line in 8085 but in I/O
mapping the specified address is of 8 bit so to implement
this 8 bit address is transferred on both address group

 Out 8 bit add


* It is used to send the data for accumulator to output
port
It is 2 byte instruction and no flags are modified
* Here the 8 bit address is transferred to A0 –A7 and
same as to access the data from
port A8 –A15
Timing diagram of OUT 20H
In 3rd T state the address lines are loaded by
specified address
I/O mapped I/O
In I/O mapped I/O we have to specific add for I/O device
this address are provided by Decoder logic
Example- Interface Input buffer with input address FF H
And out put latch with address FE H
Example 2
Interface 8 LED to 8085 using buffer and latch as a input and
out put device and also write a program to take data from to
take switched data from input buffer and display it on LED
Input address is FF H
Output address is FE H
Connect switch with buffer and Led with latch
Input logic 0 switch is pressed
1 other wise
output logic 0 LED glow
1 Led off
Instead of using lower order address line one can use
higher order address line so that demultiplexing of lower
order address and data line may be neglected
Program: -
up IN FF H
CMA
Out FEH
JMP up
HLT
Shadowing Effect
While designing decoder logic for I/O mapped if the number
of I/O devices are less we can use linear or partial decoding
Here we consider some of the address line as Do’t care Due to
this instead of providing specific address we get multiple
address
Memory Mapped I/O
In memory mapped I/O technique I/O device can be treated as
memory location
There is no separate add and I/O address
I/O address is not 256 here but whole 64 kb memory is shared
by I/O and memory

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