Week 11

Digital Logic Design

Sequential
Logic
 • It consists of a combinational circuit to which storage
elements are connected to form a feedback path.
• The storage elements are devices capable of storing
binary information.
• The binary information stored in these elements at
any given time defines the state of the sequential
SEQUENTI circuit at that time.
• The block diagram demonstrates that the outputs in a
AL sequential circuit are a function not only of the inputs,
CIRCUITS but also of the present state of the storage elements
Types of Sequential Circuits
• There are two main types of sequential circuits, and their
classification is a function of the timing of their signals:
• Synchronous Sequential Circuits
All Sequential components get updated at the same time. The
time is usually provided as the Clock. All components have
the same Clock and get updated simultaneously.
The Clock is provided by a Clock Generator which provides a
clock signal having the form of a periodic train of clock pulses.

• Asynchronous Sequential Circuits

The sequential components get updated individually without
any synchronization.
Synchrono
us clocked
sequential
circuit
Latches
Storage Element
Latch : A Storage Element
• A storage element in a digital circuit can maintain a
binary state indefinitely (as long as power is
delivered to the circuit), until directed by an input
signal to switch states.
• Storage elements that operate with signal levels
(rather than signal transitions) are referred to as
latches; those controlled by a clock transition are
flip-flops.
• Latches are said to be level sensitive devices; flip-
flops are edge-sensitive devices.
• The two types of storage elements are related
because latches are the basic circuits from which all
flip-flops are constructed.
 SR Latch

Functionality type: RS,JK,T,D

Operation mode: (latch , Transparent)
SR Latch
SR Latch with NAND Gate
 SR Flip flop Function Table Excitation Table
S R Q Q(t+1) S R Q(t+1) Q Q(t+1) S R
0 0 0 0 0 0 0 D
0 0 Q(t)
0 0 1 1 0 1 1 0
0 1 0
0 1 0 0
1 0 1 1 0 0 1
0 1 1 0
1 1 x 1 1 D 0
1 0 0 1
1 0 1 1
1 1 0 x
1 1 1 x

Truth Table
S’R’ S’R SR SR’

Q’ x 1
Q 1 X 1

Q(t+1)= S + R’Q(t)
 JK Flip flop Function Table Excitation Table
J K Q Q(t+1) J K Q(t+1) Q Q(t+1) J K
0 0 0 0 0 0 0 D
0 0 Q(t)
0 0 1 1 0 1 1 D
0 1 0
0 1 0 0
1 0 1 1 0 D 1
0 1 1 0
1 1 Q(t)’ 1 1 D 0
1 0 0 1
1 0 1 1
1 1 0 1
1 1 1 0

Truth Table
J’K’ J’K JK JK’

Q’ 1 1
Q 1 1

Characteristic Equation: Q(t+1)= JQ’ +K’Q

 T Flip flop Truth Table Excitation Table
J K Q Q(t+1) T Q Q(t+1) Q Q(t+1) T
0 0 0 0 0 0 0 0 0 0
0 0 1 1 0 1 1 0 1 1
0 1 0 0
1 0 1 1 0 1
0 1 1 0
1 1 0 1 1 0
1 0 0 1
1 0 1 1
1 1 0 1 T Q(t+1)
1 1 1 0 0 Q(t)
Truth Table 1 Q(t)’
T’ T Function Table
Q’ 1
Q 1

Characteristic Equation: Q(t+1)= TQ’ +T’Q

D Latch
(Transparent Latch)
 D Flip flop Truth Table Excitation Table
J K Q Q(t+1) D Q Q(t+1) Q Q(t+1) D
0 0 0 0 0 0 0 0 0 0
0 0 1 1 0 1 0 0 1 1
0 1 0 0
1 0 1 1 0 0
0 1 1 0
1 1 1 1 1 1
1 0 0 1
1 0 1 1
1 1 0 1
D Q(t+1)
1 1 1 0
0 0
Truth Table
1 1
D’ D
1 Function Table
Q’
Q 1

Characteristic Equation: Q(t+1)= D

D Latch (Transparent Latch)

One way to eliminate the

undesirable condition of the
Instead of S and R input this
indeterminate state in the
Latch has just one Input (D),
SR latch is to ensure that
other than Enable.
inputs S and R are never
equal to 1 at the same time
Graphic symbols for latches
Flip Flop
Flip Flop
• The D latch with pulses in its control input is essentially a flip-flop that is triggered every time the
pulse goes to the logic-1 level.
• As long as the pulse input remains at this level, any changes in the data input will change the
output and the state of the latch.
• When latches are used for the storage elements, a serious difficulty arises.
• The state transitions of the latches start as soon as the clock pulse changes to the logic-1
level.
• The new state of a latch appears at the output while the pulse is still active.
• This output is connected to the inputs of the latches through the combinational circuit.
• If the inputs applied to the latches change while the clock pulse is still at the logic-1 level, the
latches will respond to new values and a new output state may occur.
• The result is an unpredictable situation, since the state of the latches may keep changing for
as long as the clock pulse stays at the active level.
Latch vs Flip
Flop
• The problem with the latch
is that it responds to a
change in the level of a
clock pulse.
• The key to the proper
operation of a flip-flop is to
trigger it only during a
signal transition.
 The timing of the response of a flip-flop to input data
and to the clock must be taken into consideration when
one is using edge-triggered flip-flops.

There is a minimum time called the setup time during

which the D input must be maintained at a constant
Flip flop value prior to the occurrence of the clock transition.
and Similarly, there is a minimum time called the hold time
Delays during which the D input must not change after the
application of the positive transition of the clock.

The propagation delay time of the flip-flop is defined as

the interval between the trigger edge and the
stabilization of the output to a new state