Sequential Circuit

• Digital electronics is classified into combinational logic and sequential logic.

• Combinational logic output depends on the present inputs levels, whereas sequential
logic output not only depends on the input levels, but also previous outputs.

Sequential Logic Circuits

 Combinational circuits are
easy to design and faster than
the sequential circuits.

 sequential circuits are

difficult to design and slower
than Combinational circuits .
Storage Elements: Latches and Flip-Flops:
• A storage element in a digital circuit can maintain a binary state indefinitely (as long
as power is delivered to the circuit), until directed by an input signal to switch states.

• Storage elements that operate with signal levels (rather than signal transitions) are
referred to as latches ; those controlled by a clock transition are flip-flops.

• Latches are said to be level sensitive devices; flip-flops are edge-sensitive devices.
Contd.
• The memory elements are devices capable of storing binary info. The binary info
stored in the memory elements at any given time defines the state of the sequential
circuit. The input and the present state of the memory element determine the output.
• There are two types of sequential circuits. Their classification depends on the timing
of their signals:
• Synchronous sequential circuits
This type of system uses storage elements called flip-flops that are employed to change
their binary value only at discrete instants of time.
• Asynchronous sequential circuits
This is a system whose outputs depends upon the order in which its input variables
change and can be affected at any instant of time.
Synchronous clocked sequential circuit

The outputs are formed by a combinational logic function of the inputs to the circuit or the values stored in
the flip-flops. The value that is stored in a flip-flop when the clock pulse occurs is also determined by the
inputs to the circuit or the values presently stored in the flip-flop. The new value is stored (i.e., the flip-flop
is updated) when a pulse of the clock signal occurs.
Gated S-R Latch or Clocked S-R flip flop
• The operation of the basic SR latch can be modified by providing an additional input
• signal that determines (controls) when the state of the latch can be changed by
determining whether S and R (or S and R ) can affect the circuit.

Note: The case S = R = 1 gives an output in which the Q and Q’ gives same output, which is
undetermined or possible. Ex: S = R = Q (PS) = 1 then Q (NS) = 1 and Q’ also 1, which is not possible.
Timing Diagram of S R flip flop
E
Gated D Latch
• In S R flip flop S=1 and R= 1 is invalid state. Also S=0 and R=0 which is a memory
state or hold state can be done by putting the enable or clock input as low.
• So the usable state is S=0, R=1 and S=1, R=0. We make some changes in the gated S
R flip flop to make gated D latch.
Edge Triggered flip flop
• In the gated S-R and D- latch, the inputs are processed as per the level of the enable
input. If the level is HIGH then the gated latch takes the input and change the output
accordingly but when the enable input is LOW in that duration the gated latch hold its
output (memory state) .
• The flip flops using the clock signal are called the clocked flip flop. Clocked flip-flop
can change state only when the clock makes a transition. As per the transition, the flip
flop can be positive edge triggered (0 to 1 transition) or negative edge triggered (1 to
0 transition).
Edge Triggered SR

Positive edge triggered

Negative edge triggered

Timing diagram of positive edge triggered
S R flip flop

Timing Diagram
J K flip flop and Racing Condition
• To use the S=1 and R=1 input condition , we modify the S R flip flop. But it has a
problem of Racing condition or race around condition i.e. when the input to this flip
flop is J=1 and K=1 and if the clock input is HIGH then the output will toggle
throughout the ON duration of the clock.
• We do not know what is the exact value when S = R = 1, which says uncertainty.

J K flip flop
Racing condition
Avoiding racing condition
• To avoid racing condition we have three solution
• 1) The clock ON duration should be less than the propagation delay of the flip flop
• 2) Edge triggered flip flop (change state at clock transition)
• 3) Master- Slave configuration

• Edge triggered JK flip flop

Edge triggered J K flip flop Function table

Master Slave JK flip flop
Link: https://www.youtube.com/watch?v=PVjYyYjPHRM

The Master-Slave Flip-Flop is basically a combination of two JK flip-flops connected together in a series
configuration. Out of these, one acts as the “master” and the other as a “slave”. The output from the master
flip flop is connected to the two inputs of the slave flip flop whose output is fed back to inputs of the master
flip flop. In addition to these two flip-flops, the circuit also includes an inverter. The inverter is connected to
clock pulse in such a way that the inverted clock pulse is given to the slave flip-flop. In other words if CP=0
for a master flip-flop, then CLK=1 for a slave flip-flop and if CLK=1 for master flip flop then it becomes 0
for slave flip flop.
Working of a Master Slave flip flop
• When the clock pulse goes to 1, the slave is isolated; J and K inputs may affect the state of the system. The slave flip-
flop is isolated until the CLK goes to 0. When the CLK goes back to 0, information is passed from the master flip-flop
to the slave and output is obtained.
• Firstly the master flip flop is positive level triggered and the slave flip flop is negative level triggered, so the master
responds before the slave.
• If J=0 and K=1, the high Q’ output of the master goes to the K input of the slave and the clock forces the slave to
reset, thus the slave copies the master.
• If J=1 and K=0, the high Q output of the master goes to the J input of the slave and the Negative transition of the
clock sets the slave, copying the master.
• If J=1 and K=1, it toggles on the positive transition of the clock and thus the slave toggles on the negative transition
of the clock.
• If J=0 and K=0, the flip flop is disabled and Q remains unchanged.

• In the timing diagram Qm is output of master FF and Qs is the output

of slave FF
T flip flop
• T or Toggle flip flop,
• This flip flop is common in counter design
• Output toggles if the input is T=1
• ..and holds its present state if the input is T=0
Asynchronous input of FF
• For the clocked FFs, the S R, D and J .K inputs are called synchronous inputs, because their
effect on the flip flop output is synchronized with the clock input.
• Most IC flip flops also have one or more asynchronous inputs. These asynchronous inputs
affect the flip flop output independently of the synchronous inputs and the clock input. These
asynchronous inputs can be used to SET the flip flop to 1 state or RESET the flip flop to the 0
state. They are normally labelled as PRESET and CLEAR. CLR or CLEAR to RESET your
output and PRESET or PRE to set your output.

Normal Operation
FLIP FLOP CONVERSIONS
• SR to D • D to T
• SR to JK • D to SR
• SR to T • T to D
• JK to T
• JK to D
• JK to SR
 PROCEDURE FOR CONVERSION

1. Draw the block diagram of the target flip flop from the
given problem.
2. Write truth table for the target flip-flop.
3. Write excitation table for the available flip-flop.
4. Draw k-map for target flip-flop.
5. Draw the block diagram.
 SR(Available) to D(Target) Flip flop Conversion
• Truth table • Excitation table
Present Next Present
Input Next state Flip flop Inputs
state state state

D Qn Qn+1 Qn Qn+1 S R

0 0 0 0 0 0 X

0 1 0 1 0 0 1

1 0 1 0 1 1 0

1 1 1 1 1 X 0
 SR to D Flip flop Conversion
Conversion Table
K- MAP
Present SIMPLIFICATION
Input Next state Flip flop Inputs
state

D Qn Qn+1 S R

0 0 0 0 X

0 1 0 0 1

1 0 1 1 0

1 1 1 X 0
SR to D
 SR(Available) to JK(Target) Flip-Flop
Conversion Table
Present
Input Next State Flip-Flop Inputs
State
J K Qn Qn+1 S R

0 0 0 0 0 X

0 0 1 1 X 0

0 1 0 0 0 X

0 1 1 0 0 1

1 0 0 1 1 0

1 0 1 1 X 0

1 1 0 1 1 0

1 1 1 0 0 1
SR to JK
• K-map Simplification
Logic Diagram (SR to JK)
SR(Available) to T(Target)
Conversion Table
K- MAP
SIMPLIFICATION
Present
Input Next state Flip flop Inputs
state

T Qn Qn+1 S R

0 0 0 0 X

0 1 1 X 0

1 0 1 1 0

1 1 0 0 1
Logic Diagram (SR to T)
JK(Available) to T FF
Present Next K- MAP
Input Flip flop Inputs SIMPLIFICATION
state state

T Qn Qn+1 J K

0 0 0 0 X

0 1 1 X 0

1 0 1 1 x

1 1 0 x 1
Logic Diagram (JK to T)
 JK(Available) to D(Target)Flip-flop
Conversion Table K- MAP
SIMPLIFICATION
Present Next
Input Flip flop Inputs
state state

D Qn Qn+1 J K

0 0 0 0 X

0 1 0 X 1

1 0 1 1 x

1 1 1 x 0
Logic Diagram (JK to D)
D(Available) to T(Target)Flip-Flop
Conversion Table
Present Flip flop K- MAP
Input Next state SIMPLIFICATION
state Inputs

T Qn Qn+1 D

0 0 0 0

0 1 1 1

1 0 1 1

1 1 0 0
Logic Diagram(D to T)
 T (Available) to D(Target) Flip-flop
Conversion Table Conversion
Present Flip flop K- MAP SIMPLIFICATION
Input Next state
state Inputs

D Qn Qn+1 T

0 0 0 0

0 1 0 1

1 0 1 1

1 1 1 0
 JK(Available) to SR(Target)Flip-flop
Conversion Table
conversion
Present
Input Next State Flip-Flop Inputs
State
S R Qn Qn+1 J K

0 0 0 0 0 X

0 0 1 1 X 0

0 1 0 0 0 X

0 1 1 0 X 1

1 0 0 1 1 X

1 0 1 1 X 0

1 1 0 X X X

1 1 1 X X X
JK(Available) to SR(Target)Flip-flop conversion
JK to SR
• Logic Diagram
D(Available) to SR(Target) Flip-Flop
Conversion Table Conversion
Present
Input Next State Flip-Flop Inputs
State
S R Qn Qn+1 J K

0 0 0 0 0 0

0 0 1 1 1 1

0 1 0 0 0 0

0 1 1 0 0 0

1 0 0 1 1 1

1 0 1 1 1 1

1 1 0 X X X

1 1 1 X X X
D to SR
K- MAP
SIMPLIFICATION
Logic Diagram For D to JK