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L9 8086 Interface Intro

The Intel 8086 microprocessor, introduced in 1978, was the first 16-bit microprocessor from Intel, featuring a 40-pin DIP package and operating at clock frequencies between 5MHz and 10MHz. It can address a maximum of 1MB of memory and utilizes a single-ended clock with a 33% duty cycle. The document also outlines the interfacing components and machine cycles associated with the 8086, including memory read and write operations.

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1 views

L9 8086 Interface Intro

The Intel 8086 microprocessor, introduced in 1978, was the first 16-bit microprocessor from Intel, featuring a 40-pin DIP package and operating at clock frequencies between 5MHz and 10MHz. It can address a maximum of 1MB of memory and utilizes a single-ended clock with a 33% duty cycle. The document also outlines the interfacing components and machine cycles associated with the 8086, including memory read and write operations.

Uploaded by

f20230225
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
Available Formats
Download as PPTX, PDF, TXT or read online on Scribd
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Intel 8086

Microprocessor
Interfacing Introduction
Overview

• Introduced in 1978
• First 16-bit microprocessor from Intel
(World’s first 16-bit processor was MN1610 from
Panafacom, Japan released in 1975)
• 40-pin DIP package
• Around 29000 transistors in 3um technology
• Uses +5V single supply and runs at clock
frequency 5MHz to 10MHz
• Can address maximum 1MB memory
2
Overview

Single ended clock with


33% duty cycle

3
Overview

5 V Supply and ground

4
Overview

Lower 16 bits of
Address, Upper 4
multiplexed with bits of
Data Address

5
Overview

Address latch enable.


Distinguishes whether
AD0-AD15 contains
valid address or not

6
Overview

Used distinguish
between memory
access and
input/output device
access

7
Let’s build an 8086 Computer
Vcc
min/max

8086

8
Let’s build an 8086 Computer
Vcc
Vcc
min/max
8284A
CLK
ClockGen
RES READY
RESET

8086

9
Let’s build an 8086 Computer
Vcc
Vcc
min/max
8284A
CLK
ClockGen
RES READY
RESET

8086
AD15-AD0 74S373
A19-A16 ADDR/DATA
Octal latch Address (A19:A0)

ALE STB
DEN
DT/R

OE
8286 Data (D15:D0)
Transceiver
T

10
Let’s build an 8086 Computer
Vcc
Vcc
min/max
8284A
CLK
ClockGen
RES READY RD

RESET WR

8086
AD15-AD0 74S373
A19-A16 ADDR/DATA
Octal latch Address (A19:A0)

ALE STB
DEN
DT/R

OE
8286 Data (D15:D0)
Transceiver
T

RAM
11
Let’s build an 8086 Computer
Vcc
Vcc
min/max
8284A
CLK
ClockGen
RES READY RD

RESET WR

8086
AD15-AD0 74S373
A19-A16 ADDR/DATA
Octal latch Address (A19:A0)

ALE STB
DEN
DT/R

OE
8286 Data (D15:D0)
Transceiver
T

RAM ROM
12
Let’s build an 8086 Computer
Vcc
Vcc
min/max
8284A
CLK
ClockGen
RES READY RD

RESET WR

8086
AD15-AD0 74S373
A19-A16 ADDR/DATA
Octal latch Address (A19:A0)

ALE STB
DEN
DT/R

OE
8286 Data (D15:D0)
Transceiver
T

RAM ROM Peripheral


13
Let’s build an 8086 Computer
Vcc
Vcc
min/max
8284A
CLK IO/M
ClockGen
RES READY RD
RESET WR

8086
AD15-AD0 74S373
A19-A16 ADDR/DATA
Octal latch Address (A19:A0)

ALE STB
DEN
Addr
DT/R
Decode
r
OE
8286 Data (D15:D0)
Transceiver
T

CS CS

RAM ROM Peripheral


14
State

o Operations of 8086 (and in general all processors) are synchronized


with a clock signal (a square wave)
o The clock is usually generated by a crystal
o 8086 maximum clock frequency is between 5MHz to 10MHz
o A single clock cycle is referred as a state (or T-state)

T-State
o Conventionally measured between 2 consecutive falling clock edges
15
Machine Cycle

o A basic operation performed by the processor for executing an


instruction is referred as a machine cycle
o 8086 supports different machine cycles such as
o Instruction fetch machine cycle
o Memory read machine cycle
o Memory write machine cycle
o I/O read machine cycle
o I/O write machine cycle
o Interrupt acknowledge machine cycle
o Bus idle machine cycle 16
Memory read Machine Cycle (Eg: MOV AX,
[2000H])
T1
Vcc
min/max
CLK CLK
READY RD

RESET WR
ALE
8086 02000H 02000H
74S373
M/IO AD15-AD0
A19-A16 ADDR/DATA
Octal latch Address (A19:A0)
0H
ALE STB
ADDR/Stat A19:A16
DEN
DT/R
BHE
2000H OE
ADDR/DATA A15:A0 8286 Data (D15:D0)
Transceiver
RD T

DT/R
RAM (1 MB)
17

DEN
Memory read Machine Cycle (Eg: MOV AX,
[2000H])
T1 T2
Vcc
min/max
CLK CLK
READY RD

RESET WR
ALE
8086 ZZZZ 02000H
74S373
M/IO AD15-AD0
A19-A16 ADDR/DATA
Octal latch Address (A19:A0)

ALE STB
ADDR/Stat A19:A16 S6-S3
DEN
DT/R
BHE S7
OE
ADDR/DATA A15:A0 8286 Data (D15:D0)
Transceiver
RD T

DT/R
RAM (1 MB)
DEN
Memory read Machine Cycle (Eg: MOV AX,
[2000H])
T1 T2 T3
Vcc
min/max
CLK CLK
READY RD

RESET WR
ALE
8086 1234H 02000H
74S373
M/IO AD15-AD0
A19-A16 ADDR/DATA
Octal latch Address (A19:A0)

ALE STB
ADDR/Stat A19:A16 S6-S3
DEN
DT/R
BHE S7
1234H OE 1234H
ADDR/DATA A15:A0 D15:D0 8286 Data (D15:D0)
Transceiver
RD T

DT/R
RAM (1 MB)
19

DEN
Memory read Machine Cycle (Eg: MOV AX,
[2000H])
T1 T2 T3 T4
Vcc
min/max
CLK CLK
READY RD

RESET WR
ALE
8086 ZZZZ 02000H
74S373
M/IO AD15-AD0
A19-A16 ADDR/DATA Octal latch Address (A19:A0)

ALE STB
ADDR/Stat A19:A16 S6-S3
DEN
DT/R
BHE S7
OE
ADDR/DATA A15:A0 D15:D0 8286 Data (D15:D0)
Transceiver
RD T

DT/R
RAM (120MB)
20

DEN
Memory read Machine Cycle (Eg: MOV AX,
[2000H])
Memory Access Time

CLK

ALE

M/IO

ADDR/Stat A19:A16 S6-S3

BHE S7

ADDR/DATA A15:A0 D15:D0

RD

DT/R
2121

DEN
Memory write Machine Cycle (Eg: MOV
[2000H],AX)
T1
Vcc
min/max
CLK CLK
READY RD

RESET WR
ALE
8086 02000H 02000H
74S373
M/IO AD15-AD0
A19-A16 ADDR/DATA
Octal latch Address (A19:A0)
0H
ALE STB
ADDR/Stat A19:A16
DEN
DT/R
BHE
2000H OE
ADDR/DATA A15:A0 8286 Data (D15:D0)
Transceiver
WR T

DT/R
RAM (1 MB)
22

DEN
Memory write Machine Cycle
T1 T2
Vcc
min/max
CLK CLK
READY RD

RESET WR
ALE
8086 1234H 02000H
74S373
M/IO AD15-AD0
A19-A16 ADDR/DATA
Octal latch Address (A19:A0)

ALE STB
ADDR/Stat A19:A16 S6-S3
DEN
DT/R
BHE S7
1234 H OE 1234H
ADDR/DATA A15:A0 DATA (D15:D0) 8286 Data (D15:D0)
Transceiver
WR T

DT/R
RAM (1 MB)
23

DEN
Memory write Machine Cycle
T1 T2 T3
Vcc
min/max
CLK CLK
READY RD

RESET WR
ALE
8086 1234H 02000H
74S373
M/IO AD15-AD0
A19-A16 ADDR/DATA
Octal latch Address (A19:A0)

ALE STB
ADDR/Stat A19:A16 S6-S3
DEN
DT/R
BHE S7
1234 H OE 1234H
ADDR/DATA A15:A0 DATA (D15:D0) 8286 Data (D15:D0)
Transceiver
WR T

DT/R
RAM (1 MB)
24

DEN
Memory write Machine Cycle
T1 T2 T3 T4
Vcc
min/max
CLK CLK
READY RD

RESET WR
ALE
8086 ZZZZ 02000H
74S373
M/IO AD15-AD0
A19-A16 ADDR/DATA Octal latch Address (A19:A0)

ALE STB
ADDR/Stat A19:A16 S6-S3
DEN
DT/R
BHE S7
OE
ADDR/DATA A15:A0 DATA (D15:D0) 8286 Data (D15:D0)
Transceiver
WR T

DT/R
RAM (1 MB)
25

DEN
WAIT states

• It is possible that the memory/peripherals interfaced with 8086 are


not fast enough to read/write with in the stipulated time (4 T-states)
• In this case there should be a mechanism for them to request the
processor for additional time
• That is done with the help of the READY signal
• During T3 state, 8086 checks whether the READY signal is
asserted
• If it is high processor continues with the operation
• Otherwise, additional states (clock cycles) called T states are
inserted until the memory/peripheral becomes ready
26
WAIT states (read operation)
T1 T2 T3 TWAIT T4

CLK

ALE

M/IO

ADDR/Stat A19:A16 S6-S3


READY

ADDR/DATA A15:A0 D15:D0

RD

DT/R
2727

DEN
WAIT states (write operation)
T1 T2 T3 TWAIT T4

CLK

ALE

M/IO

ADDR/Stat A19:A16 S6-S3


READY

ADDR/DATA A15:A0 DATA (D15:D0)

WR

DT/R
28

DEN
Thank you
any questions

29

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