Sequential Circuits

‫ياداوري‬
‫آموزش تکنيک هاي طراحي و پياده سازي سيستم ‪‬‬
‫‪:‬هاي پيچيده‬

‫• سيستم‪:‬‬
‫‪ ‬داراي ورودي ها‪ ،‬خروجي ها و رفتار مشخصي‬
‫است‬
‫‪ −‬اين رفتار توسط فانکشن هايي تعيين مي شود که‬
‫ورودي ها را به خروجي ها تبديل (نگاشت) مي کند‪.‬‬
‫‪ −‬مثال‪ :‬گوشي تلفن‪:‬‬
‫‪ −‬ورودي ها‪ :‬کليدها‬
‫‪ −‬خروجي ها‪ :‬صفحة نمايش و سيگنال هاي ارسالي به مرکز تلفن‬
‫‪ −‬رفتار‪ :‬شماره گيري و ايجاد ارتباط‬
‫‪ −‬مثال‪ :‬خودرو‪:‬‬
‫‪ −‬ورودي ها‪ :‬پدال ها‪ ،‬سوييچ‪ ،‬فرمان‪... ،‬‬
‫‪ −‬خروجي ها‪ :‬فرمان پيچش و چرخش چرخ ها‪ ،‬فرمان ترمز‪... ،‬‬
‫‪ −‬رفتار‪.... :‬‬
‫‪ −‬مثال‪ :‬تلويزيون‪:‬‬ ‫‪2‬‬
 Sequential vs. Combinational
• Combinational Logic:
 Outputs depend only on current input
− TV channel selector (0-9)

inputs system outputs

• Sequential Logic:
 Outputs depend on
− current input and
− current state of the system (which depends on past input values)
 Need some type of memory to remember the current state

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 Sequential Logic
• Sequential Logic circuits
 Remembers past circuit state.
 Outputs from the system are “fed back” as new inputs.
 Storage elements:
− Circuits that are capable of storing binary information
− Memory

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 Feedback Loop
• Feedback:
 A signal s1 depends on another signal
whose value depends on s1
− (perhaps with several intermediate signals).

s1

R Q

Q’
S

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 Base of Memory
 Consider the following circuit:
P1 = P2 = 0

 It can differentiate between two different states

− because it has only one feedback line that can keep
one of two values, 0 or 1.

P1 either 0 or 1

P2

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 Base of Memory
 It can differentiate between two different states
− because it has only one feedback line that can keep
one of two values, 0 or 1.

 A circuit with n feedback lines has 2n potential

states
 Memory of our circuit depends on the number of
its feedback lines:

P1

P2

n
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 SR latch (NOR version)

S
R

S R Q
0 0 hold
0 1 0
1 0 1
1 1 Not allowed

R
Q

S Q’

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 SR latch (NOR version)

S
R

S R Q
0 0 hold
0 1 0 Truth Table:
Next State = F(S, R, Current State)
1 0 1
1 1 Not allowed S(t) R(t) Q(t) Q(t+)

0 0 0 0 (hold)
0 0 1 1 (Hold)
0 1 0 0 (reset)
R
Q 0 1 1 0 (reset)
1 0 0 1 (set)
1 0 1 1 (set)
1 1 0 Not allowed
S 1 1 1 Not allowed
Q’

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 SR Latch
Truth Table: Derived K-Map:
Next State = F(S, R, Current State) S
SR
S(t) R(t) Q(t) Q(t+) 00 01 11 10
Q( t )
0 0 0 0 (hold)
0 0 1 1 (Hold) 0 0 0 X 1
0 1 0 0 (reset)
0 1 1 0 (reset)
1 0 0 1 (set) 1 1 0 X 1
1 0 1 1 (set)
1 1 0 Not allowed
1 1 1 Not allowed R

Characteristic Equation:

Q+ = S + R Q t
S
R-S
R Latch Q+

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 R=S=1 ??

• Illegal output, because

When S=R=1, both outputs go to zero.
 If both inputs now go to 0, the state of the
SR latch depends on delays.
Hence, “undefined” state.
− MUST be avoided.

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 Timing Diagram

Reset Hold Set Reset Set 100 Race

R
S
Q
Q’

Forbidden Forbidden
State State

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Timing Diagram of SR Latch

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 SR Latch State Diagram
• Observed State Diagram
SR = 00, 01 SR = 00, 10
SR = 1 0
QQ QQ
01 10
SR = 0 1
SR = 0 1 SR = 1 0
SR = 11
SR = 1 1 SR = 1 1

QQ
00
SR = 0 0
SR = 0 0

 Difficulty in observing R-S Latch in the 1-1 state

 Ambiguously returns to state 0-1 or 1-0
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 S’R’ Latch (NAND version)

0 S’ S’ R’ Q Q’
Q 1
0 0
0 1 1 0 Set
1 0
Q’ 0
1 R’ 1 1

X Y NAND
S Q 0 0 1
R-S
Latch 0 1 1
R Q’ 1 0 1
1 1 0

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S’R’ Latch (NAND version)

1 S’ S’ R’ Q Q’
Q 1
0 0
0 1 1 0 Set
1 0
Q’ 0
1 R’ 1 1 1 0 Hold

X Y NAND
0 0 1
0 1 1
1 0 1
1 1 0

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S’R’ Latch (NAND version)

1 S’ S’ R’ Q Q’
Q 0
0 0
0 1 1 0 Set
1 0 0 1 Reset
Q’ 1
1 R’ 1 1 1 0 Hold
0 1 Hold
X Y NAND
0 0 1
0 1 1
1 0 1
1 1 0

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S’R’ Latch (NAND version)

1 S’ S’ R’ Q Q’
Q 0
0 0
0 1 1 0 Set
1 0 0 1 Reset
Q’ 1
0 R’ 1 1 1 0 Hold

X Y NAND
0 0 1
0 1 1
1 0 1
1 1 0

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S’R’ Latch (NAND version)

0 S’ S’ R’ Q Q’
Q 1
0 0 1 1 Disallowed
0 1 1 0 Set
1 0 0 1 Reset
Q’ 1
0 R’ 1 1 1 0 Hold
0 1 Hold
X Y NAND
0 0 1
0 1 1
1 0 1
1 1 0

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SR Latch with Control (Enable)
S S’
Q

Q’
R R’

S R C S’ R’ Q Q’
0 0 1 1 1 Q0 Q0’ Hold
0 1 1 1 0 0 1 Reset
1 0 1 0 1 1 0 Set
1 1 1 0 0 1 1 Disallowed
X X 0 1 1 Q0 Q0’ Hold
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 D Latch
S-R latches are useful in control applications,
− Set a flag in response to some condition
− Reset it when conditions change
We often need latches simply to store bits presented on a signal
line
 D latch
Can eliminate the undesirable indeterminate state in the RS latch:
− ensure that inputs S and R are never 1 simultaneously.

D Q
D
Latch
Q’
C

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 D Latch (cont.)
S
D S’
Q

Q’
R
R’

S R C Q Q’
D C Q Q’ 0 0 1 Q0 Q0’ Store
0 1 0 1 0 1 1 0 1 Reset
1 1 1 0 1 0 1 1 0 Set
X 0 Q0 Q0’ 1 1 1 1 1 Disallowed
X X 0 Q0 Q0’ Store
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D Latch Timing Diagram
D Q
D
Latch
Q’
C

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 D-Latch Circuit
D Q
D
Latch
Q’
C

C D Q Q+
CD
0 0 0 0
0 0 1 1
0 1 0 0
0 1 1 1
1 0 0 0
1 0 1 0
1 1 0 1
1 1 1 1 Q+ = C’.Q + C.D

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 JK Latch
J Q
J(t) K(t) Q(t) Q(t+)

0 0 0 0 (hold) K Q’
0 0 1 1 (hold)
0 1 0 0 (reset)
0 1 1 0 (reset)
1 0 0 1 (set) J-K Latch
1 0 1 1 (set)
1 1 0 1 (toggle)
1 1 1 0 (toggle) Derived K-Map:
J
JK
00 01 11 10
Q( t )
J, K both one yields toggle 0 0 0 1 1

1 1 0 0 1

Characteristic Equation:
Q+ = Q K’ + Q’ J

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 JK Latch Using SR Latch
How to eliminate the forbidden state in SR?

Idea: use output feedback to

guarantee that R and S are Q
never both one J S Q
R-S
J, K both one yields toggle latch
K R Q’ Q’

J(t) K(t) Q(t) Q(t+)

0 0 0 0 HOLD
0 0 1 1
0 1 0 0 RESET
0 1 1 0
Characteristic Equation:
1 0 0 1 SET
1 0 1 1 Q+ = Q K + Q J
1 1 0 1 TOGGLE
1 1 1 0

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 JK Latch Race Condition

Set Reset 100 Toggle

J
K
Q
\Q

Toggle Correctness: Single State changes

Solution: Master/Slave Flipflop

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 JK Latch Race Condition

Set Reset 100 Toggle

J
K
Q
\Q

Toggle Correctness: Single State changes

Solution: Master/Slave Flipflop

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 Flip-Flops
Latches are “transparent” (= any
change on the inputs is seen at the
outputs immediately).
This causes synchronization
problems!
Solution: use latches to create flip-
flops that can respond (update) ONLY
at SPECIFIC times (instead of ANY
time).

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 Alternatives in FF choice

• Types of FF
RS
D
JK
T

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 D-FF

D Q Q

0 0 0
0
1
1
0
0
1
Q  D
1 1 1

c Truth table
Timing for D Flip-Flop (Falling-Edge Trigger)

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Symbols

33
Compare 3 Types

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 Rising Edge D-FF

What About Falling-Edge Circuit?

35
 Setup & Hold Time and
Propagation Delay
• Setup time:
 D input must be stable for a certain amount of
time before the active edge of clock cycle

• Hold time:
 D input must be stable for a certain amount of
time after the active edge of the clock

• Propagation Delay (Clock-to-Output):

 from the time the clock changes to the time the
output changes

• Propagation Delay (Data-to-Output):

 from the time the data changes to the time the
output changes
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 Setup & Hold Time and
Propagation Delay

Setup and Hold Times for an Edge-Triggered D Flip-Flop

tpLH may be different from tpHL

tp clock-to-output vs. tp D-to-output
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Timing Parameters of a D-Latch

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 Edge-Triggered D Flip-Flop
Determination of Minimum Clock Period

Assume:
• tco= 5 ns
• tp,inv = 2 ns
• tsu= 3 ns

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 Edge-Triggered D Flip-Flop
Determination of Minimum Clock Period

Assume:
• tco= 5 ns
• tp,inv = 2 ns
• tsu= 3 ns
TCLK = 9

TCLK = 15 TCLK = ?
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 Master-Slave FF Configuration
Using SR Latches

– Enables edge-triggered behavior

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 Master-Slave FF configuration
using SR latches (cont.)
S R CLK Q Q’
• When C=1, master is enabled and
0 0 1 Q0 Q0’ Store stores new data, slave stores old
0 1 1 0 1 Reset data.
1 0 1 1 0 Set • When C=0, master’s state passes
1 1 1 1 1 Disallowed to enabled slave (Q=Y), master not
X X 0 Q0 Q0’ Store sensitive to new data (disabled).

Master Slave

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Master-Slave J-K Flip-Flop

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 Master-Slave J-K Flip-Flop
P

P’

Sample inputs while clock high Sample inputs while clock low

1's
Set Reset Catch Toggle 100

J
K
C Correct Toggle
P Master
Operation
P‘‘ outputs
Q
Slave
Q’ outputs

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 Edge-Triggered FF

D
D
Holds D when
clock goes low Negative Edge-Triggered
0 D flipflop
R
Q
4-5 gate delays
Clk=1
setup, hold times
necessary to successfully
Q
latch the input
S

0
Holds D when
clock goes low

D
D

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 T Flip-Flop

T Flip-Flop
T Q Q

0 0 0
0
1
1
0
1
1
Q  T Q  TQ T  Q
1 1 0

b 
Timing Diagram for T Flip-Flop (Falling-Edge Trigger)

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 Implementation of T-FF
Implementation of T Flip-Flop

Q   JQ  K Q TQ  T Q
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 FFs with Additional Inputs

D Flip-Flop with Clock Enable

The characteristic equation : Q  Q CE   D CE

The MUX output : Q  D Q CE   Din CE

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 Asynchronous Preset/Clear
 Many times it is desirable to asynchronously
(i.e., independent of the clock) set or reset
S
FFs. D Q

 Example: At power-up, we can start from a

known state. C Q’
R

 Asynchronous set == direct set == Preset

 Asynchronous reset == direct reset == Clear

 There may be “synchronous” preset and clear.

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 Asynchronous Set/Reset
Cn indicates that Cn controls all other inputs
whose label starts with n.
S
In this case, C1 controls 1J and 1K.
1J
Function Table
C1
S R C1 1J 1K Q(t+1)
1K 0 1 X X X 1 – Preset
R 1 0 X X X 0 – Clear
0 0 X X X Undefined
IEEE standard
graphical 1 1  0 0 Q(t) – Hold
symbol for JK- 1 1  0 1 0 – Reset
FF with direct
set & reset 1 1  1 0 1 – Set
1 1  1 1 Q(t)’ -- Complement

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 Asynchronous Inputs
 Asynchronous Clear
 Asynchronous Preset

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Synchronous Reset

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