18 Seq Design2-C
18 Seq Design2-C
State Optimization
• Equivalent States:
Two states are equivalent if, for
each member of the set of inputs,
they give exactly the same output and
send the circuit either to the same
state or to an equivalent state.
If two states are equivalent, one can
be eliminated without effecting the
behavior of the FSM.
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State Optimization Algorithm:
Row Matching
Two states are equivalent if for all input values,
any of the conditions are true:
1. If two states have the same output AND both
transition are to the same next state,
2. If two states have the same output AND both
transition are to each other
3. If two states have the same output AND both self-
loop.
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Row Matching Example
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Row Matching Example
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Row Matching Example (cont)
NS output
PS x=0 x=1 x=0 x=1
a a b 0 0
b c d 0 0
c a d 0 0
d e f 0 1
e a f 0 1
f e f 0 1
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Row Matching Example (cont)
NS output
PS x=0 x=1 x=0 x=1
Reduced State Transition Diagram
a a b 0 0
b c d 0 0
c a d 0 0
d e f 0 1
e a f 0 1
f e f 0 1
NS output
PS x=0 x=1 x=0 x=1
a a b 0 0
b c d 0 0
c a d 0 0
d e d 0 1
e a d 0 1
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State Optimization Algorithm
a b iff d f and c h
Implication Chart
b c because the outputs differ
Prese Next State Present Output
nt
State X=0 1 X=0
a d c 0
b f h 0
c e d 1
d a e 0
e c a 1
f f b 1
g b h 0
h c g 1
a d iff a d and c e
a g iff b d and c h
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State Optimization Algorithm
• Implication Chart After First Pass
Processing order is important
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State Optimization Algorithm
• Implication Chart After Second Pass
a a c 0
b f h 0
c c a 1
f f b 1
g b h 0
h c g 1
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Equivalent Sequential Circuits
• Definition:
Sequential circuit N1 is equivalent
to sequential circuit N2 if
for each state p in N1, there is a state
q in N2 such that p ≡ q , and
conversely, for each state s in N2 ,
there is a state t in N1 such that s ≡ t.
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Example
N1 N2
X=0 X=1 X=0 X=1 X=0 X=1 X=0 X=1
A B A 0 0 S0 S3 S1 0 1
B C D 0 1 S1 S3 S0 0 0
C A C 0 1 S2 S0 S2 0 0
D C B 0 0 S3 S2 S3 0 1
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X=0 X=1 X=0 X=1 X=0 X=1 X=0 X=1
A B A 0 0 S0 S3 S1 0 1
B C D 0 1 S1 S3 S0 0 0
C A C 0 1 S2 S0 S2 0 0
D C B 0 0 S3 S2 S3 0 1
• Implication Tables:
S0
S1
S2
S3
D C B A
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X=0 X=1 X=0 X=1 X=0 X=1 X=0 X=1
A B A 0 0 S0 S3 S1 0 1
B C D 0 1 S1 S3 S0 0 0
C A C 0 1 S2 S0 S2 0 0
D C B 0 0 S3 S2 S3 0 1
• Implication Tables:
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X=0 X=1 X=0 X=1 X=0 X=1 X=0 X=1
A B A 0 0 S0 S3 S1 0 1
B C D 0 1 S1 S3 S0 0 0
C A C 0 1 S2 S0 S2 0 0
D C B 0 0 S3 S2 S3 0 1
• Implication Tables:
A S 2 B S 0 C S 3 D S1
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State Encoding
The simplest assignment of s coded states to 2n
possible states is to use the first s binary
integers in binary counting order.
000, 001, 010, 011, 100
However, the simplest state assignment does
not always lead to the simplest circuit.
In fact, the state assignment often has a major effect
on circuit cost (was previously shown).
In general, the only formal way to find the best
assignment is to try all the assignments.
That’s too much work!!
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Example
Design a clocked synchronous
state machine with two inputs, A
and B, and a single output Z that is
1 if:
– A had the same value at each of the
two previous clock ticks, or
– B has been 1 since the last time that
the first condition was true.
– Otherwise, the output should be 0.
A Z
B
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Timing Diagram
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Moore Machine OKA0: still OK (because from an OK
A0: got 0 on A
state, got B=1), and got a 0 on A
A1: got 1 on A Reset/0
OKA1: still OK (because from an OK
OK00: got 00 on A init state, got B=1), and got a 1 on A
00
OK11: got 11 on A 10
01
11
00
01
10 A0 00
A1
11 01
10
10 11 00
10 00
11 01
00 10
OK11 OK00
01 11
10
00 11
01 11 OKA1
OKA0
01
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State Table
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Moore Machine OKA0: still OK (because from an OK
A0: got 0 on A
state, got B=1), and got a 0 on A
A1: got 1 on A Reset/0
OKA1: still OK (because from an OK
OK00: got 00 on A init state, got B=1), and got a 1 on A
00
OK11: got 11 on A 10
01
11
00/01
10 A0 00
A1
11 01
10
11
10 00
11 01
00 10
OK1 11 OK0
11
01
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State Encoding
• Guidelines:
Choose an initial coded state into which
the machine can easily be forced at reset
00. . . 00 or 11. . . 11 in typical circuits.
Minimize the number of state variables
that change on each transition.
Maximize the number of state variables
that don’t change in a group of related
states
i.e., a group of states in which most of
transitions stay in the group.
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State Encoding
• Samples:
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Synthesis Using D FF
Present State Next State Output
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State Assignment
• Unused States:
Each of the m states must be assigned a
unique code
Minimum number of bits required is n
such that
n ≥ log2 m
where x is the smallest integer ≥ x
There are 2n - m unused states
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State Assignment
• Unused States:
Minimal risk:
Assumes: FSM may get into unused (or “illegal”) states,
Due to a hardware failure, an unexpected input
Unused states go to the “initial” state (or a legal state)
Minimal cost:
Assumes: FSM never enters an unused state
Next-state entries of the unused states can be marked as
“don’t-cares”.
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Present
State Next State
Reset/0
init 00
10 01
11
00/01
10 A0 00
A1
11 01
10
11
10 00
11 00 01
10
OK1 11 OK0
11
01
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Case 1: Minimal Risk
• Assumption:
Unused states go to 000 (minimal risk)
D1 = Q1 + Q2¢.Q3¢
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Case 1: D2 Equation
D3 = Q1.A + Q2¢.Q3¢.A
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Case 1: Z Equation
Z = Q1.Q2.Q3¢ + Q1.Q2.Q3
= Q1.Q2
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Case 2: Minimal Cost
• Assumption:
next states of unused states are “don’t-cares” (minimal cost).
Z = don’t care for unused states.
D1 = 1
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Case 2: D2 Equation
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Case 2: D3 Equation
D3 = A
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Case 2: Z Equation
Z = Q2
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Case 2: Logic Diagram
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Third Solution
• Trade-off:
Use minimal cost.
Then check to see if there is
serious problem.
Incrementally modify.
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