CSIE30300 Computer Architecture

Unit 12: Bus and I/O Systems

Hsin-Chou Chi

[Adapted from material by Patterson@UCB and Irwin@PSU]

Review: Major Components of a Computer

Processor Devices

Control Memory Output

Datapath Input

 Important metrics for an I/O system

 Performance
 Expandability
 Dependability
 Cost, size, weight
Input and Output Devices
 I/O devices are incredibly diverse with respect to
 Behavior – input, output or storage
 Partner – human or machine
 Data rate – the peak rate at which data can be transferred
between the I/O device and the main memory or processor

Device Behavior Partner Data rate (Mb/s)

Keyboard input human 0.0001

8 orders of magnitude
Mouse input human 0.0038
Laser printer output human 3.2000

range
Graphics display output human 800.0000-8000.0000
Network/LAN input or machine 100.0000-1000.0000
output
Magnetic disk storage machine 240.0000-2560.0000
I/O Performance Measures
 I/O bandwidth (throughput) – amount of information
that can be input (output) and communicated across
an interconnect (e.g., a bus) to the processor/memory
(I/O device) per unit time
1. How much data can we move through the system in a
certain time?
2. How many I/O operations can we do per unit time?

 I/O response time (latency) – the total elapsed time to

accomplish an input or output operation
 An especially important performance metric in real-time
systems

 Many applications require both high throughput and

short response times
A Typical I/O System

Interrupts
Processor

Cache

Memory - I/O Bus

Main I/O I/O I/O

Memory Controller Controller Controller

Graphics Network
Disk Disk
I/O System Interconnect Issues
 A bus is a shared communication link (a single set of
wires used to connect multiple subsystems) that needs
to support a range of devices with widely varying
latencies and data transfer rates
 Advantages
- Versatile – new devices can be added easily and can be moved
between computer systems that use the same bus standard
- Low cost – a single set of wires is shared in multiple ways
 Disadvantages
- Creates a communication bottleneck – bus bandwidth limits the
maximum I/O throughput
 The maximum bus speed is largely limited by
 The length of the bus
 The number of devices on the bus
Bus Characteristics
Control lines: Master initiates requests
Bus Data lines: Data can go either way Bus
Master Slave

 Control lines
 Signal requests and acknowledgments
 Indicate what type of information is on the data lines
 Data lines
 Data, addresses, and complex commands
 Bus transaction consists of
 Master issuing the command (and address) – request
 Slave receiving (or sending) the data – action
 Defined by what the transaction does to memory
- Input – inputs data from the I/O device to the memory
- Output – outputs data from the memory to the I/O device
Types of
Buses
 Processor-memory bus (proprietary)
 Short and high speed
 Matched to the memory system to maximize the memory-
processor bandwidth
 Optimized for cache block transfers

 I/O bus (industry standard, e.g., SCSI, USB, Firewire)

 Usually is lengthy and slower
 Needs to accommodate a wide range of I/O devices
 Connects to the processor-memory bus or backplane bus

 Backplane bus (industry standard, e.g., ATA, PCIexpress)

 The backplane is an interconnection structure within the chassis
 Used as an intermediary bus connecting I/O busses to the
processor-memory bus
A Computer System with One Bus: Backplane Bus

Backplane Bus
Processor Memory

I/O Devices

 A single bus (the backplane bus) is used for:

 Processor to memory communication
 Communication between I/O devices and memory
 Advantages: Simple and low cost
 Disadvantages: slow and the bus can become a major
bottleneck
 Example: IBM PC - AT
 A Two-Bus System

Processor Memory Bus

Processor Memory

Bus Bus Bus

Adaptor Adaptor Adaptor

I/O I/O I/O

Bus Bus Bus

 I/O buses tap into the processor-memory bus via bus

adaptors:
 Processor-memory bus: mainly for processor-memory traffic
 I/O buses: provide expansion slots for I/O devices
 Apple Macintosh-II
 NuBus: Processor, memory, and a few selected I/O devices
 SCCI Bus: the rest of the I/O devices
A Three-Bus System

Processor Memory Bus

Processor Memory

Bus
Adaptor
Bus
Adaptor I/O Bus
Backplane Bus
Bus I/O Bus
Adaptor

 A small number of backplane buses tap into the

processor-memory bus
 Processor-memory bus is used for processor memory traffic
 I/O buses are connected to the backplane bus
 Advantage: loading on the processor bus is greatly
reduced
Synchronous and Asynchronous
Buses
 Synchronous bus (e.g., processor-memory buses)
 Includes a clock in the control lines and has a fixed protocol for
communication that is relative to the clock
 Advantage: involves very little logic and can run very fast
 Disadvantages:
- Every device communicating on the bus must use same clock rate
- To avoid clock skew, they cannot be long if they are fast
 Asynchronous bus (e.g., I/O buses)
 It is not clocked, so requires a handshaking protocol and
additional control lines (ReadReq, Ack, DataRdy)
 Advantages:
- Can accommodate a wide range of devices and device speeds
- Can be lengthened without worrying about clock skew or
synchronization problems
 Disadvantage: slow(er)
Asynchronous Bus Handshaking Protocol
 Output (read) data from memory to an I/O device

ReadReq 1
2
Data addr data
3
Ack 4 6
5 7
DataRdy

I/O device signals a request by raising ReadReq and putting the addr on
the data lines

1. Memory sees ReadReq, reads addr from data lines, and raises Ack
2. I/O device sees Ack and releases the ReadReq and data lines
3. Memory sees ReadReq go low and drops Ack
4. When memory has data ready, it places it on data lines and raises DataRdy
5. I/O device sees DataRdy, reads the data from data lines, and raises Ack
6. Memory sees Ack, releases the data lines, and drops DataRdy
7. I/O device sees DataRdy go low and drops Ack
The Need for Bus Arbitration
 Multiple devices may need to use the bus at the same
time so must have a way to arbitrate multiple requests
 Bus arbitration schemes usually try to balance:
 Bus priority – the highest priority device should be serviced first
 Fairness – even the lowest priority device should never be
completely locked out from the bus
 Bus arbitration schemes can be divided into four classes
 Daisy chain arbitration – see next slide
 Centralized, parallel arbitration – see next-next slide
 Distributed arbitration by self-selection – each device wanting the
bus places a code indicating its identity on the bus
 Distributed arbitration by collision detection – device uses the
bus when its not busy and if a collision happens (because some
other device also decides to use the bus) then the device tries
again later (Ethernet)
Daisy Chain Bus
Arbitration
Device 1 Device 2 Device N
Highest Lowest
Priority Priority

Ack Ack Ack

Bus Release
Arbiter Request

wired-OR
Data/Addr

 Advantage: simple
 Disadvantages:
 Cannot assure fairness – a low-priority device may be locked out
indefinitely
 Slower – the daisy chain grant signal limits the bus speed
Centralized Parallel
Arbitration
Device 1 Device 2 Device N

Request1 Request2 RequestN

Ack1
Bus Ack2
Arbiter
AckN

Data/Addr

 Advantages: flexible, can assure fairness

 Disadvantages: more complicated arbiter hardware
 Used in essentially all processor-memory buses and in
high-speed I/O buses
Communication of I/O Devices and Processor
 How the processor directs the I/O devices
 Special I/O instructions
- Must specify both the device and the command
 Memory-mapped I/O
- Portions of the high-order memory address space are assigned to
each I/O device
- Read and writes to those memory addresses are interpreted
as commands to the I/O devices
- Load/stores to the I/O address space can only be done by the OS
 How the I/O device communicates with the processor
 Polling – the processor periodically checks the status of an I/O
device to determine its need for service
- Processor is totally in control – but does all the work
- Can waste a lot of processor time due to speed differences
 Interrupt-driven I/O – the I/O device issues an interrupts to the
processor to indicate that it needs attention
Interrupt-Driven I/O
 An I/O interrupt is asynchronous wrt instruction execution
 Is not associated with any instruction so doesn’t prevent any
instruction from completing
- You can pick your own convenient point to handle the interrupt
 With I/O interrupts
 Need a way to identify the device generating the interrupt
 Can have different urgencies (so may need to be prioritized)
 Advantages of using interrupts
 Relieves the processor from having to continuously poll for an I/O
event; user program progress is only suspended during the actual
transfer of I/O data to/from user memory space
 Disadvantage – special hardware is needed to
 Cause an interrupt (I/O device) and detect an interrupt and save
the necessary information to resume normal processing after
servicing the interrupt (processor)
Direct Memory Access (DMA)
 For high-bandwidth devices (like disks) interrupt-driven
I/O would consume a lot of processor cycles
 DMA – the I/O controller has the ability to transfer data
directly to/from the memory without involving the
processor
1. The processor initiates the DMA transfer by supplying the I/O
device address, the operation to be performed, the memory
address destination/source, the number of bytes to transfer
2. The I/O DMA controller manages the entire transfer (possibly
thousand of bytes in length), arbitrating for the bus
3. When the DMA transfer is complete, the I/O controller
interrupts the processor to let it know that the transfer is
complete
 There may be multiple DMA devices in one system
 Processor and I/O controllers contend for bus cycles and for
memory
I/O and the Operating System
 The operating system acts as the interface between the
I/O hardware and the program requesting I/O
 To protect the shared I/O resources, the user program is not
allowed to communicate directly with the I/O device

 Thus OS must be able to give commands to I/O devices,

handle interrupts generated by I/O devices, provide
equitable access to the shared I/O resources, and
schedule I/O requests to enhance system throughput
 I/O interrupts result in a transfer of processor control to the
supervisor (OS) process