University Institute of Engineering

Department of Computer Science & Engineering

COMPUTER ORGANIZATION & ARCHITECTURE

ER. SHIKHA ATWAL

ASSISTANT PROFESSOR

BE-CSE
 MAIN MEMORY

The main memory acts as the central storage unit in a computer system. It is a
relatively large and fast memory which is used to store programs and data
during the run time operations.
The primary technology used for the main memory is based on
semiconductor integrated circuits.
The integrated circuits for the main memory are classified into two major
units.
1.RAM (Random Access Memory) integrated circuit chips
2.ROM (Read Only Memory) integrated circuit chips
1. RAM integrated circuit chips
The RAM integrated circuit chips are further classified into two
possible operating modes, static and dynamic.
The primary compositions of a static RAM are flip-flops that store
the binary information. The nature of the stored information is volatile, i.e.
it remains valid as long as power is applied to the system. The static RAM
is easy to use and takes less time performing read and write operations as
compared to dynamic RAM.
The dynamic RAM exhibits the binary information in the form of electric
charges that are applied to capacitors. The capacitors are integrated
inside the chip by MOS transistors. The dynamic RAM consumes
less power and provides large storage capacity in a single memory chip.
RAM chips are available in a variety of sizes and are used as per
the system requirements.
The following block diagram demonstrates the chip interconnection in a 128 * 8
RAM chip.

o A 128 * 8 RAM chip has a memory capacity of 128 words of eight bits (one
byte) per word. This requires a 7-bit address and an 8-bit bidirectional data bus.
o The 8-bit bidirectional data bus allows the transfer of data either from memory
to CPU during a read operation or from CPU to memory during a write
operation.
oThe read and write inputs specify the memory operation, and the two chip
select (CS) control inputs are for enabling the chip only when the
microprocessor selects it.
oThe bidirectional data bus is constructed using three-state buffers.
oThe output generated by three-state buffers can be placed in one of the
three possible states which include a signal equivalent to logic 1, a signal equal
to logic 0, or a high-impedance state.

Note: The logic 1 and 0 are standard digital signals whereas the high-impedance
state behaves like an open circuit, which means that the output does not carry a
signal and has no logic significance.
The following function table specifies the operations of a 128 * 8 RAM chip.

From the functional table above, we can conclude that the unit is in operation
only when CS1 = 1 and CS2 = 0. The bar on top of the second select variable
indicates that this input is enabled when it is equal to 0.
2. ROM integrated circuit
The primary component of the main memory is RAM integrated circuit chips,
but a portion of memory may be constructed with ROM chips.
A ROM memory is used for keeping programs and data that are permanently
resident in the computer.
Apart from the permanent storage of data, the ROM portion of main memory is
needed for storing an initial program called a bootstrap loader. The
primary function of the bootstrap loader program is to start the computer
software operating when power is turned on.
ROM chips are also available in a variety of sizes and are also used as per the
system requirement. The following block diagram demonstrates the chip
interconnection in a 512 * 8 ROM chip.
o A ROM chip has a similar organization as a RAM chip. However, a ROM can
only perform read operation; the data bus can only operate in an output mode.
o The nine address lines in the ROM chip specify any one of the 512 bytes
stored in it.
o The two chip select inputs must be CS1=1 and CS2=0 for the unit to
operate. Otherwise, the data bus is said to be in a high-impedance state.
Memory Address Map
The system designer must calculate the amount of memory required for a given
application and assign it to RAM or ROM.
The interconnection between the processor and the memory is established from
the knowledge of the size of memory required and the type of ROM
and RAM chips available. The addressing of memory can be established by
means of a table that specify the memory address assigned to each chip. The
table is called the Memory address map, is a pictorial representation of
assigned address space for each chip in the system.
Component Hexadecima Address Bus
l Address 10 9 8 7 6 5 4 3 2 1

RAM 1 0000-007F 0 0 0 X X X X X X X
RAM 1 0080-007F 0 0 1 X X X X X X X
RAM 1 0100-017F 0 1 0 X X X X X X X
RAM 1 0180-01FF 0 1 1 X X X X X X X
ROM 0200-03FF 1 X X X X X X X X X
The memory address map for the configuration of 512 bytes RAM and 512 bytes
ROM is shown in table above. The component column specifies whether a RAM
or a ROM chip is used. The hexadecimal address column assigns a range of
hexadecimal equivalent addresses for each chip. The address bus lines are listed in
the third column. The RAM chips have 128 bytes and need seven address lines.
The ROM chip has 512 bytes and needs 9 address lines.
Memory Connection to CPU

 The data and address buses are

Memory
Connection to
the CPU
The connection of memory chips to the CPU is shown in the figure above. This
configuration gives a memory capacity of 512 bytes of RAM and 512 bytes of
ROM. Each RAM receives the seven low-order bits of the address bus to select
one of 128 possible bytes.
The particular RAM chip selected is determined from lines 8 and 9 in the
address bus. This is done through a 2 X 4 decoder whose outputs go to the CS1
inputs in each RAM chip.
Thus, when address lines 8 and 9 are equal to 00, the first RAM chip is selected.
When 01, the second RAM chip is select, and so on.
The RD and WR outputs from the microprocessor are applied to the inputs of
each RAM chip. The selection between RAM and ROM is achieved through bus
line 10. The RAMs are selected when the bit in this line is 0, and the ROM when
the bit is 1.
Address bus lines 1 to 9 are applied to the input address of ROM without going
through the decoder. The data bus of the ROM has only an output
capability, whereas the data bus connected to the RAMs can transfer
information in both directions.
References

Reference Books:
●J.P. Hayes, “Computer Architecture and
Organization”, Third Edition.
●Mano, M., “Computer System Architecture”, Third
Edition, Prentice Hall.
●Stallings, W., “Computer Organization and Architecture”, Eighth
Edition, Pearson Education.

Text Books:
●Carpinelli J.D,” Computer systems organization &Architecture”, Fourth
Edition, Addison Wesley.
●Patterson and Hennessy, “Computer Architecture”, Fifth Edition Morgaon
Kauffman.
Reference Website:
●Memory Hierarchy Design and its Characteristics - GeeksforGeeks
●What is memory hierarchy? (tutorialspoint.com)

Video Links:
 https://youtu.be/oj4_c9IMOCg?si=1FMiriyxX7JwkE4h
 https://youtu.be/zwovvWfkuSg?si=fKl4vq0THSpiMa0M
 https://www.youtube.com/watch?v=LE_lyLCqy8I&list=PL3R9-
um41JszyaKeoc9qP8Bn45XzqJycj
 https://www.youtube.com/watch?v=_ImgTuITW-s&list=PL3R9-
um41JszyaKeoc9qP8Bn45XzqJycj&index=4