COSE321 Computer Systems Design

Lecture 1. ARM Intro.

Prof. Taeweon Suh

Computer Science &
Engineering
Korea University
www.arm.com (as of 2018)

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 ARM Brief
• ARM architecture was first developed in the 1980s by Acorn

• Spin off from Acorn in 1990

• As of 2013, Arm architecture is the most widely used 32-bit ISA in terms of
quantity produced

• 64-bit architecture (Armv8) was announced in Oct. 2011.

• Armv9 (64-bit architecture) was announced in March 2021

 Machine learning, Enhanced security, and Improved vector and DSP capabilities
(DSP: Digital Signal
Processing)

• In 2010 alone, 6.1 billion Arm-based processors shipped, representing

 95% of smartphones, 35% of digital TV and set-top boxes, 10% of mobile computers

• Softbank, a Japanese company, surprised the technology world with the arm
acquisition in 2016 at $31.4 billion
Source: Wikipedia
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https://www.anandtech.com/show/16584/arm-announces-armv9-architecture Korea Univ
Vision (as of 2018)

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 ARM Partners

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Source: 2008 Embedded SW Insight Conference
Korea Univ
 ARM (as of 2008)

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Source: 2008 Embedded SW Insight Conference
Korea Univ
 ARM Processor Portfolio
Galaxy S2, S3
(2011, 2012)

Galaxy S
iPhone 4
(2010)

~1990s ~2000s
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Source: 2008 Embedded SW Insight Conference
Korea Univ
 Product Code

• T: Thumb
• T2: Thumb-2 Enhancement
• D: Debug
• M: Multiplier
• I: Embedded ICE (In-Circuit Emulation)
• E: Enhanced DSP Extension
• J: Jazelle
 Direct execution of 8-bit Java bytecode in
hardware
• S: Synthesizable core
• Z: Should be TrustZone?
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 ARMv5, v6, v7, v8

• VFP: Vector Floating Point

• SIMD: Single Instruction Multiple Data
• Jazelle: Native execution of Java Bytecode
• TrustZone: ARM’s security architecture

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www.arm.com Korea Univ
 ARM Cortex Series

• ARM Cortex-A family:

 Applications processors for feature- x1-4
Cortex-A15
...2.5GHz
rich OS and 3rd party applications x1-4
Cortex-A9

Unparalleled Applicability
Cortex-A8
• ARM Cortex-R family: x1-4
Cortex-A5
 Embedded processors for Real-time
1-2

Cortex-R7
1-2
signal processing, control Cortex-R5
applications Cortex-R4
Cortex-M4
SC300
• ARM Cortex-M family: Cortex-M3
 Microcontroller-oriented processors Cortex-M1
SC000
for MCU, ASSP, and SoC applications
MCU: Microcontroller Unit Cortex-M0
ASSP: Application Specific Standard Product 12k gates...
SoC: System-on-chip

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Source: ARM Processor Portfolio 2011
Korea Univ
 Cortex-A Portfolio

Galaxy S6 Edge
Galaxy S4, S5
(2015)
(2013, 2014)

32-bit architecture 64-bit architecture

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https://www.arm.com/files/pdf/ARM-Cortex-Portfolio-2114.pdf
Korea Univ
 Cortex-R & Cortex-M Portfolio

32-bit
architecture

2011 2016

32-bit
architecture

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https://www.arm.com/files/pdf/ARM-Cortex-Portfolio-2114.pdf
Wikipedia
Korea Univ
 ARMv8-A & ARMv7-A

ARMv8 ARMv7

 ACP: Accelerator Coherency Port  SCU: Snoop Control Unit

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www.arm.com Korea Univ
 ARM Processor Selector

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www.arm.com Korea Univ
 ARM Processor Brief

#pipeline stages Frequency Architecture Process

ARM6 (1992) 3 ~33MHz ARMv3 1.2μm

ARM7TDMI 3 ~70MHz ARMv4 0.13μm

ARM920T 5 ~400MHz ARMv4 90nm

ARM1136J 8 ~1Ghz ARMv6 65nm

Cortex-A9 8~11 (OoO) ~2GHz ARMv7 32nm

Cortex-A15 15~24 (OoO) ~2.5GHz ARMv7 22nm

 OOO: Out Of Order

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 Abstraction

• Abstraction helps us deal with complexity

 Hide lower-level detail
• Instruction set architecture (ISA)
 An abstract interface between the hardware
and the low-level software interface

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 Abstraction in Computer

Users Application programming using

APIs

Abstractio Operating Systems

n layer

Abstractio Instruction Set Architecture Machine

n layer (ISA) language
Assembly
language

Core0 Core1
Hardware
implementatio
n

L2 Cache

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 A Memory Hierarchy

DDR3 HDD

2nd Gen. Core i7

(2011)

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 A Memory Hierarchy

higher level lower level

On-Chip Components
Secondary
CPU Core Storage
L1I Main
(Instr )
Re L3 Memory (Disk)
g L2 (DRAM)
L1D
Fil (Data)
e

peed (cycles): ½’s 1’s 10’s 100’s 10,000’s

ize (bytes): 100’s 10K’s M’s G’s T’s

Cost: highest
lowest

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 Typical and Essential
Instructions
• CPU provides many instructions
 It would be time-consuming to study all the
instructions CPU provides
 There are essential and common instructions

• Instruction categories
 Data processing instructions
• Arithmetic and Logical (Integer)
 Memory access instructions
• Load and Store
 Branch instructions
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 High-level Code to Binary (x86)
%gcc –g simple_sub.c -o simple_sub Instructions
%objdump –SD -Mintel simple_sub
int mysub(int op1, int op2) { (human-
readable)
#include <stdio.h> 8048429: 55 push ebp
addres 804842a: 89 e5 mov ebp,esp
s 804842c: 83 ec 10 sub esp,0x10
#define A 3
int myres;
#define B 5
myres = op1 - op2;
int main() {
printf("%d - %d = %d", C Compiler 804842f: 8b 45 0c mov eax,DWORD PTR
[ebp+0xc]
A, B, mysub(A, B));
8048432: 8b 55 08 mov edx,DWORD PTR
return 0; [ebp+0x8]
} 8048435: 89 d1 mov ecx,edx
8048437: 29 c1 sub ecx,eax
int mysub(int op1, int 8048439: 89 c8 mov eax,ecx
op2) { 804843b: 89 45 fc mov DWORD PTR [ebp-
0x4],eax
int myres;
myres = op1 - op2; return myres;
return myres; Representation in 804843e: 8b 45 fc mov eax,DWORD PTR [ebp-
} hexadecimal 0x4]
simple_sub (machine-readable)
}
.c
218048441: c9 leave
8048442: c3 ret
Korea Univ
Levels of Program Code (ARM)
• High-level language program (in C)

swap (int v[], int k)

{ int temp;
temp = v[k];
v[k] = v[k+1];
v[k+1] = temp;
}
C Compiler

• Assembly language program

swap: sll R2, R5, #2

add R2, R4, R2
ldr R12, 0(R2)
ldr R10, 4(R2)
str R10, 0(R2)
str R12, 4(R2)
b exit
Assembler
• Machine (object, binary) code

000000 00000 00101 0001000010000000

000000 00100 00010 0001000000100000
. . .
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 CISC vs RISC

• CISC (Complex Instruction Set Computer)

 One instruction does many (complex) jobs
• Example: movs in x86
 Variable length instruction
 Examples: x86 (Intel, AMD), Motorola 68k

• RISC (Reduced Instruction Set Computer)

 Each instruction does a small (unit) job
• Example: add, lw, sw, beq in RISC-V
 Fixed-length instruction
 Load/Store Architecture
 Examples: RISC-V, Arm, MIPS
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 ARM Architecture

• ARM is RISC (Reduced Instruction Set Computer)

 x86 ISA is based on CISC (Complex Instruction Set
Computer) even though x86 internally implements
RISC-like microcode and pipelining

• Suitable for embedded systems (Cortex-M)

 Very small die size (low price)
 Low power consumption (longer battery life)

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 ARM Registers

At reset, ARM goes to the “Supervisor” mode

(see a backup slide, “exception vector”, p35)

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Source: ARMv7 Architecture Reference Manual Korea Univ
 ARM Registers

• Unbanked registers: R0 ~ R7
 Each of them refers to the same 32-bit
physical register in all processor modes.
 They are completely general-purpose
registers, with no special uses implied
by the architecture

• Banked registers: R8 ~ R14

 R8 ~ R12 have no dedicated special
purposes
• FIQ mode has dedicated registers for fast
interrupt processing
 R13 and R14 are dedicated for special
purposes for each mode

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 R13, R14, and R15
• Some registers in ARM are used for special
purposes
 R15 == PC (Program Counter)
• x86 uses a terminology called IP (Instruction Pointer)
 R14 == LR (Link Register)
 R13 == SP (Stack Pointer)

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 CPSR

• Current Program Status Register (CPSR) is accessible in all modes

• Contains all condition flags, interrupt disable bits, the current
processor mode

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CPSR in ARM

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CPSR bits

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 CPSR bits

• ARM: 32-bit instructions

• Thumb, Thumb2: 16-bit or 32-bit instructions
• Jazelle: Special mode for JAVA acceleration
• ThumbEE (Thumb Execution Environment)
 First appeared in 2005 (in Cortex-A8)
 4th instruction set state, making small changes to Thumb2
 ARM deprecates any use of ThumbEE ISA and ARMv8 removes
support for ThumbEE
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 APSR (Application Program Status
Register)

http://esca.korea.ac.kr/teaching/cose321_CSD/labs/DDI0406C_C_armv7AR_architecture_reference_manual.pdf
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 Interrupt

• Interrupt is an asynchronous signal from hardware indicating

the need for attention or a synchronous event in software
indicating the need for a change in execution.
 Hardware interrupt causes the processor (CPU) to save its state of
execution via a context switch, and begins execution of an interrupt
handler.
 Software interrupt is usually implemented as an instruction in the
instruction set, which causes a context switch to an interrupt handler
similar to a hardware interrupt.

• Interrupt is a commonly used technique in computer system for

communication between CPU and peripheral devices

• Operating systems also extensively use interrupt (timer

interrupt) for task (process, thread) scheduling
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 Hardware Interrupt in ARM
• IRQ (Normal interrupt request)
 Informed to CPU by asserting IRQ pin
 PC is changed to (vector base + 0x18)
 ARM goes to IRQ mode

• FIQ (Fast interrupt request)

 Informed to CPU by asserting FIQ pin
 Has a higher priority than IRQ
 PC is changed to (vector base + 0x1C)
 ARM goes to FIQ mode
IRQ
FIQ

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 Supervisor Call in ARM

• Supervisor Call (previously, Software Interrupt)

 SVC instruction (previously, SWI instruction)
 PC is changed to (vector base + 0x08)
 ARM goes to Supervisor mode
• Supervisor call is commonly used by OS for system calls
 Modern OSs have hundreds of system calls (Linux has over 300 system calls)
 Examples: open(), close(), read(), write(), exit().. etc

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https://en.wikipedia.org/wiki/System_call
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 Exception Vectors in ARM

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RAZ: Read As Zero Korea Univ
Backup Slides

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ARM (www.arm.com)

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 ARM

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Source: 2008 Embedded SW Insight Conference
Korea Univ
ARM Processor Portfolio (Cont.)

Galaxy S6 Edge
Galaxy S4, S5 (2015)
(2013, 2014)

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 Exception Vectors in ARM

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RAZ: Read As Zero Korea Univ
 ARM Registers
• ARM has 31 general purpose registers and 6 status
registers (32-bit each)

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 Levels of Program Code (x86)

Code with
High-level Machine Code
Language a = 3;
c7 45 f0 03 00 00 00 movl $0x3,-0x10(%ebp)
int main()
b = 9;
{
c7 45 f4 09 00 00 00 movl $0x9,-0xc(%ebp)
int a, b, c; C Compiler
a = 3;
c = a + b;
b = 9;
8b 55 f4 mov -0xc(%ebp),%edx
c = a + b;
8b 45 f0 mov -0x10(%ebp),%eax
return c;
01 d0 add %edx,%eax
}
89 45 f8 mov %eax,-0x8(%ebp)

Representation in Instructions
hexadecimal (human-
(machine- readable)
readable)

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