CS220 Computer Architecture

Digital Logic Design

Recap
Understand how positive and negative integers may be encoded in binary.

Understand how to convert from decimal to binary and to hexadecimal

number formats.

Learn the definitions of the four main arithmetic functions on binary

operands.

Understand how a 1-bit adder circuit can be designed, how larger adders can
be composed of smaller units and how subtraction can be done on an adder
using two’s complement arithmetic.
 CS220 Computer Architecture
Digital Logic Design

In Today’s Class
Making larger adder circuits faster – the carry lookahead adder

Circuits for interfacing - selecting, routing and exchanging data

Multiplexer, Demultiplexer, Decoder, Encoder circuits

Resolving contention for signal paths using Tri-State Buffers

 CS220 Computer Architecture
Digital Logic Design

Arithmetic and Logic Operations A-B

 CS220 Computer Architecture
Digital Logic Design

Arithmetic and Logic Operations

For large values of n, the delay becomes unacceptably large. In
our adder design, each bit position takes about three gate delays
to produce each carry so in the case of adding, for example, two
32-bit numbers we are looking at a long propagation delay of
about 96 gate delays before the adder computes the total sum of
the numbers.

While the sum value for each bit position can be calculated in
parallel, we need an accelerated way of generating the carry to
overcome the serial performance limitations of the ripple carry
design.
 CS220 Computer Architecture
Digital Logic Design

Arithmetic and Logic Operations

Carry Look-Ahead Adder

The solution is to simultaneously calculate all the carry bits

involved for every bit position. That is, develop a two level sum
of products expression for each carry position.

These carry bits can then be presented in parallel to each of the

1-bit full adders to compute the n sums in parallel using the
usual XOR gate combinations.
 CS220 Computer Architecture
Digital Logic Design

Arithmetic and Logic Operations

Carry Look-Ahead Adder

The design of the look-ahead carry generator involves two

Boolean functions named Generate and Propagate.
For each of the pair wise bits of the number these functions are
defined as:

Gi = Ai .Bi ; Carry will definitely be generated if Ai=1 and Bi=1

Pi = Ai + Bi ; Carry might be generated when this function is
combined with c-outi-1
 CS220 Computer Architecture
Digital Logic Design

Arithmetic and Logic Operations

Carry Look-Ahead Adder – First Stage

The first stage of our 4-bit look ahead adder

 CS220 Computer Architecture
Digital Logic Design

Arithmetic and Logic Operations

Carry Look-Ahead Adder
The carry-out bit c-outi generated when adding two bits Ai and Bi
is 1 if :-
1) The corresponding function Gi is 1 or
2) The c-outi-1=1 and the function Pi = 1 simultaneously.
Therefore, the carry-out bit corresponding to a pair of bits Ai and
Bi is calculated according to the equation:
c-outi = Gi + Pi.c-ini

NOTE: c-outi-1 = c-ini (The carry out from a previous bit position is
 CS220 Computer Architecture
Digital Logic Design

Arithmetic and Logic Operations

Carry Look-Ahead Adder
For a four-bit adder the carry-outs are calculated as follows

c-out0 = G0 + P0.c-in0
c-out1 = G1 + P1.(G0 + P0.c-in0) = G1 + P1G0 + P1P0.c-in0
c-out2 = G2 + P2G1 + P2P1G0 + P2P1P0.c-in0
c-out3 = G3 + P3G2+ P3P2G1 + P3P2P1G0 + P3P2P1P0.c-in0

NB: c-outi-1 = c-ini

 CS220 Computer Architecture
Digital Logic Design

Arithmetic and Logic Operations

Carry Look-Ahead Adder – Second Stage
For a four-bit adder the carry-outs are calculated as follows
c-out0 = G0 + P0.c-in0
c-out1 = G1 + P1.c-in1 = G1 + P1.(G0 + P0.c-in0) = G1 + P1G0 + P1P0.c-in0
c-out2 = G2 + P2.c-in2 = G2 + P2G1 + P2P1G0 + P2P1P0.c-in0
c-out3 = G3 + P3.c-in3 = G3 + P3G2+ P3P2G1 + P3P2P1G0 + P3P2P1P0.c-in0
 CS220 Computer Architecture
Digital Logic Design

Arithmetic and Logic Operations

Carry Look-Ahead Adder – Third Stage
Finally, the sums can be calculated from the following equations,
where c_in is taken from the carry c_out calculated in the circuit
in stage 2.

sum_out0 = A0  B0  c_in0
sum_out1 = A1  B1  c_in1
sum_out2 = A2  B2  c_in2
sum_out3 = A3  B3  c_in3
 CS220 Computer Architecture
Digital Logic Design

Arithmetic and Logic Operations

Carry Look-Ahead Adder – Third Stage

sum_out0 = A0  B0  c_in0
sum_out1 = A1  B1  c_in1
sum_out2 = A2  B2  c_in2
sum_out3 = A3  B3  c_in3
 CS220 Computer Architecture
Digital Logic Design

Arithmetic and Logic Operations

By putting all the stages of the circuit together, you can see that
the critical path through the circuit involves four gate delays
before the complete sum of the four-bit numbers A+B is
calculated.

This represents a significant improvement in circuit performance

over the 4-bit ripple carry adder design.
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Digital Logic Design

Circuits for interfacing

In the next section, we are going to look at some common circuit
types that can be used for selecting and enabling components
and sub circuits and for routing and exchanging data over shared
connections to reduce interconnection costs.

In particular we will look at the purpose of

Multiplexer, Demultiplexer, Decoder and Encoder circuits

We also look at an application of encoders to interrupt

management.
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Digital Logic Design

Data Transmission
The wired exchange of data between two digital systems
requires a pair of wires to create a signalling path between the
two communicating points. Bits are signalled by voltage changes
between the wire pairs over a period of time. Ground
0 1 1 0 1
Data Signal

Bits are transmitted serially in time along the wire. If we want to

send more than one bit simultaneously to achieve greater data
throughput at the same signalling frequency perhaps, then we
need more wire pairs to create additional signalling paths
between the systems.
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Digital Logic Design

Data Transmission
Data in digital systems is sometimes processed and transmitted
in parallel. As an example, consider flat ribbon cables connecting
equipment like hard disks with motherboards over a short
distance. There are multiple pairs of wires acting as signal paths
to enable multiple bits to be transmitted simultaneously from
one point to another.

Ground
0 1 1 0 1
Data Signal
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Digital Logic Design

Bus Data Transmission

At the very highest bus signalling speeds over short distances however, dedicated
single channel serial transmission per device gives higher performance than shared
parallel transmission due to bus arbitration and synchronisation and crosstalk
problems with parallel bus signalling systems. E.g. PCI Express serial bus replaced PCI a
shared parallel extension bus in PCs.

Synchronising all transceivers to send and receive their

individual bits simultaneously in parallel when
operating at very high frequencies is difficult
from an engineering perspective as there can be minor
differences between components and cables.
Crosstalk is a phenomenon where a signal transmitted
on one circuit path creates an undesired effect on
another circuit path due to electromagnetic
interference.
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Digital Logic Design

Aside - Long Haul Data Transmission

Parallel data transfer by copper wire is not used over long distances as
the cost of the multiple interconnections(wires) becomes a factor. For
long distance transmission, a serial conversion of some kind takes
place so that data can be exchanged over a single signal path of two
wires serially.
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Digital Logic Design

Long Haul Data Transmission

Internet services are commonly provided to
houses using pairs of copper wire from the
house to the nearest street cabinet or
exchange. The distance to the street cabinet
determines the maximum speed of your
broadband.

The use of electromagnetic

radio waves for wireless data
transmission enables mobile
communication with nearby
base stations or wifi points.

Longer distance high volume communication is

commonly done using fibre optic cables running
between cell towers and between street cabinets and
exchanges and under the oceans.
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Digital Logic Design

Multiplexing
One of the techniques that can be employed for reducing the
number of connections between devices that need to
communicate is known as multiplexing.

Multiplexing is the process of combining signals from multiple sources

for transmission over the same shared connection by using
synchronised switches. Each source uses the channel for a percentage
of the overall time.
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Digital Logic Design

Multiplexers
To save on the interconnection cost of multiple simple
components, a Multiplexer is a device which connects a number
of inputs to share a single output in time. It selects 1 of the n
input channels and routes it to the output depending on the
value placed on the control inputs.
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Digital Logic Design

Multiplexers
Internal Schematic
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Digital Logic Design

Multiplexing Applications
A multiplexer can be used to share a single wire connection
between data sources and where they are collected/sent and
processed, saving interconnection costs, no network protocols or
contention hardware required.
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Digital Logic Design

Demultiplexer
A demultiplexer performs the opposite function to a multiplexer.
A demultiplexer sends input data to one of its n outputs,
selected by values placed on the control inputs. An application
might involve the control of a number of devices from a remote
distance using a single transmission line with a demultiplexer
circuit on the end.
 CS220 Computer Architecture
Digital Logic Design

Demultiplexer
The internal schematic of a 4-to-1 line Demultiplexer is given
below:-
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Digital Logic Design

Telecommunications Applications
Multiplexer combining multiple inputs into a single data stream
for transmission. On the receiving side, a demultiplexer splits the
single data stream into the original multiple signals.
 CS220 Computer Architecture
Digital Logic Design

Multiplexer Applications
Multiplexers can be used to implement switching functions.
Consider the Full Carry Output from a 1-bit Full-Adder (i.e. A
three variable switching function).
 CS220 Computer Architecture
Digital Logic Design

Multiplexer Applications
Note that this implementation is less efficient (8x4-input AND
and 1x8 input OR) in terms of overall numbers of gates than our
earlier circuit constructed from simple gates.
 CS220 Computer Architecture
Digital Logic Design

Multiplexer Applications
We could also implement the Full Carry function using a 4-1
Multiplexer.
 CS220 Computer Architecture
Digital Logic Design

Tri-State Buffers
A buffer is a logic device whose main purpose is to amplify or
drive output lines when interfacing with other devices. It
provides the necessary current and voltage required by the
interface. In addition, a tri-state buffer provides the ability to
disconnect an output from a shared circuit such as a bus system.

The output stage of a tri-state buffer may be in one of three

states: either 0, 1 or a high impedance state. When in the high
impedance state the flow of any current through the buffer is
prevented and it effectively functions as if the output is
disconnected from anything on the other side of the buffer.
 CS220 Computer Architecture
Digital Logic Design

Tri-State Buffers
Different types of tri-state buffers are described by the symbols
below. The tri-state buffer output may be enabled by an active
high signal (left) or by an active low signal(right) depending on its
type.

The buffer may be inverting(above) or non-inverting(below),

again depending on its type.
 CS220 Computer Architecture
Digital Logic Design

Tri-State Buffers
The ability to ‘disconnect’ a circuit output is important when two
or more outputs are sharing a connection to another system
such as a bus.
A bus is a shared set of communication lines and controlling logic
that interconnects subsystem components in a computer system.

The tri-state buffer provides a mechanism to deal with

‘contention’ for the bus, that is, when both circuits want to use
the bus at the same time. Without one being disconnected, the
two circuits could damage each other and the bus system itself
when they try to apply different logic levels to the same wires.
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Digital Logic Design

Decoders
A decoder translates a binary input to a spatial location, i.e. one
of its 2n outputs is selected and activated depending on the value
placed on its n control inputs.

Some decoders and multiplexers have Enable lines. The outputs

of these devices incorporate tri-state buffers and function as if
they were disconnected if the Enable line is not active.
 CS220 Computer Architecture
Digital Logic Design

Decoders
The Internal Schematic of a 1-of-4 decoder with an enable line
might look as follows:-
 CS220 Computer Architecture
Digital Logic Design

Decoders
Decoders may be used to select and enable other circuits. For
example, A and B could represent part of a memory address. The
output of the decoder could be used to select and activate the
appropriate memory device or to choose a row or column of
cells out of a memory device.
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Digital Logic Design

Decoders
2^32 bit address = 4 GigaBytes of memory space
 CS220 Computer Architecture
Digital Logic Design

Decoders
4 GBytes of DRAM organised as 4x1GByte devices.
2^32 memory locations. ¼ of address space in each module.
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Digital Logic Design

Decoders
The decoder may also be regarded as a minterm generator. Each
output generates one minterm (a product of the control inputs A
and B). By combining the appropriate outputs from the decoder
using an OR gate, you can implement a switching function.
CS220 Computer Architecture
Digital Logic Design
 CS220 Computer Architecture
Digital Logic Design

Implement f(A,B) = ∑m1, m3 using a decoder

 CS220 Computer Architecture
Digital Logic Design

Encoders
Encoders translate a set of inputs into a binary encoding.
If one of the A inputs below is active, the F output represents its
appropriate binary code in the range 0..3.

Encoder
 CS220 Computer Architecture
Digital Logic Design

Encoders
One example application of an encoder might be in fielding
interrupts from various devices connected to the inputs and
then using the outputs to communicate the interrupt number
that has occurred using fewer communication lines for the
signals.
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Digital Logic Design

Encoders
Internal Schematic of 4 to 1 Encoder
F0 = A1 + A3
F1 = A2 + A3

Encoder
 CS220 Computer Architecture
Digital Logic Design

Encoders
Note that this arrangement doesn’t differentiate between device
A0 and no device signalling. Could ignore connection A0.

Encoder
 CS220 Computer Architecture
Digital Logic Design

Encoders
What if more than one encoder input was active at the same
time?
Solution: Design the encoder so that the output corresponds
with the number of the highest priority device.

Encoder
 CS220 Computer Architecture
Digital Logic Design

Encoders
Priority Encoder Design
 CS220 Computer Architecture
Digital Logic Design

Encoders
Priority Encoder Design

F1 = A3+A3’.A2 = A3 + A2
F0 = A3 + A3’.A2’.A1 = A3 + A2’.A1
NR = A3’.A2’.A1’.A0’
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Digital Logic Design

Encoders
Priority Encoder Design

F1 = A3+A3’.A2 = A3 + A2
F0 = A3 + A3’.A2’.A1 = A3 + A2’.A1
NR = A3’.A2’.A1’.A0’