SJUCET – EECE Dept.

ANALOGY & DIGITAL ELECTRONICS

EET05104
Unit 2 – Applications of OPAMP &
Special ICs
Lecture 2-2: Timer IC
By DAVID JUMA, BSc.
EECE Department
Juma,BSc.:
Mr. David
SJUCET – EECE Dept. Lecture 2-2: Timer IC [IC 555]
Lecture 2-2: Outline

1 Introduction to Timer IC (IC 555)

2 Features of 555 Timer

Juma, BSc.:

3 Basic Timer Circuit

4 Functional Block
Mr. David

5 Pin Diagram
 Lecture 2-2: Timer IC [IC 555]
Introduction
 The 555 is a monolithic timing circuit that can
produce accurate & highly stable time delays
or oscillation.
 Used as monostable multivibrator, astable
multivibrator, analog square wave signal
generator, Tachometer frequency meter and
others.
 The timer basically operates in one of two
modes: either
(i) Monostable (one - shot) multivibrator or
(ii) Astable (free running) multivibrator
 Lecture 2-2: Timer IC [IC 555]
The important features of the 555 timer are :
(i) It operates on +4.5v to +18 v supply voltages
(ii) It has an adjustable duty cycle
(iii) Timing is from microseconds to hours
(iv) It has a current o/p
(v) It has two basic operating modes: Monostable
and Astable
(vi) Sinking or sourcing 200 mA of load current.
(vii) It has very high temperature stability as it is designed to
operate in the temperature range of -55 ° C to 125° C.
(viii) The output of a 555 timer can drive a transistor-
transistor logic (TTL) due to its high current output.
(ix) The maximum power dissipation per package is 600 mW
 Lecture 2-2: Timer IC [IC 555]
555 Timer Basics
The 555 timer combines
1. A relaxation oscillator,
2. Two comparators,
3. R-S flip-flop,
4. And a discharge transistor.

(A relaxation oscillator is a nonlinear

electronic oscillator circuit that produces a
nonsinusoidal repetitive output signal, such as a
triangle wave or square wave.)
.
 Lecture 2-2: Timer IC [IC 555]
Concept of RS Flip Flop using (NOR gates)
𝑹
(𝑹𝒆𝒔𝒆𝒕)
X Y NOR
� Notice that these are 00
� complements of each 1
other
01
0

𝑺
� 10
ത
𝑹 𝑺 𝑸ഥ
(𝑺𝒆𝒕)
0
� Q 1 1 State
0
N.B: In writing the 0 0 NC NC No Change (NC)
Truth Table we ensure 0 1 1 0 Set
that the state is stable
i.e. doesn’t change 1 0 0 1 Reset
until
Indeterminate
the input changes. 1 1 0/1 0/1 (Unpredictable)
 Lecture 2-2: Timer IC [IC 555]
SR Latch (NOR version) X Y
0 NOR
0 1
0 1 0
�
1 0 0
� 1 1 0
�
� Present Next
Inputs State State
𝑺 𝑹 𝑸𝒏 𝑸𝒏+𝟏
�
State
�
ത
� 0 0 0 0
No Change (NC)
� 0 0 1 1
0 1 0 0
N.B: In writing the Reset
0 1 1 0
Truth Table we ensure
that the state is stable 1 0 0 1
Set
i.e. doesn’t change 1 0 1 1
until
1 1 0 X Indeterminate
the input changes.
(Invalid)
.

1 1 1 X
 Lecture 2-2: Timer IC [IC 555]
SR Latch (NOR version) X Y NOR
� Note that these are
0 0
� complements of each 1
� 0 1
� other
0

N.B: Q is connected to R and is 𝑸 ഥ

1 0
�
0 connected to
�
ത circuit functions, recall that a HIGH on any input
S, this is opposite to that of NAND
1 version
1 0
�
 To understand how this
�
to a NOR gate forces its output LOW.
 Thus a HIGH on the 𝑺 input will set the 𝑹𝑺 latch, i.e. Q=1 and 𝑸ഥ=0.
 And HIGH on the 𝑹 input will reset it, i.e. Q=0 and 𝑸ഥ=1.
 If Both 𝑹ഥ and ഥ𝑺 are LOW, the latch will remain in its previous state.
 When both 𝑹 and 𝑺 inputs are HIGH, the output is invalid since they
force
outputs of both NOR gates to the HIGH state (Q=1 and 𝑸ഥ=1) which
.

also violates the basic definition of latch that requires Q to be complement

Lecture 2-2: Timer IC [IC 555]

Basic Timer Circuit

 Lecture 2-2: Timer IC [IC 555]

Basic Timer Circuit & Waveforms

 Lecture 2-2: Timer IC [IC 555]

Basic Timing Concept

 From the figure above assume the output
of the S-R flip flop, Q to be high. This high
value is passed on to the base of the
transistor and the transistor gets
saturated, thus producing a zero voltage
at the collector. The capacitor voltage is
clamped at ground, that is, the capacitor
C is shorted and cannot charge.
 Lecture 2-2: Timer IC [IC 555]

Basic Timing Concept

 The inverting input of the comparator is fed
with a control voltage, and the non-inverting
input is fed with a threshold voltage With R-S
flip flop set, the saturated transistor holds the
threshold voltage at zero. The control voltage,
however, is fixed at 2/3 VCC, that is, at 10 volts,
because of the voltage divider.
The threshold voltage is nothing but capacitor
voltage.
 Lecture 2-2: Timer IC [IC 555]
Basic Timing Concept
 Suppose that a high voltage is applied to the R input. This
resets the flip-flop R-Output Q goes low and the transistor
is cut-off. Capacitor C is now free to charge. As this
capacitor C charges, the threshold voltage rises.
Eventually, the threshold voltage becomes slightly greater
than (+ 10 V). The output of the comparator then goes
high, forcing the R-S flip-flop to set The high Q output
saturates the transistor, and this quickly discharges the
capacitor.
 An exponential rise is the capacitor
across C, and a positive going pulse appears
at voltage
capacitor the VC output Q. the
is exponential while Thus
output is
rectangular.
Lecture 2-2: Timer IC [IC 555]

Functional Block
 Lecture 2-2: Timer IC [IC 555]
Pin Configuration
 The 555 Timer IC is available as an 8-pin metal
can, an 8-pin mini DIP (dual-in-package) or a
14-pin DIP. The pin configuration is shown in
the figures.
 Lecture 2-2: Timer IC [IC 555]
Pins Functions
Pin 1: Grounded Terminal
 All the voltages are measured with respect to the
Ground terminal.
Pin 2: Trigger Terminal
 The trigger pin is used to feed the trigger input
then the 555 IC is set up as a
monostable multivibrator. This pin is an
inverting input of a comparator and is
responsible for the transition of flip-flop from
set to reset. The output of the timer depends
on the amplitude of the external trigger
 Lecture 2-2: Timer IC [IC 555]
Pin 2 (cont…)
 The inverting input of the lower comparator
which is compared with Vcc/3, is nothing but
trigger input brought out as pin number 2.
 When the trigger input is slightly less than
Vcc/3 the lower comparator (Comparator 2)
output goes HIGH.
 This output is given to reset input of R-S flip
flop. So high output of comparator 2 resets the
flip flop.
 Lecture 2-2: Timer IC [IC 555]
Pins Functions
Pin 3: Output Terminal:
 Here is where the output of the timer is taken from.
 The complementary signal output (Q’) of the flipflop
goes to pin 3 which is the output.
 There are two ways in which a load can be connected to
the output terminal. One way is to connect between
output pin (pin 3) and ground pin (pin 1) or between pin
3 and supply pin (pin 8). The load connected between
output and ground supply pin is called the normally ON
load and that connected between output and ground
pin is called the normally OFF load.
.
 Lecture 2-2: Timer IC [IC 555]

Pins Functions
Pin 3: Output Terminal:
Normally the output is LOW.
 Lecture 2-2: Timer IC [IC 555]
Pins Functions
Pin 4: Reset Terminal
 Whenever the timer IC is to be reset or
disabled, a negative pulse is applied to pin 4,
and thus is named as reset terminal. The
output is reset irrespective of the input
condition. When this pin is not to be used for
reset purpose, it should be connected to + VCC
to avoid any possibility of false triggering.
 Lecture 2-2: Timer IC [IC 555]
Pins Functions
Pin 5: Control Voltage Terminal
 The threshold and trigger levels are controlled
using this pin. The pulse width of the output
waveform is determined by connecting a POT
or bringing in an external voltage to this pin.
The external voltage applied to this pin can
also be used to modulate the output
waveform.
 Lecture 2-2: Timer IC [IC 555]
Pins Functions
Pin 5: Control Voltage Terminal (cont…)
 Thus, the amount of voltage applied in this
terminal will decide when the comparator is to
be switched, and thus changes the pulse width
of the output.
 When this pin is not used, it should be bypassed
to ground through a 0.01 micro Farad to avoid
any noise problem.
 Lecture 2-2: Timer IC [IC 555]
Pins Functions
Pin 6: Threshold Terminal
 This is the non-inverting input terminal of
comparator 1, which compares the voltage
applied to the terminal with a reference
voltage of 2/3 VCC. The amplitude of voltage
applied to this terminal is responsible for the
set state of flip-flop. When the voltage
applied in this terminal is greater than 2/3Vcc,
the upper comparator switches to +Vsat and
the output gets reset.
 Lecture 2-2: Timer IC [IC 555]
Pins Functions
Pin 7 : Discharge Terminal
 This pin is connected internally to the collector
of transistor and mostly a capacitor is
connected between this terminal and ground.
 It is called discharge terminal because when
transistor saturates, capacitor discharges
through the transistor.
 When the transistor is cut-off, the capacitor
charges at a rate determined by the external
resistor and capacitor.
 Lecture 2-2: Timer IC [IC 555]
Pins Functions
Pin 8: Supply Terminal:
 A supply voltage of + 5 V to + 18 V is applied to
this terminal with respect to ground (pin 1).
.
 Lecture 2-2: Timer IC [IC 555]

555 TIMER
More Functional Block Diagrams
NOTE: You may find
different block
diagrams for Timer
555 as shown in the
following slides but the
Concept is the same
 Lecture 2-2: Timer IC [IC 555]
555 TIMER
More Functional Block Diagram
 Lecture 2-2: Timer IC [IC 555]

555 TIMER
More Functional Block Diagram
(Internal block diagram with pins as appears in
the pin diagram)
.
 Lecture 2-2: Timer IC [IC 555]

555 TIMER
More Functional Block Diagram
b)
 Lecture 2-2: Timer IC [IC 555]
555 TIMER
More Functional Block Diagram
 The block diagram of a 555 timer is shown in the
above figure. A 555 timer has two comparators,
which are basically 2 op-amps), an R-S flip-flop,
two transistors and a resistive network.
Resistive network consists of three equal resistors
and acts as a voltage divider.
 Comparator 1 compares threshold voltage with a
reference voltage + 2/3 VCC volts.
 Comparator 2 compares the trigger voltage with a
reference voltage + 1/3 VCC volts.
.
 Lecture 2-2: Timer IC [IC 555]
More Functional Block Diagram
Resistive network consists of three equal resistors
and acts as a voltage divider.
 When the Threshold at the upper comparator is
higher than the Control voltage then the
output of the comparator will be High which
will results to Q=0 and Q’ = 1
 When the Trigger at the lower comparator
becomes smaller than the Vtl (Control voltage
at the lower comparator) then output of
comparator 2 will be High can only cause the
flip-flop to output low.