© DHBK 2005 1/Chapter2

Course contents
1. Introduction to microprocessor systems
2. The Intel 8088/8086 microprocessors
3. Assembly programming for 8086
4. Memory and I/O Interfacing
5. Interrupt
6. Didect memory access (DMA)
7. Real life microprocessors
© DHBK 2005 2/Chapter2

Chapter 2: The Intel 8088/8086

microprocessors
2.1 Internal architecture
2.2 Pin map
2.3 Memory map of IBM-PC
2.4 Addressing modes of 8086
2.5 Instruction encoding
2.6 Instruction set of 8086
2.7 Protected mode memory management of 80286 machines and
above
© DHBK 2005 3/Chapter2

Chapter 2: The Intel 8088/8086

microprocessors
2.1 Internal architecture
2.1.1 Block diagram
2.1.2 General purpose registers
2.1.3 Segment registers
2.1.4 Index and pointer registers
2.1.5 Flag register
2.1.6 Instruction queue
2.2 Pin map
2.3 Memory map of IBM-PC
2.4 Addressing modes of 8086
2.5 Instruction encoding
2.6 Instruction set of 8086
2.7 Protected mode memory management of 80286 machines and
above
© DHBK 2005 4/Chapter2

Chapter 2: The Intel 8088/8086

microprocessors
2.1 Internal architecture
2.1.1 Block diagram
2.1.2 General purpose registers
2.1.3 Segment registers
2.1.4 Index and pointer registers
2.1.5 Flag register
2.1.6 Instruction queue
2.2 Pin map
2.3 Memory map of IBM-PC
2.4 Addressing modes of 8086
2.5 Instruction encoding
2.6 Instruction set of 8086
2.7 Protected mode memory management of 80286 machines and
above
© DHBK 2005 5/Chapter2

2.1.1 Block diagram of 8088/8086

Address bus
General purpose AX EU 20 bit  BIU
BX Execution Unit Bus Interface Unit
registers Khối thực thi Khối giao tiếp BUS ngoài
CX
DX
SP Segment registers CS
Index and pointer BP and instruction DS
registers SI pointer
SS
DI ES
IP

Data bus
ALU 16 bit Bus control
logic
Temporary registers (hidden)

External
EU Control Bus
ALU Unit
Arithmetic
Logic Unit
Instruction queue
Flags Register (88: 4 bytes; 86: 6 bytes)
© DHBK 2005 6/Chapter2

Chapter 2: The Intel 8088/8086

microprocessors
2.1 Internal architecture
2.1.1 Block diagram
2.1.2 General purpose registers
2.1.3 Segment registers
2.1.4 Index and pointer registers
2.1.5 Flag register
2.1.6 Instruction queue
2.2 Pin map
2.3 Memory map of IBM-PC
2.4 Addressing modes of 8086
2.5 Instruction encoding
2.6 Instruction set of 8086
2.7 Protected mode memory management of 80286 machines and
above
© DHBK 2005 7/Chapter2

2.1.2 General purpose registers

8 Higher bits 8 lower bits

•8088/8086 to 80286 : 16 bits

AX AH AL •80386 and above: 32 bits EAX, EBX,
BX BH BL ECX, EDX

CX CH CL
DX DH DL

• AX (accumulator): stores the result of operations. 8 bit results are stored in

register AL
• BX (base): stores the base address (XLAT)
• CX (count): stores the number of iterations in Loop instruction. CL is used to
store the number of shift or rotation positions in shift and rotate instructions.
• DX (data): used in conjuntion with AX to store the results of 16 bit
multiplicaton and division operations. DX can also be used to store the I/O
port addresses in direct I/O instructions IN/OUT.
© DHBK 2005 8/Chapter2

Chapter 2: The Intel 8088/8086

microprocessors
2.1 Internal architecture
2.1.1 Block diagram
2.1.2 General purpose registers
2.1.3 Segment registers
2.1.4 Index and pointer registers
2.1.5 Flag register
2.1.6 Instruction queue
2.2 Pin map
2.3 Memory map of IBM-PC
2.4 Addressing modes of 8086
2.5 Instruction encoding
2.6 Instruction set of 8086
2.7 Protected mode memory management of 80286 machines and
above
© DHBK 2005 9/Chapter2

2.1.3 Segment registers

• Memory organization in 1 Mbytes momory space
 Memory segment
216 bytes =64 KB
FFFFF
Segment 1: starting address 00000H
Segment 2: starting address 00010H
Last segment: starting address FFFF0H
 Memory cells in one segment:
Offset address
Cell 1: offset=0000H
Last cell: offset=FFFFH
 Physical address: 1FFFF
Segment : offset Offset=F000
1F000

10000 1000
Physical address=Segment*16 + offset
Segment register
real mode memory managment 00000
© DHBK 2005 10/Chapter2

2.1.3 Segment registers

• Example 1: Physical address 12345H
Segment Offset

10000 + 2345H = 2345H

12345H
12000 + 0345H = 0345H
12345H
10040 H = 12345H –
10040H =
0300 H ?

• Example 2: Given the beginning address of the segment 4900x 10H = 49000
H, determine the ending address: maximum offset (16bit) = FFFF H
© DHBK 2005 11/Chapter2

2.1.3 Segment registers

• Segment registers: store the corresponding segment address
(EXE file) FFFFF
.............
58FFF
Đoạn dữ liệu phụ
extra segment
49000 4900 ES
43FFF
Đoạn ngăn xếp
Stack segment
34000 3400 SS
30000
2FFFF Đoạn mã
Code segment
20000 2000 CS
1FFFF Đoạn dữ liệu
Data segment
10000 1000 DS

00000
© DHBK 2005 12/Chapter2

2.1.3 Segment registers

• Overlapped segments (COM file)
FFFFF

s
t
a d
c a
k 0A480
t 0A47F
a c Stack
o 0A280
d 0A28 SS
0A27F
e Data
0A0F0 0A0F DS
0A0EF
Code
090F0 090F CS

00000
© DHBK 2005 13/Chapter2

Chapter 2: The Intel 8088/8086

microprocessors
2.1 Internal architecture
2.1.1 Block diagram
2.1.2 General purpose registers
2.1.3 Segment registers
2.1.4 Index and pointer registers
2.1.5 Flag register
2.1.6 Instruction queue
2.2 Pin map
2.3 Memory map of IBM-PC
2.4 Addressing modes of 8086
2.5 Instruction encoding
2.6 Instruction set of 8086
2.7 Protected mode memory management of 80286 machines and
above
© DHBK 2005 14/Chapter2

2.1.4 Index and pointer registers

• Store the offset address:
 Instruction pointer IP: stores the offset address of the next instruction to
be executed in the Code Segment
Instruction address is CS:IP
 Base Pointer BP: stores the offset address of data in Stack segment
SS:BP
 Stack Pointer SP: stores the offset address of the top of the stack
SS:SP
 Source Index SI: stores the offset address of source data in the Data
Segment in string instructions
DS:SI
 Destination Index DI: stores the offset address of destination data in the
Data Segment in string instructions
DS:DI
 SI and DI may be used as general purpose registers
 80386 and above: 32 bit: EIP, EBP, ESP, EDI, ESI
© DHBK 2005 15/Chapter2

2.1.4 Index and pointer registers

• Default segment and offset

Segment Offset Note

CS IP Instruction address

SS SP or BP Stack address

DS BX, DI, SI, 8 bit or 16 bit Data address

number (constant)

ES DI Destination string
address
© DHBK 2005 16/Chapter2

Chapter 2: The Intel 8088/8086

microprocessors
2.1 Internal architecture
2.1.1 Block diagram
2.1.2 General purpose registers
2.1.3 Segment registers
2.1.4 Index and pointer registers
2.1.5 Flag register
2.1.6 Instruction queue
2.2 Pin map
2.3 Memory map of IBM-PC
2.4 Addressing modes of 8086
2.5 Instruction encoding
2.6 Instruction set of 8086
2.7 Protected mode memory management of 80286 machines and
above
© DHBK 2005 17/Chapter2

2.1.5 Flag Register

15 14 2 1 0
O D I T S Z A P C

• 9 bits are used, 6 status flags:

 C or CF (carry flag): CF=1 when there is carry or borrow from MSB
 P or PF (parity flag): PF=1 (0) when there is an even (odd) number of 1 bit
in the result
 A or AF (auxilary carry flag): AF=1 when there is carry or borrow from a
low BCD digit to higher one.
 Z or ZF (zero flag): ZF=1 when the result is zero
 S or SF (Sign flag): SF=1 when the result is negative.
 O or OF (Overflow flag): OF=1 when the result exceeds the representation
range in signed number addition/subtraction.
© DHBK 2005 18/Chapter2

2.1.5 Flag Register

15 14 2 1 0
O D I T S Z A P C

• 3 control flags
 T or TF (trap flag)): TF=1 => CPU will execute only one instruction at a
time
 I or IF (Interrupt enable flag): IF=1 => maskable interrupts are enabled
 D or DF (direction flag): DF=1 => CPU will work with string from right to
left (instruction STD, CLD)
© DHBK 2005 19/Chapter2

2.1.5 Flag Register

• Example: 80h
+
80h

100h

 SF=0 since msb =0

 PF=1 since the numbe of 1 bit is 0 (even number)
 ZF=1 since the result is 0
 CF=1 since there is carry bit from msb
 OF=1 since adding two negative numbers results a positive number

7Fh
+
01h

????
© DHBK 2005 20/Chapter2

Chapter 2: The Intel 8088/8086

microprocessors
2.1 Internal architecture
2.1.1 Block diagram
2.1.2 General purpose registers
2.1.3 Segment registers
2.1.4 Index and pointer registers
2.1.5 Flag register
2.1.6 Instruction queue
2.2 Pin map
2.3 Memory map of IBM-PC
2.4 Addressing modes of 8086
2.5 Instruction encoding
2.6 Instruction set of 8086
2.7 Protected mode memory management of 80286 machines and
above
© DHBK 2005 21/Chapter2

2.1.6 Instruction queue

• 4 bytes for 8088 and 6 bytes for 8086
• Pipelining

without
pipelining F1 D1 E1 F2 D2 E2 F3 D3 E3
t

F1 D1 E1
with pipelining F2 D2 E2
F3 D3 E3
t
© DHBK 2005 22/Chapter2

Chapter 2: The Intel 8088/8086

microprocessors
2.1 Internal architecture
2.2 Pin map
2.3 Memory map of IBM-PC
2.4 Addressing modes of 8086
2.5 Instruction encoding
2.6 Instruction set of 8086
2.7 Protected mode memory management of 80286 machines and
above
© DHBK 2005 23/Chapter2

2.2 Pin map

Intel 8088
• 16-bit processor
• introduced in 1979
• 3 µm, 5 to 8 MHz, 29 KTOR,
0.33 to 0.66 MIPS
© DHBK 2005 24/Chapter2

2.2 Pin map

Intel 8088

•Min and Max modes:

MN/MX = 1 Min mode

= 0 Max mode with bus controller
8288
© DHBK 2005 25/Chapter2

2.2 Pin map

Intel 8086
© DHBK 2005 26/Chapter2

Chapter 2: The Intel 8088/8086

microprocessors
2.1 Internal architecture
2.2 Pin map
2.3 Memory map of IBM-PC
2.4 Addressing modes of 8086
2.5 Instruction encoding
2.6 Instruction set of 8086
2.7 Protected mode memory management of 80286 machines and
above
© DHBK 2005 27/Chapter2

2.3.1 Start up routine

• When power up or at Reset
 CS=FFFFh and IP=0000 => instructions at FFFF0 directs CPU to jump to
the BIOS programs.
 BIOS programs check memory and system hardwares
 BIOS programs initiates interrupt vector table and BIOS data area
 BIOS loads boot program from the hard disk to main memory
 Boot program loads the operating system into memory
 The OS loads application programs into memory
© DHBK 2005 28/Chapter2

2.3.2 Memory map of IBM-PC

Extended
memory

FFFFF System memory

384 Kbytes
A0000 1 Mbytes
9FFFF Physical memory
Program memory
640 Kbytes
00000
© DHBK 2005 29/Chapter2

2.3.2 Memory map of IBM-PC

Program memory
9FFFF
MSDOS
9FFF0

Application program area

08E30
COMMAND.COM
08490
Device drivers (mouse.sys)
02530
MSDOS
01160
IO.SYS
00700
DOS area
00500
BIOS area
00400
00000 Interrupt vector table
© DHBK 2005 30/Chapter2

2.3.2 Memory map of IBM-PC

System memory
FFFFF
ROM BIOS
F0000
ROM BASIC
E0000

Reserved area

C8000
Video BIOS ROM
C0000
Video RAM (text)
B0000
Video RAM (graphics)
A0000
© DHBK 2005 31/Chapter2

2.3.2 Memory map of IBM-PC

Reserved memory area of 8088/8086
FFFFF
Reset Bootstrap
FFFF0 program jump

003FF
Interrupt vectors
00000
© DHBK 2005 32/Chapter2

2.3.2 Memory map of IBM-PC

I/O address
• Addresses: 0000H –FFFFH, M/IO =0
FFFF

Extended area

COM1
03F8
Floppy disk controller
03F0
CGA adapter
03D0
LPT1
0378
Hard disk controller
0320
COM2
02F8
8255
0060
Timer (8253)
0040
Interrupt controller
0020
0000 DMA conntroller
© DHBK 2005 33/Chapter2

Chapter 2: The Intel 8088/8086

microprocessors
2.1 Internal architecture
2.2 Pin map
2.3 Memory map of IBM-PC
2.4 Addressing modes of 8086
2.4.1 Register addressing
2.4.2 Immediate addressing
2.4.3 Direct addressing
2.4.4 Register indirect addressing
2.4.5 Based relative addressing
2.4.6 Indexed relative addressing
2.4.7 Based Indexed relative Addressing
2.5 Instruction encoding
2.6 Instruction set of 8086
2.7 Protected mode memory management of 80286 machines and
above
© DHBK 2005 34/Chapter2

2.4.1 Register Addressing Mode

• Registers are used as operands
• High speed

• Examples:
 MOV BX, DX ; Copy the content of DX into BX, the content of DX is
unchanged
 MOV AL, BL ;
 ADD AL, DL ; AL=AL+DL
© DHBK 2005 35/Chapter2

2.4.2 Immediate Addressing Mode

• Destination operand is a register or memory location
• Source operand is a constant
• Used to load a constant into registers (except segment registers
and flags) or memory location in Data segment.
• Examples:
 MOV BL, 44 ; Copy 44 into BL
 MOV AX, 44H ; Copy 0044H into AX
 MOV AL, ‘A’ ; Copy ASCII code of ‘A’ into AL
 MOV [BX], 10 ; copy 10 into memory location with address DS:BX
© DHBK 2005 36/Chapter2

2.4.3 Direct Addressing Mode

• One operand is memory address which stores data, the other
must be a register

• Examples:
 MOV AL, [ 1234H ] ; Copy the content of memory location with address
DS:1234 into AL
 MOV [ 4320H ], CX ; Copy the content of CX into two consecutive memory
locations with addresses DS: 4320 and DS: 4321
© DHBK 2005 37/Chapter2

2.4.4 Register indirect Addressing Mode

• One operand is a memory address stored in a register, the
other must be a register
• Examples:
 MOV AL, [BX] ; Copy the content of memory location with address DS:BX
into AL
 MOV [ SI ], CL ; Copy the content of CL into memory location with
address DS:SI
 MOV [ DI ], AX ; copy the content of AX into two consecutive memory
locations with addresses DS: DI and DS: (DI +1)
© DHBK 2005 38/Chapter2

2.4.5 Based relative Addressing Mode

• One operand is base registers BX, BP plus constants
representing displacements, the other must be a register.
• Examples:
 MOV CX, [BX]+10 ; Copy the content of two consecutive memory
locations with addresses DS:BX+10 and DS:BX+11 into CX
 MOV CX, [BX+10] ; similar to the above example
 MOV AL, [BP]+5 ; copy the content of memory location with address
SS:BP+5 into AL
© DHBK 2005 39/Chapter2

2.4.6 Indexed relative Addressing Mode

• One operand is index registers SI, DI plus constants
representing displacements, the other must be a register
• Examples:
 MOV AX, [SI]+10 ; Copy the content of two consecutive memory locations
with addresses DS:SI+10 and DS:SI+11 into AX
 MOV AX, [SI+10] ; similar to the above example
 MOV AL, [DI]+5 ; copy the content of memory location with address
DS:DI+5 into AL
© DHBK 2005 40/Chapter2

2.4.7 Based Indexed relative Addressing Mode

• Examples:
 MOV AX, [BX] [SI]+8 ; Copy the content of two consecutive memory
locations with addresses DS:BX+SI+8 and DS:BX+SI+9 into AX
 MOV AX, [BX+SI+8] ;
 MOV CL, [BP+DI+5] ; copy the content of memory location with address
SS:BP+DI+5 into CL
© DHBK 2005 41/Chapter2

Summary of addressing modes

Addressing mode Operand Default segment register

Register Registers

Immediate Constant data

Direct [offset] DS

Register indirect [BX] DS

[SI] DS
[DI] DS

Based relative [BX] + displacement DS

[BP] + displacement SS
Indexed relative [DI] + displacement DS
[SI] + displacement DS
Based indexed relative [BX] + [DI]+ displacement DS
[BX] + [SI]+ displacement DS
[BP] + [DI]+ displacement SS
[BP] + [SI]+ displacement SS
© DHBK 2005 42/Chapter2

Segment override

• Examples:
 MOV AL, [BX]; Copy the content of memory location with address DS:BX
into AL
 MOV AL, ES:[BX] ; Copy the content of memory location with address
ES:BX into AL
© DHBK 2005 43/Chapter2

Chapter 2: The Intel 8088/8086

microprocessors
2.1 Internal architecture
2.2 Pin map
2.3 Memory map of IBM-PC
2.4 Addressing modes of 8086
2.5 Instruction encoding
2.6 Instruction set of 8086
2.7 Protected mode memory management of 80286 machines and
above
© DHBK 2005 44/Chapter2

2.5 8086 Instruction encoding

• One instruction may have a size from 1 to 6 bytes
Opcode MOD-REG-R/M Displacement Immediate
1-2 byte 0-1 byte 0-2 byte 0-2 byte

Byte Opcode

D W

W=0 1 byte data

Opcode
W=1 2 byte data

D=1 data flow to the register encoded with 3 bits REG

D=0 data flow from the register encoded with 3 bits REG
 © DHBK 2005 45/Chapter2

2.5 8086 Instruction encoding

7 6 5 4 3 2 1 0

MOD REG R/M

MOD <> 11

0 no displacement Register Code Code Addressing mode

1 8 bit displacement
W=1 W=0 000 DS:[BX+SI]
0 16 bit displacement
AX AL 000 001 DS:[BX+DI]
1 R/M is a register BX BL 011 010 SS:[BP+SI]
CX CL 001 011 SS:[BP+DI]
DX DL 010 100 DS:[SI]
SP AH 100 101 DS:[DI]
DI BH 111 110 SS:[BP]
BP CH 101 111 DS:[BX]
SI DH 110
© DHBK 2005 46/Chapter2

2.5 8086 Instruction encoding

• Example 1: Encode MOV CL, [BX] into machine code
 opcode MOV: 100010
 1 byte data: W=0
 To register: D=1
 No displacement: MOD=00
 [BX] => R/M=111
 CL => REG=001

1 0 0 0 1 0 1 0 0 0 0 0 1 1 1 1

MOV MOD CL [BX]

D W

Example 2: Encode MOV [SI+F3H], CL into machine code

© DHBK 2005 47/Chapter2

Chapter 2: The Intel 8088/8086

microprocessors
2.1 Internal architecture
2.2 Pin map
2.3 Memory map of IBM-PC
2.4 Addressing modes of 8086
2.5 Instruction encoding
2.6 Instruction set of 8086
2.6.1 Data movement/modification instructions
2.6.2 Arithmetic and logic instructions
2.6.3 Program control instructions
2.6.4 Other instructions
2.7 Protected mode memory management of 80286 machines and
above
© DHBK 2005 48/Chapter2

Chapter 2: The Intel 8088/8086

microprocessors
2.1 Internal architecture
2.2 Pin map
2.3 Memory map of IBM-PC
2.4 Addressing modes of 8086
2.5 Instruction encoding
2.6 Instruction set of 8086
2.6.1 Data movement/modification instructions
2.6.2 Arithmetic and logic instructions
2.6.3 Program control instructions
2.6.4 Other instructions
2.7 Protected mode memory management of 80286 machines and
above
© DHBK 2005 49/Chapter2

2.6.1 Data movement instructions

• MOV, XCHG, POP, PUSH, POPF, PUSHF, IN, OUT, LDS, LEA,
LES
• String movement instructions MOVS, MOVSB, MOVSW,
LODS(B/W)

• MOV
 Used to move data amongst registers, between one register and one
memory location or move a constant into a register or a memory location
 Syntax: MOV Destination, source
 This instruction doesn’t affect flags.
 Examples:
MOV AX, BX
MOV AH, ‘A’
MOV AL, [1234H]
© DHBK 2005 50/Chapter2

2.6.1 Data movement instructions

• Operands combination possibilities for MOV instruction

Dest GPR Segment Memory Constant

register location
Source
GPR YES YES YES NO

Segment YES NO YES NO

register

Memory YES YES NO NO

location

Constant YES NO YES NO

© DHBK 2005 51/Chapter2

2.6.1 Data movement instructions

• XCHG (Exchange 2 operands)
 Used to swap the content of two registers or one register and one memory
location
 Syntax: XCHG destination, source
 Constraint: operands must not be segment registers
 This instruction has no effect on flags
 Examples:
 XCHG AX, BX
 XCHG AX, [BX]
• LEA- Load Effective Address
 Load effective address into a register
 Operation: Destination= offset address (i.e. effective address) of source
 Examples:
 LEA DX,Message
 LEA CX,[BX][DI]
© DHBK 2005 52/Chapter2

2.6.1 Data movement instructions

• PUSH
 Used to store one word from a register or memory to the top of the stack
 Syntax: PUSH Source
 Description: SP=SP-2, Source => {SP}
 Constraint: 16 bit register or 16 bit memory
 This instruction has no effect on flags
 Examples:
 PUSH BX
 PUSH PTR[BX]

• PUSHF
 Store the content of flag register on top of the stack
© DHBK 2005 53/Chapter2

2.6.1 Data movement instructions

• PUSH example PUSH AX PUSH BX
SP
1300A 1300A 1300A
13009 13009 12 13009 12
13008 13008 SP 13008
34 34
13007 13007 13007 78
13006 13006 13006 SP
56
13005 13005 13005
13004 13004 13004
13003 13003 13003
13002 13002 13002
13001 13001 13001
13000 13000 13000

SS 1300 SS 1300 SS 1300

SP 000A SP 0008 SP 0006

AX 1234 AX 1234 BX 7856

© DHBK 2005 54/Chapter2

2.6.1 Data movement instructions

• POP
 Used to retrieve one word from the top of the stack into a register or memory
locations.
 Syntax: POP Destination
 Description: {SP} => Destination, SP=SP+2
 Constraint: 16 bit registers (except IP) or 16 bit memory
 This instruction has no effect on flags
 Examples:
 POP BX
 POP PTR[BX]
• POPF
 Copy 16 bits from the top of the stack to Flag register
© DHBK 2005 55/Chapter2

2.6.1 Data movement instructions

• POP instruction example POP DX

1300A 1300A
13009 12 13009 12
13008 34 13008 34 SP
13007 78 13007 78
13006 SP 13006
56 56
13005 13005
13004 13004
13003 13003
13002 13002
13001 13001
13000 13000

SS 1300 SS 1300

SP 0006 SP 0008

DX 1234 DX 7856
© DHBK 2005 56/Chapter2

2.6.1 Data movement instructions

• Example of using PUSH, POP
MOV AX, 10
MOV BX, 20
LCALL subProgram; call sub program
;AX=?, BX=?

subProgram:
PUSH AX ; Store AX into stack
PUSH BX ; Store BX into stack
PUSHF
MOV AX,0 ;
MOV BX, 10
POPF
POP BX ; Get back the old values of AX, BX
POP AX
RET ;Return to the main program
© DHBK 2005 57/Chapter2

2.6.1 Data movement instructions

• IN
 Used to read 1 byte or 2 bytes data from a port into AL or AX
 Syntax: IN Acc, Port
 This instruction has no effect on flags
 Examples:
 IN AX, 00H MOV DX,03F8h
 IN AL, F0H IN AL,DX
 IN AX, DX
• OUT
 Used to write 1 byte or 2 bytes data from AL or AX to a port
 Syntax: OUT Port, Acc
 This instruction has no effect on flags
 Examples:
 OUT 00H, AX
 OUT F0H, AL
 OUT DX, AX
© DHBK 2005 58/Chapter2

Chapter 2: The Intel 8088/8086

microprocessors
2.1 Internal architecture
2.2 Pin map
2.3 Memory map of IBM-PC
2.4 Addressing modes of 8086
2.5 Instruction encoding
2.6 Instruction set of 8086
2.6.1 Data movement/modification instructions
2.6.2 Arithmetic and logic instructions
2.6.3 Program control instructions
2.6.4 Other instructions
2.7 Protected mode memory management of 80286 machines and
above
© DHBK 2005 59/Chapter2

2.6.2 Arithmetic and logic instructions

• ADD, ADC, SUB, MUL, IMUL, DIV, IDIV, INC, DEC
• AND, OR, NOT, NEG, XOR
• Rotate and shift: RCL, ROL, RCR, ROR, SAL, SAR, SHL, SHR
• Comparison: CMP, CMPS

• ADD
 Syntax: ADD destination, source
 Operation: destination=detination + source
 Constraints: both operands must not be memory locations nor segment
registers
 This instruction affects the following flags: AF, CF, OF, PF, SF, ZF
 Examples:
ADD AX, BX
ADD AX, 40H
© DHBK 2005 60/Chapter2

2.6.2 Arithmetic and logic instructions

• ADC (add with carry)
 Syntax: ADD destination, source
 Operation: destination=detination + source + CF
 Constraints: both operands must not be memory locations nor segment
registers
 This instruction affects the following flags: AF, CF, OF, PF, SF, ZF
 Example:
ADD AL, 30H
• SUB
 Syntax: SUB destination, source
 Operation: destination=detination - source
 Constraints: both operands must not be memory locations nor segment
registers
 This instruction affects the following flags: AF, CF, OF, PF, SF, ZF
 Example:
SUB AL, 30H
© DHBK 2005 61/Chapter2

2.6.2 Arithmetic and logic instructions

• MUL
 Unsigned multiplication
 Syntax: MUL source (source must be a register)
 Operation:
 AX=AL* 8bitSource
DXAX=AX * 16bitSource
 This instruction affects the following flags : CF, OF
 Examples:
MUL BL ; AX=AL*BL
MUL BX ; DXAX=AX*BX
• IMUL
 Singed multiplication
© DHBK 2005 62/Chapter2

2.6.2 Arithmetic and logic instructions

• DIV
 Unsigned division
 Syntax: DIV source
 Operation:
AL = quotient (AX / 8bitSource) ; AH=remainder (AX / 8bitSource)
AX = quotient (DXAX / 16bitSource) ; DX=remainder (DXAX / 16bitSource)
 This instruction has no effect on flags
 Example:
DIV BL
• IDIV
 Singed division
© DHBK 2005 63/Chapter2

2.6.2 Arithmetic and logic instructions

• INC-Increase by 1
 Syntax: INC destination
 Operation: destination=destination + 1
 This instruction affects the following flags : AF, OF, PF, SF, ZF
 Example:
INC AX
• DEC-Decrease by 1
 Syntax: DEC destination
 Operation: destination=destination - 1
 This instruction affects the following flags : AF, OF, PF, SF, ZF
 Example:
DEC [BX]
© DHBK 2005 64/Chapter2

2.6.2 Arithmetic and logic instructions

• AND
 Syntax: AND destination, source
 Operation: destination=destination And source
 Constraints: both operands must not be memory locations nor segment
registers
 This instruction modifies: PF, SF, ZF and clears CF, OF
 Example:
AND BL, 0FH
• XOR, OR: similar to AND

• NOT: returns one-complement of the operand

• NEG: returns two-complement of the operand
© DHBK 2005 65/Chapter2

2.6.2 Arithmetic and logic instructions

• CMP-Compare 2 operands to Update the Flags
 Syntax: CMP destination, source
 Operation:
dest =src : CF=0 ZF=1
dest> src : CF=0 ZF=0
dest < src : CF=1 ZF=0
© DHBK 2005 66/Chapter2

2.6.2 Arithmetic and logic instructions

• TEST - AND 2 operands to Update the Flags
 Syntax: TEST Operand1,Operand2
 Example: test bit 0 of AL
TEST AL,01h ;ZF=1 if AL.0=0, ZF=0 if AL.0=1
• Flag setting instructions
 STC-Set the Carry Flag CF=1
 STD-Set the Direction Flag DF=1
 STI-Set the Interrupt Flag IF=1
• Flag clear instructions
 CLC-Clear the Carry Flag CF=0
 CLD-Clear the Direction Flag DF=0
 CLI-Clear the Interrupt Flag IF=0
• CMC-Complement the Carry Flag CF=not(CF)
© DHBK 2005 67/Chapter2

2.6.2 Arithmetic and logic instructions

• RCL-Rotate through Carry flag to the Left
 Syntax: RCL destination, CL
RCL destination, 1
RCL destination, number of places # 1 (only for 80286
and above)
 Operation: rotate destination CL places
 This instruction modifies: CF, OF
CF MSB LSB

• RCR-Rotate through Carry flag to the Right

© DHBK 2005 68/Chapter2

2.6.2 Arithmetic and logic instructions

• Example 1: RCL AL,1
CF AL

1 0 1 0 0 1 1 0 1

• Example 2: RCR AL,1

CF AL

0 1 0 0 1 1 0 1 1
© DHBK 2005 69/Chapter2

2.6.2 Arithmetic and logic instructions

• SAL-Shift Arithmetically Left
 Syntax: SAL destination, CL
SAL destination, 1
SAL destination, number of placess # 1 (only for 80286
and above)
 Operation: shift left destination CL places, dest=dest*2 CL
 This instruction modifies SF, ZF, PF
CF MSB LSB

• SHL-SHift Left
 Logic shift left, similar to SAL
© DHBK 2005 70/Chapter2

2.6.2 Arithmetic and logic instructions

• Example: SAL AL,1

CF AL

0 0 1 0 0 1 0 1 0

• Before: AL=25H=37

• After: AL=4AH=74
© DHBK 2005 71/Chapter2

2.6.2 Arithmetic and logic instructions

• SAR-Shift Arithmetically Right
 Syntax: SAR destination, CL
SAR destination, 1
SAR destination, number of places # 1 (only for 80286 and
above)
 Operation: shift right destination CL places. dest=dest/2 CL
 This instruction modifies SF, ZF, PF. CF takes the value of LSB
MSB LSB CF
© DHBK 2005 72/Chapter2

2.6.2 Arithmetic and logic instructions

• SHR-SHift Right
 Syntax: SHR destination, CL
SHR destination, 1
SHR destination, number of places # 1 (only for 80286 and
above)
 Operation: shift right destination CL places.
 This instruction modifies SF, ZF, PF. CF takes the value of LSB
MSB LSB CF

0
© DHBK 2005 73/Chapter2

2.6.2 Arithmetic and logic instructions

• Example 1: SAR AL,1

AL CF

1 0 1 0 0 1 1 0

Before: AL=A6H=-90(166) After: AL=D3H=-45(211)

• Example 2: SHR AL,1

AL CF

0 1 0 1 0 0 1 1 0

Before: AL=A6H=-90 (166) After: AL=53H=+83

© DHBK 2005 74/Chapter2

Chapter 2: The Intel 8088/8086

microprocessors
2.1 Internal architecture
2.2 Pin map
2.3 Memory map of IBM-PC
2.4 Addressing modes of 8086
2.5 Instruction encoding
2.6 Instruction set of 8086
2.6.1 Data movement/modification instructions
2.6.2 Arithmetic and logic instructions
2.6.3 Program control instructions
2.6.4 Other instructions
2.7 Protected mode memory management of 80286 machines and
above
© DHBK 2005 75/Chapter2

2.6.3 Program control instructions

Unconditional jump JMP
• Used to jump to a memory location in memory
• 3 types: short jump, near jump and far jump
 Short jump
Instruction length 2 bytes:
E B displacement

Jump scope: -128 to 127 bytes from the instruction right after JMP instruction
Operation: IP=IP + displacement

Example:

XOR BX, BX
Label1: MOV AX, 1
ADD AX, BX
JMP SHORT Label1
© DHBK 2005 76/Chapter2

2.6.3 Program control instructions

Unconditional jump JMP
 Near jump
Jump scope: ± 32 Kbytes from the instruction right after JMP instruction
Example:

XOR BX, BX XOR CX, CX XOR CX, CX

Label1: MOV AX, 1 MOV AX, 1 MOV AX, 1
ADD AX, BX ADD AX, BX ADD AX, BX
JMP NEAR Label1 JMP NEAR PTR BX JMP WORD PTR [BX]

Operation: IP=IP+ displacement IP=BX IP=[BX+1] [BX]

E 9 DispLo DispHi
Indirect jump
© DHBK 2005 77/Chapter2

2.6.3 Program control instructions

Conditional jump
• JE/JZ, JNE/JNZ, JG/JNLE, JGE/JNL, JL/JNGE, JLE/JNG (used
for singed numbers) and
JA/JNBE, JB/JC/JNAE, JAE/JNB/JNC, JBE/JNA (used for
unsigned numbers) and
JNP/JPO, JP/JPE, JNS
• Jump operation depends on the flags
• Conditional jump instructions are short jump.
• Example: Lable1: XOR BX, BX
Label2: MOV AX, 1
CMP AL, 10H Operation: IP=IP + displacement
JNE Label1
JE Label2
© DHBK 2005 78/Chapter2

2.6.3 Program control instructions

LOOP instructions
• LOOP, LOOPE/LOOPZ, LOOPNE/LOOPNZ
• Combination between DEC CX and JNZ

XOR AL, AL XOR AL, AL XOR AL, AL

MOV CX, 16 MOV CX, 16 MOV CX, 16

Label1: INC AL Label1: INC AL Label1: INC AL

LOOP Label1 CMP AL, 10 CMP AL, 10

LOOPE Label1 LOOPNE Label1

Loop until CX=0 Loop until CX=0 Loop until CX=0

or AL<>10 (ZF=0) or AL=10
© DHBK 2005 79/Chapter2

2.6.3 Program control instructions

CALL and RET instructions
• Used to call subprogram
• 2 types: near CALL and far CALL
 near call: similar to near jump instruction
Call sub program in the same code segment

Tong PROC NEAR Tong PROC NEAR

ADD AX, BX
ADD AX, BX
ADD AX, CX
ADD AX, CX RET
Tong ENDP
RET
...
Tong ENDP MOV BX, OFFSET Tong
CALL BX
...
CALL Tong
Store IP into the stack Store IP into the stack
IP=IP + displacement IP= BX
RET: get IP back from stack RET: get IP back from stack
© DHBK 2005 80/Chapter2

2.6.3 Program control instructions

CALL and RET instructions
 Far call
Call a sub program outside the current code segment

Tong PROC FAR

ADD AX, BX
ADD AX, CX
RET
Tong ENDP
...
CALL Tong

Store CS in stack
Store IP in stack
IP=IP of Tong
CS =CS of Tong
RET: get IP and CS back
from stack
© DHBK 2005 81/Chapter2

2.6.3 Program control instructions

INT and IRET instructions
• INT call interrupt service subroutines (ISS)
• Interrupt vector table: 1 Kbytes 00000H to 003FFH
 256 interrupt vectors
 1 vector 4 bytes, contains IP and CS of ISS
 32 first vectors are reserved for Intel
 224 last vectors are for user use

• Syntax: INT Number

• Example: INT 21H call the ISS of DOS
© DHBK 2005 82/Chapter2

2.6.3 Program control instructions

INT and IRET instructions
• INT operations:
 Store flag register in the stack
 Set IF=0, TF=0
 Store CS in the stack
 Store IP in the stack
 IP=[N*4], CS=[N*4+2]
• IRET:
 Get IP back from the stack
 Get CS back from the stack
 Get Flag register back from the stack
© DHBK 2005 83/Chapter2

Chapter 2: The Intel 8088/8086

microprocessors
2.1 Internal architecture
2.2 Pin map
2.3 Memory map of IBM-PC
2.4 Addressing modes of 8086
2.5 Instruction encoding
2.6 Instruction set of 8086
2.6.1 Data movement/modification instructions
2.6.2 Arithmetic and logic instructions
2.6.3 Program control instructions
2.6.4 Other instructions
2.7 Protected mode memory management of 80286 machines and
above
© DHBK 2005 84/Chapter2

2.6.4 Other instructions

• NOP-No Operation (takes 3 clock cycles)

• WAIT-Wait for TEST or INTR Signal
 Wait until TEST pin is asserted or INTR pin is asserted
© DHBK 2005 85/Chapter2

Chapter 2: The Intel 8088/8086

microprocessors
2.1 Internal architecture
2.2 Pin map
2.3 Memory map of IBM-PC
2.4 Addressing modes of 8086
2.5 Instruction encoding
2.6 Instruction set of 8086
2.7 Protected mode memory management of 80286 machines and
above
© DHBK 2005 86/Chapter2

2.7 Protected mode memory management of

80286 machines and above
• Why?
 Support multitasking for 80286 machines and above.
 Backward compatible with 8086.
 Allow to access data and instruction in the memory area above 1M
• Offset registers store offset address
• Segment registers store segment selector
 Segment selector selects one segment descriptor in one of two
Descriptor Tables, each is 64 KB in size.
Global DT: stores information about the memory segments which can be
accessed by all programs.
Local DT stores information about memory segements of one particular
program.
 Segment descriptor stores information about the starting address of the
segment.
© DHBK 2005 87/Chapter2

2.7 Protected mode memory management of

80286 machines and above
segment selector
15 2 1 0

Index TI RPL

RPL: requested priority level, 00 highest, 11 lowest

TI=0, use GDT, TI=1 use LDT
Index: 13 bit to select 1 from 8K segment descriptors in DT

GDOA Limit
7 00000000 00000000 6 7 Base(B31-B24) 6
V (L19-L16)
5 Access rights Base(B23-B16) 4 5 Access rights Base(B23-B16) 4
3 Base(B15-B0) 2 3 Base(B15-B0) 2
1 Limit(L15-L0) 0 1 Limit(L15-L0) 0

Segment descriptor of 80286 Segment descriptor of 80386

and above
Base: starting address of the segment
Limit: the last offset address found in a segment
© DHBK 2005 88/Chapter2

2.7 Protected mode memory management of

80286 machines and above
• 80286
 Base 24 bit: 000000H to FFFFFFH (16 MB)
 Limit 16 bit: segment size from 1 to 64 KB
 Physical address= Base + offset
 1 program can use at maximum: 2*8K*64 K= 1GB memory => virtual
memory
• 80386/486/Pentium
 Base 32 bit: 00000000H to FFFFFFFFH (4 GB)
 Limit 20 bit:
 G=0: segment size from 1 to 1MB
 G=1: segment size from 4K to 4 GB
 Physical address= Base + offset
 1 program can use at maximum : 2*8K*4 GB= 64 Terabytes memory