EC 401

Historical Perspective , Design Hierarchy, Concepts of Regularity, Modularity and

Locality, VLSI Design Styles , VLSI Design Flo w , Se mi Custom- Full Custom IC Design
Flow , Data Path, Control
Path Programmable Logic Array, CMOS And Bipolar Transistor Gate Arrays And
Their Limitations ,
Standard Cells , FP GA/CP LD Architecture , Compute r-Aide d De sign Technology
1. Entity Declaration
Describes external view of the design.
2. Architecture Body (AB)
Describes internal view of the design.

3. Configuration Declaration
4. Package Declaration
Library Declaration
5. Package Body
 CONCURRENT STATEMENTS / SEQUENTIAL
a
-- Code Fragment A
Y1
b Architecture test of example is
begin
Y
y1 <= a and b;
y2 <= c and d;
c
Y2 y <= y1 or y2;
d end architecture test;

-- Code Fragment B -- Code Fragment C

Architecture test of example is Architecture test of example is
begin begin
y <= y1 or y2; y2 <= c and d;
y2 <= c and d; y <= y1 or y2;
y1 <= a and b; y1 <= a and b;

end architecture test; end architecture test;

Entity Declaration
Describes I/O of the design. I/O Signals
are called ports.

Entity design_name is

port(signal1,signal2,…..:mode type;
signal3,signal4,…..:mode type);

End entity design_name;

Entity myexample is
port( a,b,c: in std_logic;
s: in std_logic_vector(1 downto 0);
e,f: out std_logic;
y: out std_logic_vector(4 downto 0));
end entity myexample;
• Architecture name of entity_name
is
internal signal and constant
declarations
Begin
Concurrent statement 1;
Concurrent statement 2;
Concurrent statement 3;
Concurrent statement 4;
End architecture name;
 Complex Concurrent Statements
with-select-when
with-select-when
Syntax is
with select_signal select
signal_name <= value1 when value1_of_select_sig,
value2 when value2_of_select_sig,
value3 when value3_of_select_sig,
value_default when others;
---- library statements
entity mytest is
port( a3,a2,a1,a0: in std_logic_vector(3 downto 0);
s: in std_logic_vector(1 downto 0);
y: out std_logic_vector(3 downto 0));
end entity my_test;
architecture behavior of mytest is
begin
with s select
y <= a3 when “11”,
a2 when “10”,
a1 when “01”,
a0 when others; -- default condition
end architecture behavior;
VHDL is an Object Oriented Programming (OOP)
Language. Objects can have values, attributes and
methods. We will primarily use the following VHDL
data objects:

Signals
Constants
Variables
Sequential Statements

Squential statements are executed within

a process block. Syntax is:

[label:] process (sensitivity list)

constant or variable declarations
begin
sequential statements;
end process [label];
---- library statements
entity and_example is
port(a,b: in std_logic;
ya,yb,yc: out std_logic);
End entity and_example; -- Process Block
process(a,b)
begin
Architecture test of
yc <= ‘0’;
and_example is if ((a=‘1’) and (b = ‘1’)) then yc <= ‘1’;
begin else yc <= ‘0’;
--- dataflow model end if;
ya <= a and b; end process;
End architecture test;

--- structural model

a_7408 port map(a,b,yb);
 Entity: Data flow

Architecture: Structural

Behavioral

Example of Multiplexer:
 Data Flow

SIGNALS AND COMPONENTS

Concurrent Statements
Structural
 Behavioral

Only 1 is true

Sequential Statements

Only 1 is true
 Mixed

Process
{Sequential
Statements}
Con

Con
Sequential Statements
 Data Types / Attributes

VHDL is an Object Oriented Programming (OOP)

Language. Objects can have values, attributes and
methods. We will primarily use the following VHDL
data objects:
Signals
Constants
Variables

The types allowed in VHDL consist of everything from

scalar numeric types to,
composite arrays and records to file types
 Signals:
which represents interconnection wires that connect
component instantiation ports together

Variables:
which is used for local storage of temporary data, visible
only inside a process.

Constants :
Constant, which names specific values.
SIGNAL signal_name : signal_type [:= initial_value];
Signals in package declarations
are referred to as global signals because they
can be shared among entities.

Local: Inside the architecture

Global: Inside the Entity
 Variables are used for local storage in process statements
and subprograms

• Variables assignments happen immediately, while signals

must be scheduled to occur.
• Variables take less memory, while signals need more
information to allow for scheduling and signal attributes.
• Using a signal would have required a WAIT statement to
synchronize the signal assignment to the same execution
iteration as the usage.

Constants: Give the designer the ability to have a better documented

model, and a model that is easy to update.

CONSTANT constant_name {,constant_name} : type_name[:=value];

 A wide range of types that can be used to create
simple or complex objects (Sg, Varb, Constants)

TYPE type_name IS type_mark;

It is an address, or a handle, to
a specific object. = Pointer

Scalar types describe objects that can hold, at most, one value at a time

-1.0E 38 to 1.0E38.
All of the values of an enumerated type are user defined

A typical enumerated type for a four-state simulation value system

looks
TYPE fourval IS ( ‘X’, ‘0’, ‘1’, ‘Z’);

This type contains four character literal values that each represent a unique state in the four-
state value system. The values represent the following conditions:

• ‘X’—An unknown value

• ‘0’—A logical 0 or false value
• ‘1’—A logical 1 or true value
• ‘Z’—A tristate or open collector value

Physical types are used to represent physical quantities such as

distance, current, time etc.
Array types are groups of elements of the same type, while Record
types allow the grouping of elements of different types. Arrays are
useful for modeling linear structures such as RAMs and ROMs,
while records are useful for modeling data packets, instructions.

A file object can be read from, written to, and checked for end of file
only with special procedures and functions.
Files consist of sequential streams of a particular type. A file whose
base object type is INTEGER consists of a sequential stream of
integers
Example for Attributes: FLIP FLOP
 Design for JK FLIP FLOP

Historical Perspective ,
Design Hierarchy,
Concepts of Regularity,
Modularity and Locality
Unit-1 INTRODUCTION TO VLSI DESIGN
The electronics industry has achieved a phenomenal
growth..
mainly due to the rapid
advances in integration technologies

1. One of the most important characteristics of

information services is their increasing need for very
high processing power and bandwidth
2. The information services tend to become more and
more personalized.
The level of integration as measured by the number of
logic gates in a monolithic chip has been steadily
rising, mainly due to the rapid progress in

Processing Technology
and
Interconnect Technology.
 The monolithic integration of a large number of
functions on a single chip usually provides:

• Less area/volume and therefore, compactness

• Less power consumption
• Less testing requirements at system level
• Higher reliability, mainly due to improved on-chip
interconnects
• Higher speed, due to significantly reduced interconnection
length
• Significant cost savings
 A minimum size of 0.25 microns was readily achievable by the year
1995. As a direct result of this, the integration density has also
exceeded previous expectations - the first 64 Mbit DRAM, and the
INTEL Pentium microprocessor chip containing more than 3 million
transistors were already available by 1994, pushing the envelope of
integration density.

Memory circuits are highly regular and thus more cells can be
integrated with much less area for interconnects.
 For designing system.. System description is done by gajski
VLSI Design Flow
Gajski and Kuhn’s Y Chart Components
Architectural Structural
Behavioral
Algorithmic
Primary inputs and outputs Processor
Systems Functional Block
Hardware Modules
Algorithms Logic
ALUs, Registers
Register Transfer
Logic Circuit Gates, FFs
Transfer Functions Transistors

Rectangles

Cell, Module Plans

Floor Plans
Domains
Clusters
Structural – how the system is composed
Geometry – how the system is laid out in physical space Physical Partitions

Exact positions
Physical/Geometry
the connection
34
 describes the behavior of the target chip.

Architecture of the processor is first defined. It is mapped

onto the chip surface by floorplanning.

behavioral domain defines finite state machines (FSMs)

which are structurally implemented with functional modules.
such as registers and arithmetic logic units (ALUs).

Individual modules are then implemented with leaf cells.

goal of minimizing the interconnects area
and signal delays.

detailed Boolean description of leaf cells followed

by a transistor level implementation of leaf cells
and mask generation.
 HDL is for the specifications….

Synthesis: behavior to structure(realization

1. Manual
2. Automated
Driving Factor: Semiconductor technology

Key Parameter (Feature size)

1. Distance between two conduction lines

2. Size of the transistor

Driving Device : Memory

Design Matrix
1.Area is measure of cost
2.Power (interconnects)
3.Speed (reduction of feature size)
 Impact on cost
• Area is the measure of cost
• Minimizing logic is less important
• Interconnection area is very significant in
relation to logic area
• Pin count and testing becoming a significant
part of the manufacturing cost.
 Impact on Performance
• Speed mainly clock speed is synchronous-
systems is the measure of performance
• Interestingly speed increases automatically
with feature size reduction
• Interconnection delays are very significant
• At high speed, interconnects start behaving
Like transmission lines
 Impact on Power
• CMOS is the dominant technology
• Power is a major design matric along with
Area and delay..
• Low voltage operations
• Special Packaging and cooling technologies.
Classification: Design Methodologies

Processor Instruction set (intermediate)

ASICS Top Down

Memories Bottom Up
(linear cells)
Design levels

1.Transistor level
2.Gate level
3.RTL level
4.Algorithm/behavioral level
 Design Hierarchy

The use of hierarchy, or “divide and conquer” technique involves dividing a module
into sub- modules and then repeating this operation on the sub-modules until the
complexity of the smaller parts becomes manageable.

Concepts of Regularity & Modularity

• The hierarchical design approach reduces the design complexity by

dividing the large system into several sub-modules.
• Usually, other design concepts and design approaches are also
needed to simplify the process.
• Regularity means that the hierarchical decomposition of a large
system should result in not only simple, but also similar blocks, as
much as possible.

Ex: At the transistor level, uniformly sized transistors simplify the design.
At the logic level, identical gate structures can be used, etc
Modularity in design means that the various functional blocks which
make up the larger system must have well-defined functions and
interfaces

• The concept of modularity enables the parallelisation of the design

process.

• It also allows the use of generic modules in various designs the well
defined functionality and signal interface allow plug-and-play design.