M2:Combinational logic

Objectives:
Arithmetic circuits,BCD
adder,Decoders,Encoders,Mux and DMux
or C = XY + Z(X+Y)
Binary Adder
 Binary Subtractor
• The subtrcation A – B can be done by taking
the 2’s complement of B and adding it to A
because A- B = A + (-B)
• It means if we use the inveters to make 1’s
complement of B (connecting each Bi to an
inverter) and then add 1 to the least
significant bit (by setting carry C0 to 1) of
binary adder, then we can make a binary
subtractor.
4 bit 2’s complement Subtractor
 BCD Adder

Cin
4-bit Adder

z8 z4 z2 z1
0 0

4-bit Adder

K s8 s4 s2 s1
The addition of two n-digit unsigned BCD numbers follows the same
procedure. Consider the addition of 184 + 576 = 760 in BCD:

BCD 1 1
0001 1000 0100 184
+ 0101 0111 0110 +576
Binary sum 0111 10000 1010
Add 6 ____ 0110 0110 ____
BCD sum 0111 0110 0000 760

The first, least significant pair of BCD digits produces a BCD digit
sum of 0000 and a carry for the next pair of digits. The second pair of
BCD digits plus a previous carry produces a digit sum of 0110 and a
carry for the next pair of digits. The third pair of digits plus a carry
produces a binary sum of 0111 and does not require a correction.
 Magnitude Comparator
• It is a combinational circuit that compares to
numbers and determines their relative magnitude
• The output of comparator is usually 3 binary
variables indicating: A>B
A=B
A<B
• For example to design a comparator for 1 bit binary
numbers A and B we do the following steps:
 Truth table for 1 bit comparator
A B A>B A<B A=B
Expressions :
0 0 0 0 1 A>B: A.B’
0 1 0 1 0 A<B: A’.B
A=B: A’B’+AB = A xnor B
1 0 1 0 0
1 1 0 0 1

A
Circuits: A>B:
B

B
A<B:
A

A
A=B:
B
 2-BIT MAGNITUDE COMPARATOR
• Let A = A1A0 & B = B1B0 A1 A0 B1 B0 A>B A<B A=B
0 0 0 0 0 0 1
0 0 0 1 0 1 0
0 0 1 0 0 1 0
0 0 1 1 0 1 0
0 1 0 0 1 0 0
0 1 0 1 0 0 1
0 1 1 0 0 1 0
0 1 1 1 0 1 0
1 0 0 0 1 0 0
1 0 0 1 1 0 0
1 0 1 0 0 0 1
1 0 1 1 0 1 0
1 1 0 0 1 0 0
1 1 0 1 1 0 0
1 1 1 0 1 0 0
1 1 1 1 0 0 1
 Combinational Circuits: MSI Components
Useful MSI circuits
 Four common and useful MSI circuits are:
 Decoder
 Demultiplexer
 Encoder
 Multiplexer
 Block-level outlines of MSI circuits:
encoder
decoder entity code
code entity

data demux output

mux data
input

select
select Useful MSI circuits
 Codes are frequently used to represent entities, e.g. your
name is a code to denote yourself (an entity!).
 These codes can be identified (or decoded) using a
decoder. Given a code, identify the entity.
 Convert binary information from n input lines to (max. of)
2n output lines.
 Known as n-to-m-line decoder, or simply n:m or nm
decoder (m  2n).
 May be used to generate 2n (or fewer) minterms of n input
variables.
 Example: if codes 00, 01, 10, 11 are used to identify four
light bulbs, we may use a 2-bit decoder:
2x4
Dec F0 Bulb 0
2-bit X F1 Bulb 1
code Y F2 Bulb 2
F3 Bulb 3

 This is a 24 decoder which selects an output line based

on the 2-bit code supplied.
 Truth table:
X Y F0 F1 F2 F3
0 0 1 0 0 0
0 1 0 1 0 0
1 0 0 0 1 0
1 1 0 0 0 1
 Decoders: Implementing Functions
 Example: Full adder x y z C S
S(x, y, z) = S m(1,2,4,7) 0 0 0 0 0
0 0 1 0 1
C(x, y, z) = S m(3,5,6,7) 0 1 0 0 1
0 1 1 1 0
3x8 0
1 0 0 0 1
Dec 1 1 0 1 1 0
2 S 1 1 0 1 0
x
3 1 1 1 1 1
S2
4
S1 5
y
6
S0 7 C
z
 Larger Decoders
 Larger decoders can 3x8
Dec 0 F0 = w'x'y'
1 F1 = w'x'y
be constructed from w S2
: :
x S1
smaller ones. y S0
:
7
:
F7 = wxy
 For example, a 3-to-8
decoder can be
constructed from w
2x4
0 F0 = w'x'y'
Dec
two 2-to-4 decoders x S1 1 F1 = w'x'y
y 2
(with one-enable), as S0
3
F2 = w'xy'
F3 = w'xy
follows: E

2x4
Dec 0 F4 = wx'y'
S1 1 F5 = wx'y
S0 2 F6 = wxy'
3 F7 = wxy
E
 Larger Decoders (contd..) 3x8
Dec 0 F0 = w'x'y'
w S2 1 F1 = w'x'y
2x4 : :
x S1
Dec 0 1 : :
0 w F0 = w'x'y' y S0
1 0 7 F7 = wxy
0 x S1
2 0 F1 = w'x'y
0 y S0 F2 = w'xy'
3 0
E F3 = w'xy

2x4
Dec 0 0
S1 1 0 F4 = wx'y'
S0 2 0 F5 = wx'y
3 0 F6 = wxy'
E F7 = wxy
 4x16
 Construct a 4x16 w S3
Dec 0 F0
decoder from two 3x8 x S2
1 F1
decoders with 1- y S1
:
:
:
:
enable. z S0 15 F15
 74138 (3-to-8 decoder)
Standard MSI Decoders

3x8
Dec 0 F0
w
S2 1
x F1
y S1 : :
z S0 7 F7
E

3x8
Dec 0 F8
S2 1 F9
S1 : :
S0 7 F15
E
 Encoder
 Encoding is the converse of decoding.
 Given a set of input lines, where one has been selected,
provide a code corresponding to that line.
 Contains 2n (or fewer) input lines and n output lines.
 Implemented with OR gates.
 An example:

F0 D0
Select via F1 4-to-2
switches 2-bits
F2 Encoder D1 code
F3
 Multiplexer
 A multiplexer is a device which has
(i) a number of input lines
(ii) a number of selection lines
(iii) one output line
 It steers one of 2n inputs to a single output line, using n
selection lines. Also known as a data selector.

2n:1
inputs Multiplexer output
:

...

select
  Truth table for a 4-to-1 multiplexer:
Inputs
S1 S0 Y Inputs
I0
I0 0 0 0 I0
I1 4:1 I1
1
MUX 0 1 I1 I2 mux Y
I2 2 Y Output 1 0 I2 I3
I3 3
S1 S0 1 1 I3
S1 S0
select
select
 Output of multiplexer is
“sum of the (product of data lines and selection lines)”
 Example: the output of a 4-to-1 multiplexer is:
Y = I0.(S1'.S0') + I1.(S1'.S0) + I2.(S1.S0') + I3.(S1.S0)
 A 2n-to-1-line multiplexer, or simply 2n:1 MUX, is made from
n n
an n: 2 decoder by adding to it 2 input lines, one to each
AND gate.
 Four-to-one multiplexer design.

I0 I0

I1 I1
Y Y
I2 I2

I3 I3

0 1 2 3
2-to-4
Decoder

S1 S0 S1 S0
 Larger Multiplexers
 Larger multiplexers can be constructed from smaller ones.
 An 8-to-1 multiplexer can be constructed from smaller
multiplexers like this (note placement of selector lines):
I0
I1
4:1 MUX
I2
I3 S2 S1 S0 Y
0 0 0 I0
2:1 MUX 0 0 1 I1
S1 S0 Y
0 1 0 I2
I4 0 1 1 I3
I5 1 0 0 I4
4:1 MUX
I6 1 0 1 I5
I7 S2 1 1 0 I6
1 1 1 I7

S1 S0
 Another implementation of an 8-to-1 multiplexer using
smaller multiplexers:

When
I0 2:1 I0 S2S1S0 = 000 S2 S1 S0 Y
I1 MUX 0 0 0 I0
0 0 1 I1
I2 2:1 I2 S0 0 1 0 I2
MUX 0 1 1 I3
I3
1 0 0 I4
4:1 I0
S0 1 0 1 I5
MUX 1 1 0 I6
I4 2:1 I4 1 1 1 I7
I5 MUX
S2 S1
S0 I 2:1
6

I7 MUX I6

S0
 Larger Multiplexers(contd..)
When
I0
S2S1S0 = 110 S2 S1 S0 Y
I1 4:1 I2
I2 MUX 0 0 0 I0
0 0 1 I1
I3
2:1 I6 0 1 0 I2
S1 S0 MUX Y 0 1 1 I3
I4 1 0 0 I4
I5 4:1 1 0 1 I5
I6 MUX I6 S2
1 1 0 I6
I7 1 1 1 I7

S1 S0
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