BCS302 : DIGITAL DESIGN AND

COMPUTER ORGANIZATION

Module 1

1
 Module 1: Introduction to Digital Design
Chapter 1 : Digital Systems and Binary Numbers
1.9 : Binary Logic

Chapter 2: Boolean Algebra and Logic Gates

4. Basic Theorems and Properties of Boolean
Algebra
5. Boolean Functions
2.8 Digital Logic Gates

Chapter 3: Gate-Level Minimization

6. Introduction
7. The Map Method
8. Four-Variable K-Map
5. Don’t-Care Conditions
6. NAND and NOR Implementation
3.9 Hardware Description Languages (HDLS)

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 Module 2: Combinational Logic
Chapter 4 : Combinational Logic
1. Introduction
2. Combinational Circuits
4. Design Procedure
5. Binary Adder–Subtractor
9. Decoders
10. Encoders
11. Multiplexers
12. HDL Models of Combinational Circuits
Chapter 5: Synchronous Sequential Logic
13. Introduction
14. Sequential Circuits
15. Storage Elements: Latches
16. Storage Elements: Flip-Flops

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 Chapter 1 : Digital Systems and Binary Numbers
1.9 BINARY LOGIC
 Binary logic deals with variables that take on two discrete values and with operations that assume
logical meaning.
 The two values the variables assume may be called by different names (true and false, yes and
no, etc.), but for our purpose, it is convenient to think in terms of bits and assign the values 1 and
0.
 The binary logic introduced in this section is equivalent to an algebra called Boolean algebra.
Definition of Binary Logic
 Binary logic consists of binary variables and a set of logical operations.
 The variables are designated by letters of the alphabet, such as A, B, C, x, y, z, etc., with each
variable having two and only two distinct possible values: 1 and 0.
 There are three basic logical operations: AND, OR, and NOT.
 Each operation produces a binary result, denoted by z. 4
Gates:
“A digital circuit having one or more input signals but only one
output signal is called a gate”.
Logic Gates:
“The gates which perform logical operation is called logic gates”.
•It take binary input and gives binary outputs.
•The output of the logic gates can be understood using truth
table, which contains inputs, outputs of logic circuits.
Basic Gates[NOT,OR,AND] NOT Gate[ The Inverter]:
A Y A Y
L H
H L

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7404 IC CHIP(NOT) [Extra]

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 AND Gate(7408)
• The AND gate is a logic circuit that has two or more inputs and a single
output
• The operation of the gate is such that the output of the gate is a binary 1 if
and only if all inputs are binary 1
• Similarly, if any one or more inputs are binary 0, the output will be binary 0.

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OR Gate(7432)
•The OR gate is another basic logic gate
•Like the AND gate, it can have two or more inputs and a single output
•The operation of OR gate is such that the output is a binary 1 if any one
or all inputs are binary 1 and the output is binary 0 only when all the
inputs are binary 0

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 Timing Diagram

t0 t1 t2 t3 t4 t5 t6
1
Input A 0
1 Transition
signal B 0
s s
1
F=A•B 1 Basic
Gate
2 Assumption:
Outpu G=A+B 3 Zero time for
t
4 signals to
Signal H=
s
0 propagate
A’
Through
gates
9
More input to AND and OR Gate

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EX-OR and EX-NOR Gates [Extra]
•EX-OR andEX-NOR are digital logic circuits that may use twoor
more inputs.
•EX-NOR gate returns the output opposite to EX-OR gate.
•EX-OR andEX-NOR gates are also denotedby XOR and
XNOR respectively.

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 EXOR Gate(7486)
[Extra]
•The Ex-OR (Exclusive- OR) gate returns high output with one of two high inputs (but not with
both high inputs or both low inputs)
• For example, if both the inputs are binary 0 or 1, it will return the output as 0. Similarly, if
one input is binary 1 and another is binary 0, the output will be 1 (high)
• The operation for the Ex-OR gate is denoted by encircled plus symbol
• The Ex-OR operation is widely used in digital circuits.
• The algebraic output expression of the Ex-OR gate is Y = A ⊕ B=
=

(A+B)(A’B’)=A’B+AB’

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 EXNOR Gate [Extra]
• The Ex-NOR (Exclusive- NOR) gate is a circuit that returns low output with one of two
high inputs (but not with both high inputs)
• For example, if both the inputs are binary 0 or 1, it will return the output as 1. Similarly, if
one
input is binary 1 and another is binary 0, the output will be 0 (low)
• The symbol for the Ex-NOR gate is denoted by encircled plus symbol which inverts the
binary values
• The algebraic output expression of the Ex-NOR gate is Y =

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 Universal Gate:[NAND, NOR] [Reference to Chapter 3]
NAND Gate(7400)
• The term NAND is a contraction of the expression NOT-AND
gate
• A NAND gate, is an AND gate followed by an inverter
• The algebraic output expression of the NAND gate is Y = (A.B)’

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NOR Gate(7402)
• The term NOR is a contradiction of the expression NOT-OR
• A NOR gate, is an OR gate followed by an inverter
• The algebraic output expression of the NOR gate is Y = (A +
B)’

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Applications of Logic Gates
• The following are some of the applications of Logic gates:
• Build complex systems that can be used to different fields such as
• Genetic engineering,
• Nanotechnology,
• Industrial Fermentation,
• Metabolic engineering and
• Medicine
• Construct multiplexers, adders and multipliers.
• Perform several parallel logical operations
• Used for a simple house alarm or fire alarm or in the circuit of automated
machine manufacturing industry

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 Assisgnment
1. Write truth table for y=A’B’ and logic circuit for two input variable
A&B?
2. Write truth table and logic circuit for y=AB’+A’B?
3. Write truth table and logic circuit for y=(A+B)+(C+D)?
4. Write logic circuit for y=A’BC+AB’C?

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Example of Truth table[Extra] Demorgans law

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 Chapter 2: Boolean Algebra and Logic Gates

4. Basic Theorems and Properties of Boolean Algebra

5. Boolean Functions
2.8 Digital Logic Gates

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2.4 Basic Theorems and Properties of Boolean Algebra

Boolean algebra is an algebraic structure defined by a set of elements, B, together with two binary operators, + and ⋅ , provided that
2.3 AXIOMATIC DEFINITION OF BOOLEAN ALGEBRA [Extra]

the following (Huntington) postulates are satisfied:

1.
 The structure is closed with respect to the operator + .
 The structure is closed with respect to the operator .
2.
 The element 0 is an identity element with respect to + ; that is, x + 0 = 0 + x = x .
 The element 1 is an identity element with respect to ⋅ ; that is, x ⋅ 1 = 1 ⋅ x = x .
3.
 The structure is commutative with respect to + ; that is, x + y = y+ x .
The structure is commutative with respect to ⋅ ; that is, x ⋅ y = y⋅ x .

 The operator ⋅ is distributive over + ; that is, x ⋅ ( y + z ) = ( x ⋅ y )

4.

+(x⋅ z).
 The operator + is distributive over ⋅ ; that is, x + ( y ⋅ z ) = ( x + y )
⋅ (x+z).
5. For every element x ∈ B , there exists an element x ′ ∈ B (called the
complement of x) such that (a) x + x ′ = 1 and (b) x ⋅ x ′ = 0.
6. There exist at least two elements x , y ∈ B such that x ≠ y . 20
Comparing Boolean algebra with arithmetic and ordinary algebra (the field of real numbers), we note the
following differences:
1.Huntington postulates do not include the associative law. However, this law holds for Boolean algebra and can be
derived (for both operators) from the other postulates.

2.The distributive law of + over ⋅ (i.e., x + ( y ⋅ z ) = ( x + y ) ⋅ ( x + z ) ) is valid for Boolean algebra, but not
for ordinary algebra.

3.Boolean algebra does not have additive or multiplicative inverses; therefore, there are no subtraction or division
operations.

4. Postulate 5 defines an operator called the complement that is not available in ordinary algebra.

5.Ordinary algebra deals with the real numbers, which constitute an infinite set of elements. Boolean algebra deals
with the as yet undefined set of elements, B, but in the two-valued Boolean algebra defined next (and of interest in our
subsequent use of that algebra), B is defined as a set with only two elements, 0 and 1.

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2.4 BASIC THEOREMS AND PROPERTIES OF BOOLEAN ALGEBRA

Duality:
 The Huntington postulates were listed in pairs and designated by part (a) and part (b).

 One part may be obtained from the other if the binary operators and the identity elements are interchanged.

 This important property of Boolean algebra is called the duality principle and states that every algebraic
expression deducible from the postulates of Boolean algebra remains valid if the operators and identity
elements are interchanged.
 The duality principle has many applications.

 If the dual of an algebraic expression is desired, we simply interchange OR and AND operators and replace 1’s
by 0’s and 0’s by 1’s.

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Basic Theorems
Table 2.1 lists six theorems of Boolean algebra and four of its postulates.

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24
THEOREM 1(a): x + x = x

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THEOREM 1(b): x ⋅ x =
x

 Note that theorem 1(b) is the dual of theorem 1(a) and that each step of the proof in part (b) is the dual of
its counterpart in part (a).
 Any dual theorem can be similarly derived from the proof of its corresponding theorem.

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THEOREM 2(a): x + 1 = 1.

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THEOREM 2(b): x ⋅ 0 =
0Home Work:

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THEOREM 3: ( x ′ ) ′ = x

Step1: From postulate 5, we have x + x ′ = 1 and x ⋅ x ′ = 0 , which together define the complement of x.

Step2 : The complement of x ′ is x and is also ( x ′ ) ′ . Therefore, since the complement is unique, we
have

(x′)′=x.
Step3: The theorems involving two or three variables may be proven algebraically from the postulates and the
theorems that have already been proven.

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THEOREM 6(a): x + x y = x . [Absorption Theorem]

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THEOREM 6(b): x ( x + y ) = x

Home Work :

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 The theorems of Boolean algebra can be proven by means of truth tables.

 In truth tables, both sides of the relation are checked to see whether they yield identical results for
all possible combinations of the variables involved.
 The following truth table verifies the first absorption theorem:

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The truth table for the first DeMorgan’s theorem, ( x + y ) ′ = x ′ y ′ , is as follows:

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Operator Precedence
 The operator precedence for evaluating Boolean expressions is

(1) parentheses,

(2) NOT,

(3) AND, and

(4) OR.
 In other words, expressions inside parentheses must be evaluated before all other operations. The next
operation that holds precedence is the complement, and then follows the AND and, finally, the OR.
 As an example, consider the truth table for one of DeMorgan’s theorems. ( x + y ) ′ = x ′ y ′

 The left side of the expression is ( x + y ) ′ . Therefore, the expression inside the parentheses is evaluated
first and the result then complemented.
 The right side of the expression is x ′ y ′ , so the complement of x and the complement of y are
both
evaluated first and the result is then ANDed.
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Practice Exercise [ Home work]

1. Using the basic theorems and postulates of Boolean algebra, simplify the following
Boolean
expression: F = x ′ y ′ z + x y z + x ′ y z + x y ′ z .

Answer: F = z (Step wise shows the answer)

2. Develop a truth table for the Boolean expression F = x ′ y ′ z .

Answer : solve using table construction

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 2.5 BOOLEAN FUNCTIONS
 Boolean algebra is an algebra that deals with binary variables and logic operations.

 A Boolean function described by an algebraic expression consists of binary variables, the constants 0 and 1, and
the logic operation symbols.
 For a given value of the binary variables, the function can be equal to either 1 or 0.
EX: consider the Boolean function F 1 = x + y ′ z
 The function F 1 is equal to 1 if x is equal to 1 or if both y ′ and z are equal to 1. F 1 is equal to 0 otherwise.
 A Boolean function can be represented in a truth table.
 The number of rows in the truth table is 2^n , where n is the number of variables in the function.
 The binary combinations for the truth table are obtained from the binary numbers by counting from 0 through 2^n −
1.
 Below Table shows the truth table for the function F 1 .
 There are eight possible binary combinations for assigning bits to the three variables x, y, and z.
 The column labeled F 1 contains either 0 or 1 for each of these combinations.

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Truth table F 1 = x + y ′ z
 A Boolean function can be transformed from an algebraic expression into a circuit diagram composed of logic
gates connected in a particular structure.
 The logic-circuit diagram (also called a schematic) for F 1 is shown in below figure .

X Y Z F1 F2
0 0 0 0 0
0 0 1 1 1
0 1 0 0 0
0 1 1 0 1
1 0 0 1 1
1 0 1 1 1
1 1 0 1 0
1 1 1 1 0

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 By manipulating a Boolean expression according to the rules of Boolean algebra, it is sometimes possible to
obtain a simpler expression for the same function and thus reduce the number of gates in the circuit and the
number of inputs to the gate.
 Designers are motivated to reduce the complexity and number of gates because their effort can significantly
reduce the cost of a circuit, fig 2a shows complex circuit and fig 2b shows reduced circuit.
 Consider, for example, the following Boolean function and see the truth table F2 function.

 F2=x′y′z+x′yz+xy′

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Now consider the possible simplification of the function by applying some of the identities of Boolean
algebra:

F2=x′y′z+x′yz+xy′

F2 =x′z(y′+y)+xy′

F2 =x′z+xy′
 The function is reduced to only two terms and can be implemented with gates as shown in Fig. 2.2(b) .

 It is obvious that the circuit in (b) is simpler than the one in (a), yet both implement the same function.

 Using truth table, it is possible to verify that the two expressions are equivalent.
 In general, there are many equivalent representations of a logic function.
 Finding the most economic representation of the logic is an important design task.

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Problems : Simplify the Boolean Expression.(H.W)

1. x ( x ′ + y )

2. x + x ′ y

3. (x + y ) ( x + y ′)

4. x y + x ′ z + y z

5. ( x + y ) ( x ′ + z ) ( y +
z)

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Problems : Simplify the Boolean Expression.(H.W with Answer )

1. x ( x ′ + y ) = x x ′ + x y = 0 + x y = x y.

2. x + x ′ y = ( x + x ′ ) ( x + y ) = 1 ( x + y ) = x +y.

3. ( x + y ) ( x + y ′ ) = x + x y + x y ′ + y y ′ = x ( 1 + y + y ′ ) = x.

4. x y + x ′ z + y z = x y + x ′ z + y z ( x + x ′ ) = x y+ x ′ z + x y z + x ′ y z = x y ( 1 + z ) + x ′ z ( 1
+y )
=x y+x′z.

5. ( x + y ) ( x ′ + z ) ( y + z ) = (y+xz)(x ′ +z )
= x ′y+yz+xz x ′+xz
= x ′ y+yz+xz
= x ′ y+x x ′+ yz+xz
= x ′ (y+x)+z(y+x)
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=( x + y ) ( x ′ + z )
 Complement of a Function

 The complement of a function F is F ′ and is obtained from an interchange of 0’s for 1’s and 1’s for 0’s in the
value of F.
 The complement of a function may be derived algebraically through DeMorgan’s theorems, listed in Table
2.1 for two variables. (Refer Basic Theorem topic ,slide no 24)
 DeMorgan’s theorems can be extended to three or more variables.

The three-variable form of the first DeMorgan’s theorem is derived as follows, from postulates and theorems

listed in Table 2.1 :

(A + B + C ) ′ = ( A + x ) ′ let B + C = x
= A ′ x ′ by theorem 5 ( a ) ( DeMorgan )
= A ′ ( B + C ) ′ substitute B + C = x
= A ′ ( B ′ C ′ ) by theorem 5 ( a ) ( DeMorgan )
= A ′ B ′ C ′ by theorem 4 ( b ) (associative )

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 DeMorgan’s theorems for any number of variables resemble the two variable case in form and can be derived
by successive substitutions similar to the method used in the preceding derivation.

These theorems can be generalized as follows:

( A+ B + C + D + … + F) ′ =A′ B ′ C ′ D ′ … F ′

( AB CD… F ) ′=A′+B ′+C′ +D′+… +F

′
 The generalized form of DeMorgan’s theorems states that the complement of a function is obtained by
interchanging AND and OR operators and complementing each literal.

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Problems:
1.Find the complement of the functions a) F 1 = x ′ y z ′ + x ′ y ′ z and b) F 2 = x (y ′ z ′ + y z ) using both
methods.
2. Draw a logic diagram for the Boolean function F = x ′ y + x y ′ .
3. What Boolean expression is implemented by the following logic diagram and also write the truth table.
4. Find the complement of the Boolean function F = A ′ B C ′ + A ′ B ′ C .

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Problems:
1. Find the complement of the functions a) F 1 = x ′ y z ′ + x ′ y ′ z and b) F 2 = x (y ′ z ′ + y z ) .

Method1: By applying DeMorgan’s theorems as many times as necessary, the complements are obtained as
follows:
a) F 1 ′ = ( x ′ y z ′ + x ′ y ′ z ) ′
=(x′yz′)′(x′y′z)′
= ( x + y′ + z ) ( x + y + z ′ )

b) F 2 ′ = [ x ( y ′ z ′ + y z ) ] ′
=x′+(y′z′+yz)′
=x′+(y′z′)′(y
z)′
= x′ + ( y + z ) ( y ′ + z
′)
= x ′ + y z ′ +y ′ z
 A simpler procedure for deriving the complement of a function is to take the dual of the function and
complement each literal.
 This method follows from the generalized forms of DeMorgan’s theorems.
 Remember that the dual of a function is obtained from the interchange of AND and OR operators and 1’s45and
Find the complement of the functions F 1 and F 2 by taking their duals and complementing each literal.

1. F 1 = x ′ y z ′ + x ′ y ′

z . Answer: Method 2:

Step1:The dual of F 1 is
(x′+y+z′)(x′+y′+
z)

Step2: Complement each

literal: ( x + y ′ + z ) ( x +
y+z′)=F1′

2. F 2 = x ( y ′ z ′ + y z ) .
Answer:
Step1: The dual of F 2 is
x+(y′+z′)(y+z).

Step2: Complement each

literal: x ′ + ( y + z ) ( y ′
46
+z′)=F2′
2. Draw a logic diagram for the Boolean function F = x ′ y + x y ′ .
The diagram has the following paths. First path: input x, first and gate. Second path: input y, inverter, first and
gate. Third path: first and gate, output x prime y, or gate. Fourth path: x, inverter, second and gate. Fifth path: y,
second and gate. Sixth path: second and gate, output x y prime, or gate. The or gate yields output F.

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3. What Boolean expression is implemented by the following logic diagram and also write the truth table.

F=(x′y+xy′)′
X Y F
=(x′y)′(xy′)′
0 0 1
=(x+y′)(x′+y)
0 1 0
=xx′+xy+y′x′+yy′
=xy+x′y′ 1 0 0
1 1 1

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4. Find the complement of the Boolean function F = A ′ B C ′ + A ′ B ′ C .

Answer: F′ = (A ′ B C ′ + A ′ B ′ C )
′
= (A ′ B C ′) ′ . (A ′ B ′ C ) ′
=( A+B ′ +C). (A+B+C +B ′C ′+CA+CB+ CC ′
′) A+AB+AC ′+B ′A+ B ′C ′+CA+CB
=
F ′ ==AA+AB+AC
A + B C + B ′ C ′+B
′ ′A+
BB ′

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2.8 DIGITAL LOGIC GATES
 Since Boolean functions are expressed in terms of AND, OR, and NOT operations, it is easier to implement a
Boolean function with these type of gates.
 Factors to be weighed in considering the construction of other types of logic gates are

(1) the feasibility and economy of producing the gate with physical components,

(2) The possibility of extending the gate to more than two inputs,

(3) the basic properties of the binary operator, such as commutativity and associativity, and

(4) the ability of the gate to implement Boolean functions alone or in conjunction with other gates.

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51
52
 The graphic symbols and truth tables of the eight gates are shown in above Fig.

 Each gate has one or two binary input variables, designated by x and y, and one binary output variable,
designated by F.
 The inverter circuit inverts the logic sense of a binary variable, producing the NOT, or complement, function.

 The small circle in the output of the graphic symbol of an inverter (referred to as a bubble) designates the
logic complement.
 The triangle symbol by itself designates a buffer circuit.

 A buffer produces the transfer function, but does not produce a logic operation, since the binary value of the
output is equal to the binary value of the input.
 This circuit is used for power amplification of the signal and is equivalent to two inverters connected in
cascade.

Note:1. The symbol 𝖠 is also used to indicate the exclusive-OR operator, e.g., x 𝖠 y .
2. We are using operator ( ↓ ) , to represent NOR ( x + y ) ′ = x ↓ y =NOR= Not-OR
3. We are using operator (↑) , to represent NAND ( x y ) ′= x ↑ y = NAND= Not-AND
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Extension to Multiple Inputs
 The gates shown in above Fig. except for the inverter and buffer—can be extended to have more than
two inputs.
 A gate can be extended to have multiple inputs if the binary operation it represents is commutative
and associative.
 The AND and OR operations, defined in Boolean algebra, possess these two properties.

 For the OR function, we have x + y = y + x ( commutative )

 ( x + y ) + z = x + ( y + z ) = x + y + z ( associative ) , which indicates that the gate inputs can

be interchanged and that the OR function can be extended to three or more variables.
 The NAND and NOR functions are commutative, and their gates can be extended to have more than two
inputs, provided that the definition of the operation is modified slightly.
The difficulty is that the NAND and NOR operators are not associative (i.e., ( x ↓ y ) ↓ z ≠ x ↓ ( y ↓ z ) ), as

shown in below Fig. and the following equations:

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Demonstrating the non-associativity of the NOR operator: ( x ↓y ) ↓ z ≠ x ↓ ( y ↓
z)

(x↓y)↓z=[(x+y)′+z]′
=(x+y)z′
=xz′+yz′
x ↓ ( y↓ z ) = [ x + ( y + z ) ′ ] ′
=x′(y+z)
=x′y+x′z
To overcome this difficulty, we define the multiple NOR (or NAND) gate as a complemented OR (or AND) gate.
Thus, by definition, we have a) x ↓ y ↓ z = ( x + y + z ) ′
b) x ↑ y ↑ z = ( x y z ) ′

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The graphic symbols for the three-input gates are shown in Fig.

In writing cascaded NOR and NAND operations, one must use the correct parentheses to signify the proper sequence
of the gates. To demonstrate this principle, consider the circuit of Fig. (c) .

The Boolean function for the circuit must be written as F = [ ( A B C ) ′ ( D E ) ′ ] ′ = A B C + D E

The second expression is obtained from one of DeMorgan’s theorems. It also shows that an expression in sum-of-
products form can be implemented with NAND gates.

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 Three-Input Exclusive-OR function
 The construction of a three-input exclusive-OR function is shown in below
Fig .

 This function is normally implemented by cascading two-input gates, as shown in (a).

 Graphically, it can be represented with a single three-input gate, as shown in (b).

 The truth table in (c) clearly indicates that the output F is equal to 1 if only one input is equal to 1 or if all
three
inputs are equal to 1 (i.e., when the total number of 1’s in the input variables is odd).

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 Positive and Negative Logic
 The binary signal at the inputs and outputs of any gate has one of two values, except during transition.

 One signal value represents logic 1 and the other logic 0.

Since two signal values are assigned to two logic values, there exist two different assignments of signal level to

logic value, as shown in Fig. 2.9 .

 The higher signal level is designated by H and the lower signal level by L.

 Choosing the high-level H to represent logic 1 defines a Positive logic

system.
 Choosing the low-level L to represent logic 1 defines a Negative logic
system.
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 Hardware digital gates are defined in terms of signal values such as H and L.

 It is up to the user to decide on a positive or negative logic polarity.

 Consider, for example, the electronic gate shown in Fig. 2.10(b) .

 The truth table for this gate is listed in Fig. 2.10(a) .

 It specifies the physical behavior of the gate when H is 3 V and L is 0 V.

 The truth table of Fig. 2.10(c) assumes a positive logic assignment, with H = 1 and L = 0.

 This truth table is the same as the one for the AND operation.

 The graphic symbol for a positive logic AND gate is shown in Fig. 2.10(d) .

 Now consider the negative logic assignment for the same physical gate with L = 1 and H = 0. The result is the
truth
table of Fig. 2.10(e) . table represents the OR operation, even though the entries are reversed.
 The graphic symbol for the negative-logic OR gate is shown in Fig. 2.10(f) .

 The small triangles in the inputs and output designate a polarity indicator, the presence of which along a terminal

signifies that negative logic is assumed for the signal.

 Thus, the same physical gate can operate either as a positive-logic AND gate or as a negative-logic OR gate. 59
 The conversion from positive logic to negative logic and vice versa is essentially an operation that changes 1’s to 0’s
and 0’s to 1’s in both the inputs and the output of a gate.

Since this operation produces the dual of a function, the change of all terminals from one polarity to the other results
in taking the dual of the function. The upshot is that all AND operations are converted to OR operations (or
graphic symbols) and vice versa.

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 Positive and Negative Logic
+ve logic {0=low, 1=high}
-ve logic {1=low,0=high}
1.Positive OR Negative AND
2.Positive Negative OR
3.Positive NANDNegative NOR(Home Work)
AND
4.Positive NOR Negative NAND (Home work)
1. Positive ORNegative AND
“An OR gates in a +Ve logic system
becomes an AND gates in a –Ve logic
system” X(+VE) Y(+VE) Z(+VE OR) X (-VE) Y(-VE) Z(-VE AND)
show in below
0 table.
0 0 1 1 1
0 1 1 1 0 0
1 0 1 0 1 0
1 1 1 0 0 0

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2. Positive AND Negative OR

X(+VE) Y(+VE) Z(+VE AND) X (-VE) Y(-VE) Z(-VE OR)

0 0 0 1 1 1
0 1 0 1 0 1
1 0 0 0 1 1
1 1 1 0 0 0
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Positive NAND Negative NOR

X(+VE) Y(+VE) Z(+VE NAND) X(-VE) Y(-VE) Z(-VE NOR)

0 0 1 1 1 0
0 1 1 1 0 0
1 0 1 0 1 0
1 1 0 0 0 1

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4. Positive NOR Negative NAND (Home work)

X(+ve) Y(+Ve) Z(+ve NOR) X(-ve) Y(-ve) Z(-ve NAND)

0 0 1 1 1 0
0 1 0 1 0 1
1 0 0 0 1 1
1 1 0 0 0 1

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1. Draw the logic diagram corresponding to the following Boolean expression without simplifying it:
F=D+BC+(D+C′)(A′+C).

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2. Implement the Boolean function F = x z + x ′ z ′ + x ′ y with
(a)AND, OR and Inverter gate
(b) OR and Inverter Gate
( c ) AND and Inverter
(d )NAND and inverter
gates, and
(e) NOR and inverter
gates. [ write logic
circuits ]

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Problems (H.W)
1. Demonstrate the validity of the following identities by means of truth tables:
a) DeMorgan’s theorem for three variables: ( x + y + z ) ′ = x ′ y ′ z ′ and ( xyz ) ′ = x ′ + y ′ + z ′
b) The distributive law: x + yz = ( x + y ) ( x + z )
c) The distributive law: x ( y + z ) = xy + xz
d) The associative law: x + ( y + z ) = ( x + y ) + z
e) The associative law: x ( yz ) = ( xy ) z
2. Write Boolean expressions and construct the truth tables describing the outputs of the circuits described by
the logic diagrams shown below

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3. Draw the logic diagram corresponding to the following Boolean expressions without simplifying
them:
1. B C ′ + A B C + A C D + B D
2. ( A + B ) ( C + D ) ( A ′ + B + D )
3. ( A B + A ′ B ′ ) ( C D ′ + C ′ D )
4. A + C D + ( A + D ′ ) ( B ′ + D )

5.Implement the Boolean function F = yz + z ′ y ′ + x ′ z

a)With AND, OR, and inverter gates.
b) *With OR and inverter gates.
c) With AND and inverter gates.
d) With NAND and inverter gates.
e) With NOR and inverter gates.

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THANK YOU

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