Small-Signal Amplifiers

E2002 Analog Electronics

Prof. Zheng Yuanjin
Email: [email protected]
Office: S2.2-B2-46
Tel: 65927764

1
 Module Goals

Understanding of concepts related to:

• Biasing of Transistors (BJT and MOSFET)
• dc and ac equivalent circuits for small-signal amplifier
• Small-signal models of BJT and MOSFET
• Amplifier characteristics such as voltage gain, input and output
resistances
• Analysis of three broad classes of single-stage amplifiers
- Inverting amplifiers – common-emitter and common-source
configurations
- Followers – common-collector and common-drain configurations
- Noninverting amplifiers – common-base and common-gate
configurations

2
 References

Text Book
1. Richard C. Jaeger and Travis N. Blalock,
“Microelectronic Circuit Design”, 4th Edition, McGraw
Hill, 2011, Chapters 4, 5, 13 and 14.

References
1. Allan R. Hambley, “Electronics”, 2nd Edition, Prentice
Hall, 2000
2. Donald A. Neamen, “Electronic Circuit Analysis and
Design”, 2nd Edition, McGraw-Hill, 2002

3
 MOSFET Regions of Operation
4.0 mA
Pinch-off locus
vDS = vGS – VTN or vGD = VTN

Triode VGS = 4.5 V

3.0 mA
iD Region
Drain current, iD

vDS < vGS – VTN

D VGS = 4.0 V
G or vGD > VTN
+ Saturation region
vDS 2.0 mA
-
+
vGS S vDS  vGS – VTN or vGD  VTN
- VGS = 3.5 V

1.0 mA VGS = 3.0 V

VTN : Threshold Voltage VGS = 2.5 V
of NMOS VGS = 2.0 V
Cutoff, ID = 0 vGS  VTN
0A
0V 2V 4V 6V 8V 10 V 12 V
Drain-source voltage, vDS

19 4
MOSFET Biasing for Different Regions
of Operation
In EE2002, only enhancement mode MOSFET is considered.
Region NMOS PMOS

VGS < VTN |VGS| < |VTP|

Cutoff
ID = 0 ID = 0
VDS < VGS – VTN |VDS| < |VGS| – |VTP|
Triode  V   V 
I D  K n  VGS  VTN  DS  VDS I D  K p  VGS  VTP  DS  VDS
 2   2 

VDS  VGS – VTN |VDS|  |VGS| – |VTP|

Saturation Kn Kp
VGS  VTN  V 
2 2
ID  ID  GS  VTP
2 2

W  W  5
K n n Cox   and K p  p Cox  
 L  L
 MOSFET Bias Analysis Approach
• Assume saturation region (unless operation region is
obvious)
• Use circuit analysis to find VGS
• Use VGS to calculate ID, and ID to find VDS
• Check validity of operation region assumption
• Change assumption and analyze again if required.

NOTE: An enhancement-mode MOSFET with VDS = VGS is

always in saturation because |VDS | always greater than (|
VGS|-|VTX|), where X is N or P for threshold voltage of
NMOS or PMOS, respectively.
6
 MOSFET Bias Analysis: Triode Region
Kn 250
VGS  VTN   4  1 1.13 mA
2 2
RD 1.6 kW ID 
2 2
ID
+ +
IG = 0
VDS-
4V
-
VDD VDD = ID RD + VDS
+
VGS VDS = 4 – 1.6 × 1.13 = 2.19 V
-
But VDS = 2.19 < VGS - VTN = 4 – 1 = 3,
Saturation region assumption is incorrect.
Kn = 250 mA/V2 V 

VTN = 1 V Using triode region equation, I D K n  VGS  VTN  DS  VDS
 2 
VDS = 4 – 1600 × 250m (4 – 1 – VDS/2)VDS
Assume transistor is
VDS = 2.3 V and ID = 1.06 mA
saturated,
VGS = VDD = 4 V. VDS = 2.3 < VGS - VTN = 3, transistor is in triode region.

7
 MOSFET Bias Analysis: nMOS Two-
Resistor Biasing
RD 10 kW
VDS = VDD – ID RD
RG
260 
VGS  1 10000 3.3  1.3 VGS  1
2 2
2 MW ID 3.3V + VDD VGS 3.3 
+ - 2
VDS-
IG = 0 +
VGS
1.3VGS2  1.6VGS  2 0
-
1.6  1.6 2  4 1.3  2
VGS 
2 1.3
Kn = 260 mA/V2 VGS  0.77 V or 2 V
VTN = 1 V
VGS = –0.77 V implies MOSFET is cutoff and
Since IG = 0, VDS = VGS contradict the observation.
Transistor is saturated VGS = 2 V and VDS = VGS = 2 V.
ID = 130m ×(2 – 1)2 = 130 mA.

8
 MOSFET Bias Analysis: pMOS Two-
Resistor Biasing
VSG+ + VSD = VDD – ID RD
- VSD-
50 
 VGS  VTP  220k 15  5.5  VGS  2 
IG = 0 2 2
ID
VGS 15 
RG
15V
+ VDD 2
-
2
470 kW 5.5 VGS  10 VGS  11 0
RD 220 kW
10  10 2  4 5.5  11
VGS 
2 5.5
VGS 0.37 V or 3.45 V
Kp = 50 mA/V2
VTP = -2 V Since |VGS| = 0.37 V < |VTP| = 2 V,
|VGS| = 3.45 V or VSG = 3.45 V
Since IG = 0, VSD = VSG ID = 25m ×(3.45 – 2)2 = 52.5 mA
Transistor is saturated VSD = VSG = 3.45 V

9
 Introduction to Amplifiers
• BJT is an excellent amplifier when biased in forward-active region
• MOSFET can be used as amplifier when biased in saturation region.
• In these regions, transistors can provide high voltage, current and power
gains.
• Bias refers to setting the ‘quiescent’ (idle) current when there is no signal
presence. It sets the transistor in the desired operation region.
• Q-point (determined by DC analysis) also determines
– Small-signal parameters of transistor
– Voltage gain, input resistance, output resistance
– Maximum input and output signal amplitudes
– Power consumption
– Efficiency (o/p signal power vs DC i/p power)

10
 Biasing MOSFET for linear amplification
MOSFET is biased in saturation region
S (corresponding to the forward-active of BJT)
ID1 G 6V +
M2 VCC for small-signal amplifier.
D D -
G ID2
M1 4V +
+ S - pMOS behaves like nMOS with all the
2V - polarities reversed.
pMOS nMOS

VGS
nMOS pMOS VGS

K Kp VDSAT 0 VDSAT
I D  n VGS  VTN   VGS  VTP 
2 2
ID  VTP VTN
2 2
with channel length modulation: with channel length modulation:
VSAT  VGS  VTX  0
K K
I D  n VGS  VTN  1  VDS  I D  p  VGS  VTP  1   VDS 
2 2

2 2 X  N or P

11
 MOSFET Amplifier
10V

RD 3.3kW

iD
+
vDS-
+
+ vGS
0.5sinwt V vgs -
-

+
dc biasing 3.5V -
VGS

Q-point is set at (ID, VDS) = (1.56 mA, 4.8 V) with VGS =3.5 V.
Total gate-source voltage is: vGS = VGS +vgs
1 V p-p change in vGS  1.25 mA p-p change in iD  4 V p-p change in vDS.

3 12
 DC and AC Analysis
• DC analysis:
– Obtain dc equivalent circuit by replacing all capacitors by open circuits
and inductors by short circuits. ac voltage sources by ground
connections and ac current sources by open circuits.
– Find Q-point from dc equivalent circuit by using appropriate large-
signal transistor model.
• AC analysis:
– Obtain ac equivalent circuit by replacing all capacitors by short circuits,
inductors by open circuits, dc voltage sources by ground connections
and dc current sources by open circuits.
– Replace transistor by small-signal model
– Use small-signal ac equivalent to analyze ac characteristics of amplifier.
• Combine end results of dc and ac analysis to yield total voltages and currents
in the network.

13
 DC Analysis Example: Four-Resistor
MOSFET Biasing Circuit
+10 V +10 V +10 V Req  RG1 RG 2 +10 V

RD RD 1.5 1 0.6 M
RG1 RG1 RD
75 kW 75 kW 600 k 75 kW
1.5 MW 1.5 MW
Req
 1 
M M Veq   10 M 2
 1 1.5  600 kW
G G
RG2 RG2 4 V + RS
RS RS 4 V- Veq 1
1 MW 1 MW 39 kW
39 kW 39 kW

KVL 1: Since IG = 0, Veq = VGS + IDRS ID = (4 - 2.66)/39k =34.4 mA

4 = VGS + 0.5×25m (VGS – 1)2 ×39k
KVL 2: VDS = 10 – IDRD – ISRS
VGS2 + 0.05 VGS – 7.21 = 0
VDS = 10 – 0.0344×(75 +39) = 6.08 V
VGS = -2.71 or 2.66 V
Since VDS > VGS – VTN = 1.66,
Since VGS = -2.71 < VTN = 1,
M is in saturation region.
VGS = 2.66 V.
14
 DC and AC Equivalents for
MOSFET Amplifier
+VCC
X L  L
ac equivalent
 0 rad/s, X L 0 L +
C3   RI
RI C1   + M RL vo
M +
C2   RL vo vi -
+ RB
vi -
RE
RB -
-
RE

-VEE
dc equivalent +VCC
Simplified ac equivalent

Ri
M +
M RL
vi + vo
RB
-
RB -
RE
-VEE

12 15
 Small Signal Parameters of MOSFET
Kn
ig id iD  vGS  VTN 2 1   vDS 
G D 2
+ + i
vgs gmvgs ro vds gm  D  K n VGS  VTN 1  VDS 
vGS Q  pt
-
S -
W 
• Since gate is insulated from channel where K n  nCOX  
 L
by gate-oxide input resistance = . ID
• Small-signal parameters are gm   2Kn I D
VGS  VTN
controlled by the Q-point.
• For same operating point, MOSFET
2
has lower transconductance than BJT.
1
 VDS
1
MOSFET transconductance is ro   
geometry dependent. ID  ID
16
 Small Signal Operation of MOSFET
Kn
 GS TN  for vDS vGS  VTN
2
iD  v  V
2
Kn Kn 
VGS  vgs  VTN  
2
VGS  VTN   2vgs VGS  VTN   vgs
2 
2
iD 
2 2  
Kn
id iD  I D   2vgs VGS  VTN   vgs
2 
2  
For linearity, id should be proportional to vgs

vgs  2 VGS  VTN   vgs 0.2 VGS  VTN 

Since MOSFET can be biased with (VGS - VTN) equal to several volts, it can
handle much larger values of vgs than corresponding values of vbe for BJT.
17
 Small-Signal Model for PMOS
iD ID
id vGS = VGS - vgs
-
vgs + VCC
- vGS i D = ID - i d
VGS
+
S ig = 0 id D
- G
+
vgs gmvgs ro gmvgs ro
vgs
G + D -
ig = 0 ic
S

The small signal model for pMOS is exactly IDENTICAL to that of nMOS.
This is not a mistake because the current direction is taken care of by the
polarity of VGS.
13 18
 Summary of Small Signal Parameters
Parameter BJT n-MOSFET
2I D
IC VGS  VTN
gm K n VGS  VTN 1  VDS  K n VGS  VTN 
VT
2 K n I D 1  VDS   2 K n I D

 VT
rp gm

IC

1
VA  VCE VA  VDS
ro   1
IC IC 
ID ID
Small-signal vbe 0.005 V vgs 0.2 VGS  VTN 
requirement
 Small Signal Analysis of Fully Bypass
C-S Amplifier
VDD
• AC equivalent circuit is
RG1 RD C2   constructed by assuming that
RI C1   D vo all capacitances have zero
G M RL
impedance at signal frequency
S
vi +
- RG2 and dc voltage sources
RS C3  
represent ac grounds.

RI
D • The small signal parameters,
G M + gm and ro of the MOSFET is
vi +
RG
S RD RL vo calculated at the Q-point, ID
-
- and VDS.

R R R
G G1 G2

11 20
 Fully Bypass C-S Amplifier:
Voltage Gain
RI G D
+ gmvgs
+ Overall voltage gain from source vi
vi +
-
RG vgs ro RD RL vo to output voltage across RL is:

- -
S vo vo vg vg
Av     Avt 
R r R R
L 0 D L
vi vg vi vi
Terminal voltage gain between  RG 
gate and drain is:  g m RL  
R
 I  RG 

vd  g m vgs RL
Avt    g m RL
vg vgs

21
 Fully Bypass C-S Amplifier Input Resistance

VDD

ix G D
RG1 RD C2  
+ gmvgs
+
RI C1  
+
M RL vx -
RG vgs ro RD RL vo
+
vi - Rin RG2 - -
RS C3  
S
RG RG1 RG 2

vx ix R
G
R vx R
in ix G

10 22
 Fully Bypass C-S Amplifier
Output Resistance
VDD

G D ix
RG1 RD C2   + gmvgs
RI C1   +
M RL
RI RG vgs ro RD - vx
Rour
vi +
RG2 -
-
RS C3   S
RG RG1 RG 2

Since vgs = 0, gmvgs = 0. vx

Rout  RD ro
ix
vx ix  RD ro  Rout RD if ro RD

12 23
 Fully Bypass C-S Amplifier Example
DC Analysis:

VDS
I1 
5 106
VGS  I1 2 106
0.4VDS
Kn 2
ID  VGS  VTN   (1)
2
Problem: Find voltage gain, input
and output resistances.
VDS 10  20 103  I D  I1 L L (2)
Given Kn = 500 mA/V2, VTN = 1V, VDS 5V , VGS 2V , I D 250  A
l = 0.0167 V-1
24
 Fully Bypass C-S Amplifier Example
(contd.)
Construct the ac equivalent and
simplify it.

Rin  RG  RG1 RG 2 1M 

gm  2K n I D 5.20104 S
Rout ro R R 18.2kΩ
1 D G3
VDS  
R
ro  260 kΩ vo 
Av   gm ( Rout R )
 in

  7.93
ID v 3  R  R 
i  I in 

25
 Amplifier Families
• Constraints for signal injection and extraction yield three families of amplifiers
– Common-Emitter (C-E)/Common- Source (C-S)
– Common-Base (C-B)/Common- Gate (C-G)
– Common-Collector (C-C)/Common- Drain (C-D)
• All circuit examples here use the four-resistor bias circuits to establish Q-point
of the various amplifiers
• Coupling and bypass capacitors are used to change the ac equivalent circuits.
VCC VDD

RB1 RC RG1 RD

Q M

RB2 RG2
RE RS

26
 Amplifier Family
v  v  Kn
 TN 
2
i i I exp  b e is id  v  v  V
 2
g s
V
e c S

  T

VCC VDD

RC C2   RG1 RD C2  
RB1
RI C1  
RI C1  
Q RL M RL
C1 C R
2  I
C2 R
C1  I
+
vi + vi RG2
- RB2 +
- +
vi
RE RL - vi RS RL -

C-E: i/p at B, o/p at C C-S: i/p at G, o/p at D

C-C: i/p at B, o/p at E C-D: i/p at G, o/p at S
C-B: i/p at E, o/p at C C-G: i/p at S, o/p at D
17 27
 C-S Amplifier (Inverting Amplifier):
Terminal Voltage Gain
VDD
RI G D id
RG1 RD C2   + gmvgs
RI
vo +
C1  
M RL
vgs ro

vi +
RD RL vo
RS1 - RG -
S
vi +
- RG2 id -
RS2 C3   RS1

RG RG1 RG 2 RL RD RL

∵ 𝑖𝑟 ≪ 𝑔𝑚 𝑣 𝑔𝑠 , 𝑖𝑑 ≈ 𝑔 𝑚 𝑣 𝑔𝑠
𝑜

vd  id RL  g m vgs RL  g m RL

Avt    
vg vgs  id RS 1 vgs  g m vgs RS1 1  g m RS1
12 28
 C-S Amplifier (Inverting Amplifier):
Input Resistance
VDD
ig= 0 G D

RG1 RD C2   + gmvgs
vo Rin R’in +
RI C1   vgs ro
M RL
vg +
- RD RL vo
RS1 -
Rin S
vi +
- RG2 RG = RG1 || RG1 -
RS2 C3   RS1

vg
 ig 0, Rin   Rin Rin RG RG
ig

18 29
 C-S Amplifier (Inverting Amplifier):
Overall Voltage Gain
VDD RI G D
+ gmvgs
RG1 RD C2   Rin vgs ro +
RI
vo + vo
C1  
vi RL
M RL - - RD
S
RG = RG1 || RG2 -
RS1
+ Rin RS1
vi - RG2
RS2 C3  

RI

+
+ Rin vg
vi
vo vo vg Rin -
Av     Avt  -
vi vg vi RI  Rin

30
 C-S Amplifier (Inverting Amplifier):
Output Resistance
VDD ix
G D
+ gmvgs
RG1 RD C2  
vgs ro R’out Rout
RI C1  
vo
+
M RL Rth - ix RD - vx
Rout S
RS1
+ RS1
vi - RG2
RS2 C3  
Rth RI RG1 RG 2

vx ix  g mix RS 1  ro  ix RS1

vx ix  g m vgs  ro  vs
v
vs ix RS 1   x 1  g m RS 1  ro
Rout
ix
 vg 0, vgs  vs  ix RS1  RD
Rout Rout
21 31
 C-S Amplifier (Inverting Amplifier):
Input Signal Range
For MOSFET small-signal operation, |vgs |  0.2(VGS – VTN).
RI G D
vgs vg  vs vg  g m vgs RS 1
+ gmvgs
vg Rin vgs +
vgs  ro
1  g m RS 1 vi +
- RD RL vo
-
vgs 0.2 VGS  VTN 
S
RG = RG1 || RG2 -
RS1
 vg 0.2 VGS  VTN 1  g m RS 1 

 Rin   RI  Rin 
 vg   vi  vi 0.2 VGS  VTN 1  g m RS1  
R
 I  Rin   R in 
Presence of RS1 increase permissible value of vi.
32
 Summary: C-E and C-S
Parameter Terminal Voltage Input Resistance Output Resistance
Gain
Amplifier Rin 
Rout
Avt
BJT C-E  g m RL  RE1
r    1 RE1  1  
 ro
1  g m RE 1 r  Rth  RE 1 

MOSFET C-S  g m RL
 1  g m RS1  ro
1  g m RS 1
BJT C-C g m RL
r    1 RL  r  Rth 
ro   
1  g m RL   1 
MOSFET C-D g m RL 1
1  g m RL
 ro
gm
BJT C-B 1
g m RL  1  g m r Rth  ro
gm
MOSFET C-G g m RL 1 1  g m Rth  ro
gm
 C-D Amplifier (Voltage Follower):
Terminal Voltage Gain
VDD
RI G S
+ vgs -
+
RG1
vi
+
RG
gmvgs ro RS RL vo
RI C1   -
M -
C2  
vo D
vi +
- RG2 RS RG RG1 RG 2 RL ro RS RL
RL

vs g m vgs RL g m RL

Avt   
vg vgs  g mvgs RL 1  g m RL

If g m RL  1, Avt 1  vo vg

9 34
 C-D Amplifier (Voltage Follower):
Input Resistance
VDD
ix G S
+ vgs - +
RG1 Rin
vx
+ gmvgs ro RS RL vo
RI C1   - RG
M -
C2  

Rin vo D
vi +
- RG2 RS RG RG1 RG 2
RL

vx
vx ix RG Rin  RG
ix

13 35
 C-D Amplifier (Voltage Follower):
Overall Voltage Gain
VDD
RI G S
+ vgs - +
RG1 + Rin vo
vi gmvgs ro RS RL
RI C1   - RG
M -
C2  
vo D
+
vi - RG2 RS
RL
RG RG1 RG 2

vo vo vg RG
Av     Avt 
vi vg vi RI  RG

36
 C-D Amplifier (Voltage Follower):
Output Resistance
VCC
G S ix
+ vgs -

RG1 Rout +
Rth RI RG1 RG 2 gmvgs ro RS -
vx
RI C1  
M
C2  
vo D
+
vi - RG2 RS
Rout RL
vx vx  1 1 
ix    g mv x    g m  v x
RS ro  RS ro 
vx vx
ix    g m vgs 1
RS ro vx  1 1  1 1
Rout     g m  RS ro  RS
vgs  vx ix  RS ro  gm gm

15 37
 C-D Amplifier (Voltage Follower):
Input Signal Range
For MOSFET small-signal operation, |vgs |  0.2(VGS – VTN).
RI
vgs vg  vs vg  g m vgs RL G
+ vgs - S
+
vg
vgs  vi
+ gmvgs ro RS RL vo
RG
1  g m RL -
-
vgs 0.2 VGS  VTN  D
RL ro RS RL
 vg 0.2 VGS  VTN 1  g m RL 

 RG   RI  RG 
 vg   vi  vi 0.2 VGS  VTN 1  g m RL 
 
 RI  RG   R G 

38
 Summary: C-C and C-D
Parameter Terminal Voltage Input Resistance Output Resistance
Gain
Amplifier Rin 
Rout
Avt
BJT C-E  g m RL  RE 1
r    1 RE 1  1  
 ro
1  g m RE 1 r  Rth  RE 1 

MOSFET C-S  g m RL
 1  g m RS 1  ro
1  g m RS 1
BJT C-C g m RL
r    1 RL  r  Rth 
ro   
1  g m RL   1 
MOSFET C-D g m RL 1
1  g m RL
 ro
gm
BJT C-B 1
g m RL  1  g m r Rth  ro
gm
MOSFET C-G g m RL 1 1  g m Rth  ro
gm
 C-G Amplifier (Noninverting Amplifier):
Terminal Voltage Gain
ro
VDD
RI S D
id
RD C2   - +
RG1 gmvgs
vo + RS RD vo
vi - vgs RL
M RL
+G -
C1   RI
C3  
RG2
+ vi RL RD RL
RS -
 iro  g m vgs , id  g m vgs
vs  vgs
vd  id RL  g m vgs RL
Avt     g m RL
vs  vgs  vgs
12 40
 C-G Amplifier (Noninverting Amplifier):
Input Resistance
VDD ro

ix S D
RG1 RD C2   - +
vo Rin gmvgs
+ Rin
RL vx - RS vgs RD RL vo
M

C1   RI +G -
C3  
RG2
RS
+
-
vi RL RD RL
Rin
 vgs  vx , ix  gm vx
vx 1
vsd Rin  
ix  g m vgs  ix g m
ro
RS
This current can be ignored due to large r0 Rin Rin RS 
1  g m RS
19 41
 C-G Amplifier (Noninverting Amplifier):
Overall Voltage Gain
VDD ro

RI S D
RG1 RD C2  
vo - +
gmvgs
RL + Rin
M vi - RS vgs RD RL vo
C1   RI -
+G
C3  
RG2
RS
+
-
vi
Rin

RI

+
1 RS
vo vo vs Rin vi + Rin vs Rin RS 
Av     Avt  - g m 1  g m RS
vi vs vi RI  Rin -

42
 C-G Amplifier (Noninverting Amplifier):
Output Resistance
VDD ro

S D
ix
RG1 RD C2   - gmvgs
vo
Rth vgs  RD
Rout Rout +
vx
M RL -
Rout
C1   RI +G
C3   RG2 Rth RI RS
RS
+
-
vi
vx ix  g mix Rth  ro  ix Rth
vx ix  g m vgs  ro  vs 1  g m Rth ix ro
vx
vs ix Rth  
Rout 1  g m Rth  ro
ix
vgs  vs  ix Rth  RD
Rout Rout
20 43
 C-G Amplifier (Noninverting Amplifier):
Input Signal Range
For MOSFET small-signal operation, |vgs |  0.2(VGS – VTN).
ro
 Rin 
vgs    vi RI S D
 RI  Rin  - +
gmvgs
vgs 0.2 VGS  VTN  vi +
-
Rin
RS vgs RD RL vo

 RI  Rin  +G -
 vi 0.2 VGS  VTN  
 R in 
RS RI  Rin RI
 Rin   1  g m RI 
1  g m RS Rin RS
If 𝑅 𝑆 ≫ 𝑅 𝐼 ,|𝑣𝑖| ≤ 0.2 ( 𝑉 𝐺𝑆 −𝑉 𝑇𝑁 )( 1+𝑔 𝑚 𝑅 𝐼 )

44
 Summary: C-B and C-G
Parameter Terminal Voltage Input Resistance Output Resistance
Gain
Amplifier Avt Rin 
Rout

BJT C-E  g m RL  RE1

r    1 RE 1  1  
 ro
1  g m RE 1 r  Rth  RE 1 

MOSFET C-S  g m RL
 1  g m RS1  ro
1  g m RS 1
BJT C-C g m RL
r    1 RL  r  Rth 
ro   
1  g m RL   1 
MOSFET C-D g m RL 1
1  g m RL
 ro
gm
BJT C-B 1
g m RL  1  g m r Rth  ro
gm
MOSFET C-G g m RL 1 1  g m Rth  ro
gm
 Current Gain

ii RI io
Amplifier +
vi +
-
C-E, C-C, C-B, C-S, RL vo
Rin C-D, C-G
-

vo
io RL vo RI  Rin RI  Rin
Ai      Av 
ii vi vi RL RL
RI  Rin

46