ADDRESSING MODES,

COMPUTER
INSTRUCTIONS

Lecture 10
COMPUTER INSTRUCTIONS

Computer instructions are a set of machine language instructions that a

particular processor understands and executes. A computer performs
tasks on the basis of the instruction provided.
An instruction comprises of groups called fields. These fields include:
• The Operation code (Opcode) field which specifies the operation to
be performed.
• The Address field which contains the location of the operand, i.e.,
register or memory location.
• The Mode field which specifies how the operand will be located.
INSTRUCTION SET

■ The instruction set, also called ISA (instruction set architecture), is

part of a computer that pertains to programming, which is basically
machine language. The instruction set provides commands to the
processor, to tell it what it needs to do. The instruction set is stored in
the control unit
■ The instruction set consists of addressing modes, instructions, native
data types, registers, memory architecture, interrupt, and exception
handling, and external I/O.
TYPES OF INSTRUCTION SETS.
■ Reduced Instruction Set Computer (RISC): It is a type of computer architecture
that uses a small, highly optimized set of simple instructions.
■ Complex Instruction Set Computer (CISC): single instruction can execute
several low-level operations such as memory access, arithmetic operations, or
multi-step addressing modes.
■ Minimal instruction set computers (MISC): Minimal instruction set computers
(MISC) is a processor architecture with a very small number of basic instruction
operations and corresponding opcodes
■ Very long instruction word (VLIW): Very long instruction word (VLIW) is an
instruction set architectures designed to exploit instruction level parallelism (ILP)
■ Explicitly parallel instruction computing (EPIC): Is an instruction set that permits
microprocessors to execute software instructions in parallel by using the compiler,
rather than complex on-die circuitry, to control parallel instruction execution. This
was intended to allow simple performance scaling without resorting to higher
clock frequencies.
TYPES OF INSTRUCTION SETS.

■ One instruction set computer (OISC): One instruction set computer

(OISC) is an abstract machine that uses only one instruction obviating
(removing the need) the need for a machine language opcode.
■ Zero instruction set computer (ZISC): Zero instruction set computer
(ZISC) is a computer architecture based on pattern matching and
absence of microinstructions in the classical sense. These chips are
known for being thought of as comparable to the neural networks
being marketed for the number of "synapses" and "neurons"
INSTRUCTION CYCLE

■ The instruction cycle (also known as the fetch–decode–execute cycle

or simply the fetch execute cycle) is the cycle which the central
processing unit (CPU) follows from boot-up until the computer has
shut down in order to process instructions.
■ It is composed of three main stages:
– the fetch stage,
– the decode stage, and
– the execute stage.
■ Fetch Stage:
The next instruction is fetched from the memory address that is currently stored
in the program counter and stored into the instruction register. At the end of the
fetch operation, the PC points to the next instruction that will be read at the next
cycle.
■ Decode Stage:
During this stage, the encoded instruction presented in the instruction register is
interpreted by the decoder
■ Execute Stage:
The control unit of the CPU passes the decoded information as a sequence of
control signals to the relevant function units of the CPU to perform the actions
required by the instruction, such as reading values from registers, passing them
to the ALU to perform mathematical or logic functions on them, and writing the
result back to a register.
If the ALU is involved, it sends a condition signal back to the CU. The result
generated by the operation is stored in the main memory or sent to an output
device.
Based on the feedback from the ALU, the PC may be updated to a different
address from which the next instruction will be fetched.
Register-reference
instructions
■ A register reference instruction is generally any instruction that
accesses registers for operands rather than memory. The format will
vary depending on the specific architecture of the CPU.
■ D7I’T3=r (common to all register reference instructions)
■ The register reference instruction will be executed when the decoder
value D7 = 1, I’ =0 and at time T3. This means that at time T3 the
register reference instruction will be decided.
■ Based on the three values it is clear that this is a register reference
instruction. But the register reference instruction will be decided
based on the bit number (i) from the instruction register
MEMORY REFERENCE
INSTRUCTIONS
■ Actual execution of an instruction in the bus system requires a
sequence of micro operations as data in memory cannot be
processed.
■ Micro operations are needed for data to be read from memory to a
register to operate them on logic circuits.
■ There are 7 memory reference instructions;
1. AND: AND to AC
2. ADD: ADD to AC
4. STA: Store AC
5. BUN: Branch Unconditionally
6. BSA: Branch and Save Return Address
7. ISZ: Increment and Skip if Zero
ADDRESSING MODES
ADDRESSING MODES

An addressing mode means the method by which an operand can be

specified in a register or a memory location. Thus the way any operand is
selected during the program execution is dependent on the addressing
mode of the instruction.

■ Opcode: An opcode is a short of “operation code”. It is portion of

machine language instruction that specifies the operation to be
performed.
■ Operands: means the data to be operated on. Operands are
manipulated by the opcode.
■ Effective address: is the location where operand is present/ found.
Importance of addressing modes.

■ The various addressing mode helps to identify the type of operands in

the instruction.
■ An addressing mode specifies how to calculate the effective memory
address of an operand by using information held in registers and/or
constants contained within a machine instruction or elsewhere.
■ It is one of the important threads that attract full attention of compiler
writers and those who programmed using assembly language directly.
Types of Addressing Modes:
■ Implicit Addressing mode
■ Immediate Addressing mode
■ Direct Addressing mode
■ Indirect Addressing mode
■ Register Addressing mode
■ Register Indirect Addressing mode
■ Displacement Addressing mode
■ Stack addressing mode.
■ Implicit addressing mode.
Under this type of addressing mode, by default the instruction knows from
where it is going to access the operand.
■ Immediate addressing mode
In this mode, the operand is specified in the instruction itself. An immediate
mode instruction has an operand field rather than the address field. Therefore
no computations are required to obtain the effective address.
■ Direct addressing mode
In this mode, effective address of the operand is present in instruction itself.
 Single memory reference to access data.
 No additional calculations to find the effective address of the operand.
■ Indirect addressing mode.
In this mode, the address field of the instruction gives the address where the
effective address is stored in memory. This slows down the execution, as this
includes multiple memory lookups to find the operand
■ Register addressing mode
In this mode the operand is stored in the register and this register is
present in CPU. The instruction has the address of the register where the
operand is stored.
■ Register indirect addressing mode
In this mode the instruction specifies the register whose contents give us the
address of operand which is in memory. Thus the register contains the address
of operand rather than the operand it’s self.

■ Displacement addressing mode.

The instruction contains the opcode and register name and an address. The
register will be selected from the register set and its content will be added to
the address (base address) and it will be known as the effective address then
mapped on to the memory to access the operand
Displacement addressing mode is categorized into the following:
-- Relative: the register in this case is a program counter. Therefore EA =
A+ PC
-- Base register: the register will contain the base address, offset address
i.e. EA = A + (offset address)
-- Indexing: starting base address of the memory block and the index, i.e.
EA = A + (XR) where XR is the index register.
■ Stack-memory addressing modes
In this mode, operand is at the top of the stack.
For example:
ADD, this instruction will POP top two items from the stack, add them,
and will PUSH the result to the top of the stack.
THE END