HARDWARE DESIGN

1
Outline
 Introduction
 Combinational logic
 Sequential logic
 Custom single-purpose processor design
 RT-level custom single-purpose processor
design
 Introduction
 Processor
 Digital circuit that performs a
computation tasks
 Controller and datapath Digital camera chip
CCD
 General-purpose: variety of computation CCD preprocessor Pixel coprocessor D2A
tasks A2D

 Single-purpose: one particular lens

computation task
JPEG codec Microcontroller Multiplier/Accum
 Custom single-purpose: non-standard
task
DMA controller Display ctrl
 A custom single-purpose
processor may be
 Fast, small, low power Memory controller ISA bus interface UART LCD ctrl

 But, high NRE, longer time-to-market,

less flexible
 CMOS transistor on silicon
 Transistor
 The basic electrical component in digital systems
 Acts as an on/off switch
 Voltage at “gate” controls whether current flows from source to
drain
 Don’t confuse this “gate” with a logic gate source
gate Conducts
if gate=1
1 drain

gate
IC package IC oxide
source channel drain
Silicon substrate
 CMOS transistor implementations
 Complementary Metal source source

Oxide Semiconductor gate Conducts

if gate=1
gate Conducts
if gate=0
 We refer to logic levels drain drain

nMOS pMOS
 Typically 0 is 0V, 1 is 5V
 Two basic CMOS types
 nMOS conducts if gate=1 1 1 1

x y x
 pMOS conducts if gate=0 x F = x'
F = (xy)' y
 Hence “complementary” x F = (x+y)'
0 y x y
 Basic gates
0 0
 Inverter, NAND, NOR inverter NAND gate NOR gate
 Basic logic gates
x F x F x x y F x x y F x x y F
F y F F
0 0 y 0 0 0 0 0 0 y 0 0 0
1 1 0 1 0 0 1 1 0 1 1
1 0 0 1 0 1 1 0 1
F=x F=xy F=x+y F=xy
Driver AND 1 1 1 OR 1 1 1 1 1 0
XOR

x F x F x x y F x x y F x x y F
F F F
0 1 y 0 0 1 y 0 0 1 y 0 0 1
1 0 0 1 1 0 1 0 0 1 0
F = x’ F = (x y)’ 1 0 1 F = (x+y)’ 1 0 0 F=x y 1 0 0
Inverter NAND 1 1 0 NOR 1 1 0 XNOR 1 1 1
 Combinational logic design
A) Problem description B) Truth table C) Output equations

y is 1 if a is to 1, or b and c are 1. z is 1 if Inputs Outputs y = a'bc + ab'c' + ab'c + abc' + abc

b or c is to 1, but not both, or if all are 1. a b c y z
0 0 0 0 0
0 0 1 0 1 z = a'b'c + a'bc' + ab'c + abc' + abc
0 1 0 0 1
0 1 1 1 0
1 0 0 1 0
1 0 1 1 1
D) Minimized output equations 1 1 0 1 1
y bc 1 1 1 1 1 E) Logic Gates
a 00 01 11 10
0 0 0 1 0
a y
1 1 1 1 1 b
c
y = a + bc
z bc

a 00 01 11 10
0 0 1 0 1
z
1 0 1 1 1

z = ab + b’c + bc’
 Combinational components
I(log n -1) I0 A A B
B A B
I(m-1) I1 I0 n n
… n n n
n …
log n x n n-bit n bit,
S0 n-bit, m x 1 n-bit
Decoder Adder m function S0
… Multiplexor Comparator
ALU …
… n
S(log m) S(log m)
n n
O(n-1) O1 O0 carry sum less equal greater
O O

O= O0 =1 if I=0..00 sum = A+B less = 1 if A<B O = A op B

I0 if S=0..00 O1 =1 if I=0..01 (first n bits) equal =1 if A=B op determined
I1 if S=0..01 … carry = (n+1)’th greater=1 if A>B by S.
… O(n-1) =1 if I=1..11 bit of A+B
I(m-1) if S=1..11

With enable input e  With carry-in input Ci May have status outputs
all O’s are 0 if e=0 carry, zero, etc.
sum = A + B + Ci
 Sequential components
I
n
load shift
n-bit n-bit n-bit
Register Shift register Counter
clear I Q
n n

Q Q

Q= Q = lsb Q=
0 if clear=1, - Content shifted 0 if clear=1,
I if load=1 and clock=1, - I stored in msb Q(prev)+1 if count=1 and clock=1.
Q(previous) otherwise.
 Sequential logic design
A) Problem Description D) Implementation Model
C) State Table (Moore-type)
You want to construct a clock
divider. Slow down your pre- x
Inputs Outputs a Combinational logic
existing clock so that you output a
Q1 Q0 a I1 I0 x I1
1 for every four clock cycles
0 0 0 0 0 I0
0
0 0 1 0 1
0 1 0 0 1 0 Q1 Q0
0 1 1 1 0
B) State Diagram 1 0 0 1 0 0
1 0 1 1 1 State register
a=0 x=0 x=1 a=0 1 1 0 1 1
1
1 1 1 0 0 I1 I0
0 a=1 3

a=1 a=1

1
a=1
2
a=0
 Given this implementation model
a=0 x=0 x=0
 Sequential logic design quickly reduces
to combinational logic design
 Sequential logic design (cont.)
E) Minimized Output Equations F) Combinational Logic
I1 Q1Q0
a 00 01 11 10
a
0 0 0 1 1
I1 = Q1’Q0a + Q1a’ + x
1 Q1Q0’
0 1 0 1

I0 Q1Q0 I1
00 01 11 10
a
0 0 1 1 0 I0 = Q0a’ + Q0’a

1 1 0 0 1

x Q1Q0 I0
a
00 01 11 10
0 0 0 1 0 x = Q1Q0
Q1 Q0
1 0 0 1 0
 Custom single-purpose processor
basic model
… …

external external
control data controller datapath
inputs inputs
… …
datapath next-state registers
control and
controller inputs datapath control
logic

datapath
control state functional
outputs register units
… …
external external
control data
outputs outputs
… …

controller and datapath a view inside the controller and datapath

 Example: greatest common divisor
!1
(a) black-box view 1:
(c) state diagram
 First create algorithm 1
!(!go_i)
2:
 Convert algorithm to go_i x_i y_i !go_i
2-J:

“complex” state machine GCD

3: x = x_i
d_o
 Known as FSMD: finite- 4: y = y_i
state machine with datapath (b) desired functionality
5: !(x!=y)
 Can use templates to 0: int x, y; x!=y
1: while (1) {
perform such conversion 2: while (!go_i);
6:
x<y !(x<y)
3: x = x_i;
y = y -x 8: x = x - y
4: y = y_i; 7:
5: while (x != y) {
6-J:
6: if (x < y)
7: y = y - x;
else 5-J:

8: x = x - y; 9: d_o = x
}
9: d_o = x; 1-J:
}
 State diagram templates
Assignment statement Loop statement Branch statement
a=b while (cond) { if (c1)
next statement loop-body- c1 stmts
statements else if c2
} c2 stmts
next statement else
other stmts
next statement

!cond
a=b C: C:
cond c1 !c1*c2 !c1*!c2

next loop-body-
c1 stmts c2 stmts others
statements
statement

J: J:

next next statement

statement
 Creating the datapath
 Create a register for any 1:
!1

declared variable 1
!(!go_i)
2:
 Create a functional unit for !go_i
x_i y_i
Datapath
each arithmetic operation 2-J:
x_sel
n-bit 2x1 n-bit 2x1
3: x = x_i
 Connect the ports, registers y_sel
x_ld
0: x 0: y
and functional units 4: y = y_i
y_ld

 Based on reads and writes 5: !(x!=y)

!= < subtractor subtractor
x!=y
 Use multiplexors for multiple 5: x!=y 6: x<y 8: x-y 7: y-x
6: x_neq_y
sources x<y !(x<y) x_lt_y 9: d
y = y -x 8: x = x - y
 Create unique identifier 7: d_ld
d_o
6-J:
 for each datapath component
control input and output 5-J:

9: d_o = x

1-J:
 Creating the controller’s FSM
!1 go_i
1:
Controller !1
 Same structure as FSMD
1
!(!go_i) 0000 1:
2:
1
!(!go_i)  Replace complex
0001 2:
!go_i
2-J:
!go_i actions/conditions with
3: x = x_i
0010 2-J:
x_sel = 0
datapath configurations
0011 3: x_ld = 1

4: y = y_i
y_sel = 0 x_i y_i
0100 4: y_ld = 1
!(x!=y)
Datapath
5: !x_neq_y
0101 5: x_sel
x!=y n-bit 2x1 n-bit 2x1
x_neq_y y_sel
6: 0110 6:
x_ld
x<y !(x<y) x_lt_y !x_lt_y 0: x 0: y
y_ld
7: y = y -x 8: x = x - y 7: y_sel = 1 8: x_sel =1
y_ld = 1 x_ld = 1

6-J: 0111 1000

!= < subtractor subtractor
1001 6-J:
5: x!=y 6: x<y 8: x-y 7: y-x
5-J: x_neq_y
1010 5-J:
x_lt_y 9: d
9: d_o = x 1011 9: d_ld = 1
d_ld

1-J: 1100 1-J: d_o

 Splitting into a controller and
datapath go_i

Controller implementation model Controller !1

0000 1: x_i y_i
go_i 1
x_sel !(!go_i) (b) Datapath
Combinational y_sel 0001 2:
logic !go_i x_sel
x_ld n-bit 2x1 n-bit 2x1
y_ld 0010 2-J: y_sel
x_neq_y x_sel = 0 x_ld
0011 3: x_ld = 1 0: x 0: y
x_lt_y y_ld
d_ld
y_sel = 0
0100 4: y_ld = 1
!= < subtractor subtractor
x_neq_y=0 5: x!=y 6: x<y 8: x-y 7: y-x
0101 5:
x_neq_y
Q3 Q2 Q1 Q0 x_neq_y=1
0110 6: x_lt_y 9: d
State register d_ld
x_lt_y=1 x_lt_y=0
I3 I2 I1 I0
7: y_sel = 1 8: x_sel =1 d_o
y_ld = 1 x_ld = 1
0111 1000
1001 6-J:

1010 5-J:

1011 9: d_ld = 1

1100 1-J:
 Controller state table for the GCD
example
Inputs Outputs
Q3 Q2 Q1 Q0 x_neq x_lt_y go_i I3 I2 I1 I0 x_sel y_sel x_ld y_ld d_ld
_y
0 0 0 0 * * * 0 0 0 1 X X 0 0 0
0 0 0 1 * * 0 0 0 1 0 X X 0 0 0
0 0 0 1 * * 1 0 0 1 1 X X 0 0 0
0 0 1 0 * * * 0 0 0 1 X X 0 0 0
0 0 1 1 * * * 0 1 0 0 0 X 1 0 0
0 1 0 0 * * * 0 1 0 1 X 0 0 1 0
0 1 0 1 0 * * 1 0 1 1 X X 0 0 0
0 1 0 1 1 * * 0 1 1 0 X X 0 0 0
0 1 1 0 * 0 * 1 0 0 0 X X 0 0 0
0 1 1 0 * 1 * 0 1 1 1 X X 0 0 0
0 1 1 1 * * * 1 0 0 1 X 1 0 1 0
1 0 0 0 * * * 1 0 0 1 1 X 1 0 0
1 0 0 1 * * * 1 0 1 0 X X 0 0 0
1 0 1 0 * * * 0 1 0 1 X X 0 0 0
1 0 1 1 * * * 1 1 0 0 X X 0 0 1
1 1 0 0 * * * 0 0 0 0 X X 0 0 0
1 1 0 1 * * * 0 0 0 0 X X 0 0 0
1 1 1 0 * * * 0 0 0 0 X X 0 0 0
1 1 1 1 * * * 0 0 0 0 X X 0 0 0
 Completing the GCD custom
single-purpose processor design
 We finished the datapath … …

 We have a state table for controller datapath

the next state and control

next-state registers
logic and
control
 All that’s left is logic

combinational logic
state functional
design register units

 This is not an optimized

design, but we see the … …
basic steps
a view inside the controller and datapath
 RT-level custom single-purpose
processor design
 We often start with a state

Problem Specification
machine Sende Bridge Rece
r rdy_in A single-purpose processor that rdy_out iver
 Rather than algorithm converts two 4-bit inputs, arriving one
clock at a time over data_in along with a
 Cycle timing often too central rdy_in pulse, into one 8-bit output on
data_out along with a rdy_out pulse.
data_in(4) data_out(8)
to functionality
 Example
rdy_in=0 Bridge rdy_in=1
 Bus bridge that converts 4-bit
rdy_in=1

bus to 8-bit bus WaitFirst4 RecFirst4Start

data_lo=data_in
RecFirst4End

 Start with FSMD

rdy_in=0 rdy_in=0 rdy_in=1
rdy_in=1
 Known as register-transfer
WaitSecond4 RecSecond4Start RecSecond4End
FSMD

(RT) level data_hi=data_in

rdy_in=0
 Exercise: complete the design Inputs
Send8Start rdy_in: bit; data_in: bit[4];
data_out=data_hi Send8End
Outputs
& data_lo rdy_out=0
rdy_out: bit; data_out:bit[8]
rdy_out=1 Variables
data_lo, data_hi: bit[4];
RT-level custom single-purpose processor
design (cont’)
Bridge
(a) Controller
rdy_in=0 rdy_in=1
rdy_in=1
WaitFirst4 RecFirst4Start RecFirst4End
data_lo_ld=1
rdy_in=0 rdy_in=0 rdy_in=1
rdy_in=1
WaitSecond4 RecSecond4Start RecSecond4End
data_hi_ld=1

Send8Start Send8End
data_out_ld=1 rdy_out=0
rdy_out=1

rdy_in rdy_out
clk

data_in(4) data_out

data_lo_ld
data_out_ld
data_hi_ld
registers

data_hi data_lo
to all

data_out
(b) Datapath
Optimizing single-purpose
processors
 Optimization is the task of making design
metric values the best possible
 Optimization opportunities
 original program
 FSMD
 datapath
 FSM
Optimizing the original program
 Analyze program attributes and look for areas
of possible improvement
 number of computations
 size of variable
 time and space complexity
 operations used
 multiplication and division very expensive
Optimizing the original program
(cont’)
original program optimized program
0: int x, y; 0: int x, y, r;
1: while (1) { 1: while (1) {
2: while (!go_i); 2: while (!go_i);
3: x = x_i; // x must be the larger number
4: y = y_i; 3: if (x_i >= y_i) {
5: while (x != y) { replace the subtraction operation(s) 4: x=x_i;
6: if (x < y) with modulo operation in order to 5: y=y_i;
7: y = y - x; speed up program }
else 6: else {
8: x = x - y; 7: x=y_i;
} 8: y=x_i;
9: d_o = x; }
} 9: while (y != 0) {
10: r = x % y;
11: x = y;
12: y = r;
}
13: d_o = x;
}
GCD(42, 8) - 9 iterations to complete the loop GCD(42,8) - 3 iterations to complete the loop
x and y values evaluated as follows : (42, 8), (43, 8), x and y values evaluated as follows: (42, 8), (8,2),
(26,8), (18,8), (10, 8), (2,8), (2,6), (2,4), (2,2). (2,0)
Optimizing the FSMD
 Areas of possible improvements
 merge states
 states with constants on transitions can be
eliminated, transition taken is already known
 states with independent operations can be
merged
 separate states
 states which require complex operations
(a*b*c*d) can be broken into smaller states to
reduce hardware size
 scheduling
 Optimizing the FSMD (cont.)
int x, y; !1 optimized FSMD
original FSMD
1:
int x, y;
1
!(!go_i) eliminate state 1 – transitions have constant values 2:
2:
!go_i go_i !go_i

2-J: x = x_i
3: y = y_i
merge state 2 and state 2J – no loop operation in
3: x = x_i between them
5:

4: y = y_i x<y x>y

merge state 3 and state 4 – assignment operations are
independent of one another 7: y = y -x 8: x = x - y
5: !(x!=y)

x!=y
9: d_o = x
6: merge state 5 and state 6 – transitions from state 6 can
x<y !(x<y) be done in state 5
y = y -x 8: x = x - y
7:
eliminate state 5J and 6J – transitions from each state
6-J: can be done from state 7 and state 8, respectively

5-J:
eliminate state 1-J – transition from state 1-J can be
d_o = x done directly from state 9
9:

1-J:
Optimizing the datapath
 Sharing of functional units
 one-to-one mapping, as done previously, is not
necessary
 if same operation occurs in different states, they
can share a single functional unit
 Multi-functional units
 ALUs support a variety of operations, it can be
shared among operations occurring in different
states
Optimizing the FSM
 State encoding
 task of assigning a unique bit pattern to each state
in an FSM
 size of state register and combinational logic vary
 can be treated as an ordering problem

 State minimization
 task of merging equivalent states into a single state

state equivalent if for all possible input combinations
the two states generate the same outputs and
transitions to the next same state
Summary
 Custom single-purpose processors
 Straightforward design techniques
 Can be built to execute algorithms
 Typically start with FSMD
 CAD tools can be of great assistance
Layout, Fabrication, and
Elementary Logic Design
Introduction
 Integrated circuits: many transistors on one
chip.
 Very Large Scale Integration (VLSI)
 Complementary Metal Oxide Semiconductor
(CMOS)
 Fast, cheap, “low-power” transistors circuits
 VLSI:Very Large Scale Integration
 Integration: Integrated Circuits
 Multiple devices (transistors) on one substrate (chip)
 How large is Very Large?
 SSI (small scale integration): 7400 series, 10-100 transistors
 MSI (medium scale): 74000 series 100-1000
 LSI 1,000-10,000 transistors
 VLSI > 10,000 transistors
 ULSI/SLSI (some disagreement)
 Complementary Metal Oxide Semiconductor (CMOS)
 Fast, cheap, “low-power” transistors circuits
 The Process of VLSI Design:
Consists of many different representations/Abstractions
of the system (chip) that is being designed.
 System Level Design

 Architecture / Algorithm Level Design

 Digital System Level Design

 Logical Level Design

 Electrical Level Design

 Layout Level Design

 Semiconductor Level Design (possibly more)

Each abstraction/view is itself a Design Hierarchy of

refinements which decompose the design.
Computer Aided Design tools
 Tools  Experts
 Editors  Logic design
 Simulators  Electronic/circuit
 Libraries design
 Module Synthesis  Device physics

 Place/Route  Artwork

 Chip Assemblers  Applications - system

 Silicon Compilers design

 Architectures
 New Design Methodologies
 Methodologies which are based on:
 System Level Abstractions v.s. Device
Characteristic Abstractions
 Logic structures and circuitry change slowly over
time
 trade-offs do change, but the choices do not
 Scalable Designs
 Layout techniques also change slowly.
 But the minimum feature size steadily decreases
with time (also Voltage, Die Size, etc.)
Design Approaches
 Custom
 full control of design
 best results, slowest design time.
 Semi-custom (std cell)
 use Cell libraries from vendor
 cad tools, faster design time
 Gate Array
 fastest design time
 worst speed/power/density
 best low volume (worst high volume)
 EPLA/EPLD - FPGA - electrically programmable (in the
field) -
Technologies
 Bipolar (BJT)
 TTL, Schottky
 ECL
 I^2 L
 Dual Junction, current controlled devices
 MOS (FET unipolar)
 NMOS, PMOS
 CMOS <== our course
 Single Junction voltage controlled devices
 GaAs (typically JFET’s)
 OEIC’s - MQW’s, Integrated Lasers,?
 Silicon in 2010
Density AccessTime
(Gbits/cm2) (ns)
Die Area: 2.5x2.5 cm
DRAM 8.5 10
Voltage: 0.6 V
DRAM (Logic) 2.5 10
Technology: 0.07 m
SRAM (Cache) 0.3 1.5

Density Max. Ave. Power Clock Rate

(Mgates/cm2) (W/cm2) (GHz)
Custom 25 54 3
Std. Cell 10 27 1.5
GateArray 5 18 1
Single-Mask GA 2.5 12.5 0.7
FPGA 0.4 4.5 0.25
 WHY VLSI DESIGN?

Money, technology, civilization

Digression: Silicon Semiconductors

 Modern electronic chips are built mostly on silicon substrates

 Silicon is a Group IV semiconducting material
 crystal lattice: covalent bonds hold each atom to four neighbors

Si Si Si

Si Si Si

Si Si Si

http://onlineheavytheory.net/silicon.html
 Dopants
 Silicon is a semiconductor at room temperature
 Pure silicon has few free carriers and conducts poorly
 Adding dopants increases the conductivity drastically
 Dopant from Group V (e.g. As, P): extra electron (n-
type)
 Dopant from Group III (e.g. B, Al): missing electron,
called hole (p-type)

Si Si Si Si Si Si
- +
+ -
Si As Si Si B Si

Si Si Si Si Si Si
p-n Junctions
 First semiconductor (two terminal) devices
 A junction between p-type and n-type
semiconductor forms a diode.
 Current flows only in one direction

p-type n-type

anode cathode
MOS Integrated Circuits
 1970’s processes usually had only nMOS transistors
Inexpensive, but consume power while idle
 1980s-present: CMOS processes for low idle power

Intel 1101 256-bit SRAM Intel 4004 4-bit Proc Pentium 4 Processor
Transistor Types
 Bipolar transistors
 npn or pnp silicon structure
 Small current into very thin base layer controls large
currents between emitter and collector
 Base currents limit integration density
 Metal Oxide Semiconductor Field Effect Transistors
 nMOS and pMOS MOSFETS
 Voltage applied to insulated gate controls current
between source and drain
 Low power allows very high integration
 First patent in the ’20s in USA and Germany
 Not widely used until the ’60s or ’70s
 MOS Transistors
 Four terminal device: gate, source, drain, body
 Gate – oxide – body stack looks like a capacitor
 Gate and body are conductors (body is also called the substrate)
 SiO2 (oxide) is a “good” insulator (separates the gate from the body
 Called metal–oxide–semiconductor (MOS) capacitor, even though
gate is mostly made of poly-crystalline silicon (polysilicon)

Source Gate Drain Source Gate Drain

Polysilicon Polysilicon
SiO 2 SiO 2

n+ n+ p+ p+
p bulk Si n bulk Si

NMOS PMOS
NMOS Operation
 Body is commonly tied to ground (0 V)
 Drain is at a higher voltage than Source
 When the gate is at a low voltage:
 P-type body is at low voltage
 Source-body and drain-body “diodes” are OFF
 No current flows, transistor is OFF
Source Gate Drain
Polysilicon
SiO2

0
n+ n+
S D
p bulk Si
NMOS Operation Cont.
 When the gate is at a high voltage: Positive charge
on gate of MOS capacitor
 Negative charge is attracted to body under the gate
 Inverts a channel under gate to “n-type” (N-channel, hence
called the NMOS) if the gate voltage is above a threshold
voltage (VT)
 Now current can flow through “n-type” silicon from source
through channel to drain, transistor is ON
Source Gate Drain
Polysilicon
SiO2

1
n+ n+
S D
p bulk Si
PMOS Transistor
 Similar, but doping and voltages reversed
 Body tied to high voltage (VDD)
 Drain is at a lower voltage than the Source
 Gate low: transistor ON
 Gate high: transistor OFF
 Bubble indicates inverted behavior
Source Gate Drain
Polysilicon
SiO 2

p+ p+

n bulk Si
Power Supply Voltage
 GND = 0 V
 In 1980’s, VDD = 5V
 VDD has decreased in modern processes
 High VDD would damage modern tiny transistors
 Lower VDD saves power
 VDD = 3.3, 2.5, 1.8, 1.5, 1.2, 1.0,
 Effective power supply voltage can be lower due
to IR drop across the power grid.
Transistors as Switches
 In Digital circuits, MOS transistors are
electrically controlled switches
 Voltage at gate controls path from source to
g=0 g=1
drain d d
d
nMOS g OFF
ON
s s s

d d d

pMOS g OFF
ON
s s s
CMOS Inverter

A Y VDD
0
1

A Y

A Y
GND
CMOS Inverter

A Y VDD
0
1 0 OFF
A=1 Y=0

ON Y is pulled low by the

turned on NMOS

A Y Device. Hence NMOS

is the pull-down

GND
device.
CMOS Inverter

A Y VDD Y is pulled high by

0 1 the turned on PMOS
Device. Hence PMOS

1 0 ON is the pull-up device.

A=0 Y=1

OFF
A Y
GND
CMOS NAND Gate
A B Y
0 0
0 1 Y
1 0 A
1 1
B
CMOS NAND Gate
A B Y
0 0 1 ON ON
0 1 Y=1
1 0
A=0 OFF
1 1
B=0 OFF
CMOS NAND Gate
A B Y
0 0 1 OFF ON
0 1 1 Y=1
1 0
A=0 OFF
1 1
B=1 ON
CMOS NAND Gate
A B Y
0 0 1 ON OFF
0 1 1 Y=1
1 0 1
A=1 ON
1 1
B=0 OFF
CMOS NAND Gate
A B Y
0 0 1 OFF OFF
0 1 1 Y=0
1 0 1
A=1 ON
1 1 0
B=1 ON
CMOS NOR Gate
A B Y
0 0 1 A
0 1 0
1 0 0 B
1 1 0 Y
3-input NAND Gate
 Y is pulled low if ALL inputs are 1
 Y is pulled high if ANY input is 0

Y
A
B
C
CMOS Fabrication
 CMOS transistors are fabricated on silicon
wafer
 Wafers diameters (200-300 mm)
 Lithography process similar to printing press
 On each step, different materials are
deposited, or patterned or etched
 Easiest to understand by viewing both top
and cross-section of wafer in a simplified
manufacturing process
Inverter Cross-section
 Typically use p-type substrate for nMOS transistors
 Requires to make an n-well for body of pMOS
transistors
A
GND VDD
Y SiO 2

n+ diffusion

p+ diffusion
n+ n+ p+ p+
polysilicon
n well
p substrate
metal1

nMOS transistor pMOS transistor

Well and Substrate Taps
 Substrate must be tied to GND and n-well to VDD
 Metal to lightly-doped semiconductor forms poor
connection called Schottky Diode
 Use heavily doped well and substrate contacts/taps
(or ties) A
GND VDD
Y

p+ n+ n+ p+ p+ n+
n well
p substrate

substrate tap well tap

Inverter Mask Set A
GND VDD
Y

p+ n+ n+ p+ p+ n+
n well
p substrate

substrate tap well tap

GND VDD

nMOS transistor pMOS transistor

substrate tap well tap
 Detailed Mask Views
 Six masks n well

 n-well
 Polysilicon
Polysilicon

 n+ diffusion
 p+ diffusion n+ Diffusion

 Contact p+ Diffusion

 Metal Contact

In reality >40 masks

In may be needed

Metal
 Fabrication Steps
 Start with blank wafer (typically p-type where NMOS is created)
 Build inverter from the bottom up
 First step will be to form the n-well (where PMOS would reside)
 Cover wafer with protective layer of SiO (oxide)
2
 Remove oxide layer where n-well should be built
 Implant or diffuse n dopants into exposed wafer to form n-well
 Strip off SiO2

p substrate
Oxidation
 Grow SiO2 on top of Si wafer
 900 – 1200 C with H2O or O2 in oxidation
furnace

SiO 2

p substrate
Photoresist
 Spin on photoresist
 Photoresist is a light-sensitive organic polymer
 Property changes where exposed to light

 Two types of photoresists (positive or negative)

 Positive resists can be removed if exposed to UV light
 Negative resists cannot be removed if exposed to UV light

Photoresist
SiO 2

_
p substrate
Lithography
 Expose photoresist to Ultra-violate (UV) light
through the n-well mask
 Strip off exposed photoresist with chemicals

Photoresist
SiO 2

p substrate
Etch
 Etch oxide with hydrofluoric acid (HF)
 Seeps through skin and eats bone; nasty
stuff!!!
 Only attacks oxide where resist has been
exposed
 N-well pattern is transferred from the mask to
silicon-di-oxide surface; creates an opening
to the silicon surface
Photoresist
SiO 2

p substrate
Strip Photoresist
 Strip off remaining photoresist
 Use mixture of acids called piranah etch
 Necessary so resist doesn’t melt in next step

SiO 2

p substrate
n-well
 n-well is formed with diffusion or ion implantation
 Diffusion
 Place wafer in furnace with arsenic-rich gas
 Heat until As atoms diffuse into exposed Si
 Ion Implanatation
 Blast wafer with beam of As ions

 Ions blocked by SiO , only enter exposed Si

2

 SiO2 shields (or masks) areas which remain p-type

SiO 2

n well
Strip Oxide
 Strip off the remaining oxide using HF
 Back to bare wafer with n-well
 Subsequent steps involve similar series of
steps

n well
p substrate
Polysilicon
(self-aligned gate technology)

 Deposit very thin layer of gate oxide

 < 20 Å (6-7 atomic layers)
 Chemical Vapor Deposition (CVD) of silicon
layer
 Place wafer in furnace with Silane gas (SiH 4)
 Forms many small crystals called polysilicon
 Heavily doped to be good conductor

Polysilicon
Thin gate oxide

n well
p substrate
Polysilicon Patterning
 Use same lithography process discussed
earlier to pattern polysilicon

Polysilicon

Polysilicon
Thin gate oxide

n well
p substrate
Self-Aligned Process
 Use gate-oxide/polysilicon and masking to
expose where n+ dopants should be diffused
or implanted
 N-diffusion forms nMOS source, drain, and n-
well contact

n well
p substrate
N-diffusion/implantation
 Pattern oxide and form n+ regions
 Self-aligned process where gate blocks n-dopants
 Polysilicon is better than metal for self-aligned gates
because it doesn’t melt during later processing

n+ Diffusion

n well
p substrate
N-diffusion/implantation cont.
 Historically dopants were diffused
 Usually high energy ion-implantation used
today
 But n+ regions are still called diffusion

n+ n+ n+
n well
p substrate
N-diffusion cont.
 Strip off oxide to complete patterning step

n+ n+ n+
n well
p substrate
P-Diffusion/implantation
 Similar set of steps form p+ “diffusion”
regions for PMOS source and drain and
substrate contact

p+ Diffusion

p+ n+ n+ p+ p+ n+
n well
p substrate
Contacts
 Now we need to wire together the devices
 Cover chip with thick field oxide (FO)
 Etch oxide where contact cuts are needed

Contact

Thick field oxide

p+ n+ n+ p+ p+ n+
n well
p substrate
 Metalization
 Sputter on aluminum over whole wafer
 Copper is used in newer technology
 Pattern to remove excess metal, leaving wires

Metal

Metal
Thick field oxide
p+ n+ n+ p+ p+ n+

n well
p substrate
Physical Layout
 Chips are specified with set of masks
 Minimum dimensions of masks determine transistor
size (and hence speed, cost, and power)
 Feature size f = distance between source and drain
 Set by minimum width of polysilicon
 Feature size improves 30% every 3 years or so
 Normalize for feature size when describing design
rules
 Express rules in terms of  = f/2
 E.g.  = 0.3 m in 0.6 m process
Simplified Design Rules
 Conservative rules to get you started
 Inverter Layout
 Transistor dimensions specified as Width / Length
 Minimum size is 4-6/ 2sometimes called 1 unit
 In f = 0.25 m process, this is 0.5-0.75 m wide (W),
0.25 m long (L)
 Since fm.
Technology Roadmap
Technology Roadmap
Technology Roadmap
Summary
 MOS Transistors are stack of gate, oxide,
silicon
and p-n junctions
 Can be viewed as electrically controlled
switches
 Build logic gates out of switches
 Draw masks to specify layout of transistors
 Now you know everything necessary to start
designing schematics and layout for a simple
chip!
Circuits & Layout
CMOS Gate Design
 A 4-input CMOS NOR gate

A
B
C
D
Y
Complementary CMOS
 Complementary CMOS logic gates
 nMOS pull-down network
 pMOS pull-up network pMOS
pull-up
network
 a.k.a. static CMOS
inputs
output

nMOS
pull-down
network

Pull-up OFF Pull-up ON

Pull-down OFF Z (float) 1

Pull-down ON 0 X (crowbar)
 Series and Parallel
a a a a a
0 0 1 1
g1
g2
0 1 0 1
b b b b b
(a) OFF OFF OFF ON

 nMOS: 1 = ON a
0
a
0
a
1
a
1
a

g1

 pMOS: 0 = ON g2
b
0 1 0 1
b b b b

 Series: both must be ON (b) ON OFF OFF OFF

a
 Parallel: either can be ON
a a a a

g1 g2 0 0 0 1 1 0 1 1
b b b b b

(c) OFF ON ON ON

a a a a a

g1 g2 0 0 0 1 1 0 1 1
b b b b b

(d) ON ON ON OFF
 Conduction Complement
 Complementary CMOS gates always produce 0 or 1

 Ex: NAND gate

 Series nMOS: Y=0 when both inputs are 1
 Thus Y=1 when either input is 0
 Requires parallel pMOS Y
A
B
 Rule of Conduction Complements
 Pull-up network is complement of pull-down
 Parallel -> series, series -> parallel
Compound Gates
 Compound gates can do any inverting function
 Ex: AND-AND-OR-INV (AOI22) Y ( A  B )  (C  D)
A C A C
B D B D
(a) (b)

C D
A B C D
A B
(c)
(d)

C D
A
A B
B
Y Y
C
A C
D
B D
(f)

(e)
Example: O3AI

Y ( A  B  C )  D
Example: O3AI

Y ( A  B  C )  D

A
B
C D
Y
D
A B C
Pass Transistors
 Transistors can be used as switches
g

s d

s d
Pass Transistors
 Transistors can be used as switches
g g=0 Input g = 1 Output
s d 0 strong 0
s d
g=1 g=1
s d 1 degraded 1

g g=0 Input Output

g=0
s d 0 degraded 0
s d
g=1
g=0
s d strong 1
Signal Strength
 Strength of signal
 How close it approximates ideal voltage source
 VDD and GND rails are strongest 1 and 0
 nMOS pass strong 0
 But degraded or weak 1
 pMOS pass strong 1
 But degraded or weak 0
 Thus NMOS are best for pull-down network
 Thus PMOS are best for pull-up network
Transmission Gates
 Pass transistors produce degraded outputs
 Transmission gates pass both 0 and 1 well
Transmission Gates
 Pass transistors produce degraded outputs
 Transmission gates pass both 0 and 1 well

Input Output
g = 0, gb = 1 g = 1, gb = 0
g
a b 0 strong 0
a b g = 1, gb = 0 g = 1, gb = 0
a b 1 strong 1
gb

g g g
a b a b a b
gb gb gb
Tristates
 Tristate buffer produces Z when not enabled

EN

EN A Y A Y
0 0 Z
0 1 Z EN
1 0 0
1 1 1 A Y

EN
Nonrestoring Tristate
 Transmission gate acts as tristate buffer
 Only two transistors
 But nonrestoring
 Noise on A is passed on to Y (after several stages, the

noise may degrade the signal beyond recognition)

EN

A Y

EN
Tristate Inverter
 Tristate inverter produces restored output
 Note however that the Tristate buffer
 ignores the conduction complement rule because we want a
Z output

A
EN
Y
EN
Tristate Inverter
 Tristate inverter produces restored output
 Note however that the Tristate buffer
 ignores the conduction complement rule because we want a
Z output

A A
A
EN
Y Y Y
EN

EN = 0 EN = 1
Y = 'Z' Y=A
Multiplexers
 2:1 multiplexer chooses between two inputs

S
S D1 D0 Y
0 X 0 D0 0
0 X 1 Y
D1 1
1 0 X
1 1 X
Multiplexers
 2:1 multiplexer chooses between two inputs

S
S D1 D0 Y
0 X 0 0 D0 0
0 X 1 1 Y
D1 1
1 0 X 0
1 1 X 1
Gate-Level Mux Design
Y SD1  SD0 (too many transistors)
 How many transistors are needed?
Gate-Level Mux Design
Y SD1  SD0 (too many transistors)
 How many transistors are needed? 20
D1
S Y
D0

D1 4 2
S 4 2 Y
D0 4 2
2
Transmission Gate Mux
 Nonrestoring mux uses two transmission
gates
Transmission Gate Mux
 Nonrestoring mux uses two transmission
gates
 Only 4 transistors
S

D0
S Y
D1

S
 Inverting Mux
 Inverting multiplexer
 Use compound AOI22
 Or pair of tristate inverters
 Essentially the same thing

 Noninverting multiplexer adds an inverter

D0 S D0 D1 S
S D1 S S
Y Y D0 0
S S S S Y
D1 1
4:1 Multiplexer
 4:1 mux chooses one of 4 inputs using two
selects
4:1 Multiplexer
 4:1 mux chooses one of 4 inputs using two
selects
 Two levels of 2:1 muxes
 Or four tristates S1S0 S1S0 S1S0 S1S0

D0
S0 S1

D0 0
D1
D1 1
0
Y Y
1
D2 0 D2
D3 1

D3
D Latch
 When CLK = 1, latch is transparent
 Q follows D (a buffer with a Delay)
 When CLK = 0, the latch is opaque
 Q holds its last value independent of D

 a.k.a. transparent latch or level-sensitive latch

CLK CLK

D
Latch

D Q
Q
 D Latch Design
 Multiplexer chooses D or old Q

CLK
CLK
D Q Q
1
Q D Q
0
CLK CLK

Old Q
CLK
D Latch Operation
Q Q
D Q D Q

CLK = 1 CLK = 0

CLK

Q
 D Flip-flop
 When CLK rises, D is copied to Q
 At all other times, Q holds its value
 a.k.a. positive edge-triggered flip-flop, master-
slave flip-flop
CLK
CLK
D
Flop

D Q
Q
 D Flip-flop Design
 Built from master and slave D latches

CLK CLK
CLK QM
D Q
CLK CLK CLK CLK
CLK
Latch

Latch

QM
D Q
CLK CLK

A “negative level-sensitive” latch A “positive level-sensitive” latch

D Flip-flop Operation
Inverted version of D

QM Q
D

CLK = 0

Holds the last value of NOT(D)

QM
D Q

Q -> NOT(NOT(QM))
CLK = 1

CLK

Q
Race Condition
 Back-to-back flops can
malfunction from clock skew
 Second flip-flop fires Early
 Sees first flip-flop change
and captures its result
 Called hold-time failure or
race condition
Nonoverlapping Clocks
 Nonoverlapping clocks can prevent races
 As long as nonoverlap exceeds clock skew
 Good for safe design
 Industry manages skew more carefully instead

2 1
QM
D Q

2 2 1 1

2 1

1

2
Gate Layout
 Layout can be very time consuming
 Design gates to fit together nicely
 Build a library of standard cells
 Must follow a technology rule

 Standard cell design methodology

 VDD and GND should abut (standard height)
 Adjacent gates should satisfy design rules
 nMOS at bottom and pMOS at top
 All gates include well and substrate contacts
Example: Inverter
 Layout using Electric

Inverter, contd..
Example: NAND3
 Horizontal N-diffusion and p-diffusion strips
 Vertical polysilicon gates
 Metal1 VDD rail at top
 Metal1 GND rail at bottom
 32  by 40 
NAND3 (using Electric), contd.
Stick Diagrams
 Stick diagrams help plan layout quickly
 Need not be to scale
 Draw with color pencils or dry-erase markers
Stick Diagrams
 Stick diagrams help plan layout quickly
 Need not be to scale
 Draw with color pencils or dry-erase markers

VDD

Vin
Vout

GND
Wiring Tracks
 A wiring track is the space required for a wire
 4  width, 4  spacing from neighbor = 8  pitch
 Transistors also consume one wiring track
Well spacing
 Wells must surround transistors by 6 
 Implies 12  between opposite transistor flavors
 Leaves room for one wire track
Area Estimation
 Estimate area by counting wiring tracks
 Multiply by 8 to express in 
Example: O3AI
 Sketch a stick diagram for O3AI and estimate area


Y ( A  B  C )  D
Example: O3AI
 Sketch a stick diagram for O3AI and estimate area
 Y ( A  B  C )  D
Example: O3AI
 Sketch a stick diagram for O3AI and estimate area

Y ( A  B  C )  D
Introduction to Semiconductor
Manufacturing Technology
 Objective

 Use common semiconductor terminology

 Describe a basic IC fabrication sequence
 Briefly explain each process step
 Relate your job or products to semiconductor
manufacturing process
 Introduction

 First Transistor, AT&T Bell Labs, 1947

 First Single Crystal Germanium, 1952
 First Single Crystal Silicon, 1954
 First IC device, TI, 1958
 First IC product, Fairchild Camera, 1961
First Transistor, Bell Lab, 1947

Photo courtesy:
AT&T Archive
First Transistor and Its Inventors

John Bardeen, William Shockley and Walter Brattain

Photo courtesy: Lucent Technologies Inc.
First IC Device Made by Jack
Kilby of Texas Instrument in 1958
First Silicon IC Chip Made by Robert
Noyce of Fairchild Camera in 1961

Photo courtesy: Fairchild Semiconductor International

MOS Integrated Circuits
 1970’s processes usually had only nMOS transistors
Inexpensive, but consume power while idle
 1980s-present: CMOS processes for low idle power

Intel 1101 256-bit SRAM Intel 4004 4-bit Proc

 Intel 4004 Micro- Intel Pentium (II)
Processor microprocessor
 Moore’s Law

• Intel co-founder Gorden Moore notice in 1964

• Number of transistors doubled every 12
months while price unchanged
• Slowed down in the 1980s to every 18 months
• Amazingly still correct, likely to keep until
2010.
 Moore’s Law, Intel’s Version
Transistors
Pentium III

10M
80486
Pentium
1M
80386
100K 8086 80286

10K 4040 8080

1K
1975 1980 1985 1990 1995 2000
 Road Map Semiconductor Industry
1995 1997 1999 2001 2004 2007
Minimum feature size ( m) 0.35 0.25 0.18 0.13 0.10 0.07
DRAM
Bits/chip 64 M 256 M 1G 4G 16 G 64 G
Cost/bits @ volume
(millicents) 0.017 0.007 0.003 0.001 0.0005 0.0002
Microprocessor
Transistors/cm2 4M 7M 13 M 25 M 50 M 90 M
Cost/Transistor @ volume
(millicents) 1 0.5 0.2 0.1 0.05 0.02
ASIC
Transistors/cm2 2M 4M 7M 13 M 25 M 40 M
Cost/Transistor @ volume
(millicents) 0.3 0.1 0.05 0.03 0.02 0.01
Wafer size (mm) 200 200 200 - 300 300 300 –
300 400 (?)
 Feature Size and Wafer Size

Chip
or die
Chip made with 0.35 m
technology 300 mm
with 0.25 m
technology
200 mm
with 0.18 m
technology
150 mm
 Smallest Known Transistor Made
by NEC in 1997

Upper gate
Lower gate
Dielectric
Source Drain

n+ n+

Ultra shallow junctions

P-type substrate

0.014 micron lower gate width Photo courtesy: NEC Corporation

Limit of the IC Geometry

Size of the atom

Limit of the IC device
 Atom size: several Å
 Need some atoms to form a device
 Likely the final limit is around 100 Å or 0.01
micron.
 About 30 silicon atoms
IC Design: First IC

Photo courtesy: Texas Instruments

Design Abstraction Levels
SYSTEM

MODULE
+

GATE

CIRCUIT

DEVICE
G
S D
n+ n+
 IC Design:
CMOS Inverter Vin

Vdd
(a)
NMOS PMOS
Vss
Vout

Shallow trench isolation (STI)

N-channel active region P-channel active region
N-channel Vt P-channel Vt
N-channel LDD P-channel LDD
N-channel S/D P-channel S/D

(b)
P-well
Metal 1 Polycide gate and local N-well
interconnection Contact
Metal 1, AlCu

W
PMD

n+ n+ STI p+ p+
P-Well
P-Epi
N-Well
(c)
P-Wafer
 IC Design: Layout and Masks of CMOS Inverter

CMOS inverter layout Mask 1, N-well Mask 2, P-well

Mask 3, shallow trench isolation Mask 4, 7, 9, N-Vt, LDD, S/D Mask 5, 8, 10, P-Vt, LDD, S/D

Mask 6, gate/local interconnection Mask 11, contact Mask 12, metal 1

 Mask/Reticle

Pellicle Chrome pattern Phase shift coating

Quartz substrate
A Mask and a Reticle

Photo courtesy: SGS Thompson

Introduction of IC
Fabrication
Objectives
 Define yield and explain its importance
 Describe the basic structure of a cleanroom.
 Explain the importance of cleanroom
protocols
 List four basic operations of IC processing
 Name at least six process bays in an IC fab
 Explain the purposes of chip packaging
 Describe the standard wire bonding and flip-
chip bump bonding processes
 Wafer Process Flow
Materials IC Fab

Dielectric Test
Metallization CMP
deposition
Wafers

Thermal Etch Packaging

Implant
Processes PR strip PR strip
Masks

Photo- Final Test

lithography

Design
Fab Cost

 Fab cost is very high, > $1B for 8” fab

 Clean room
 Equipment, usually > $1M per tool
 Materials, high purity, ultra high purity
 Facilities
 People, training and pay
Wafer Yield

Wafers good
YW 
Wafers total
Die Yield

Dies good
YD 
Diestotal
Packaging Yield

Chips good
YC 
Chips total
Overall Yield

YT = YWYDYC

Overall Yield determines whether a fab is

making profit or losing money
How Does Fab Make (Loss) Money
 Cost:
 Wafer (8”): ~$150/wafer*
 Processing: ~$1200 ($2/wafer/step, 600 steps)
 Packing: ~$5/chip

 Sale:
 ~200 chips/wafer
 ~$50/chip (low-end microprocessor in 2000)

*Cost of wafer, chips per wafer, and price of chip varies, numbers here are choosing
randomly based on general information.
How Does a Fab Make (Loss) Money
• 100% yield: 150+1200+1000 = $2350/wafer
Cost: • 50% yield: 150+1200+500 = $1850/wafer
• 0% yield: 150+1200 = $1350/wafer

• 100% yield: 20050 = $10,000/wafer

Sale: • 50% yield: 10050 = $5,000/wafer
• 0% yield: 050 = $0.00/wafer

• 100% yield: 10000  2350 = $7650/wafer

Profit • 50% yield : 5000  1850 = $3150/wafer
Margin: • 0% yield : 0  1350 =  $1350/wafer
Question
 If yield for every process step is 99%, what is
the overall processing yield after 600 process
steps?
Answer
 It equals to 99% times 99% 600 times

 0.99600 = 0.0024 = 0.24%

 Almost no yield
Throughput
 Number of wafers able to process
 Fab: wafers/month (typically 10,000)
 Tool: wafers/hour (typically 60)

 At high yield, high throughput brought

Defects and Yield

1
Y n
(1  DA)
Yield and Die Size

Killer Defects

Y = 28/32 = 87.5% Y = 2/6 = 33.3%

Illustration of a Production Wafer

Die

Test die
Illustration of a Production Wafer
Scribe Lines
Test
Structures

Dies
 Clean Room

 Artificial environment with low particle counts

 Started in medical application for post-surgery

infection prevention

 Particles kills yield

 IC fabrication must in a clean room

 Clean Room

 First used for surgery room to avoid bacteria

contamination
 Adopted in semiconductor industry in 1950
 Smaller device needs higher grade clean room
 Less particle, more expensive to build
 Clean Room Class

 Class 10 is defined as less than 10 particles with

diameter larger than 0.5 m per cubic foot.
 Class 1 is defined as less than 1 such particles
per cubic foot.
 0.18 mm device require higher than Class 1
grade clean room.
Cleanroom Classes
100000

10000 Cl
ass
10
Cl 0,
1000 00
# of particles / ft3

as 0
s1
0,
Cl 00
100 Cl a s 0
Cl as s 1,
as s1 00
s1 00 0
10 Cl 0
as
Cl s1
1 as
sM
-1
0.1
0.1 1.0 10
Particle size in micron
Definition of Airborne Particulate
Cleanliness Class per Fed. Std. 209E

Particles/ft3
Class
0.1 m 0.2 m 0.3 m 0.5 m 5 m

M-1 9.8 2.12 0.865 0.28

1 35 7.5 3 1

10 350 75 30 10

100 750 300 100

1000 1000 7

10000 10000 70
Effect of Particles on Masks

Particles
on Mask

Stump Hole on
on +PR PR
Film Film

Substrate Substrate
Effect of Particle Contamination

Ion Beam
Dopant in PR
Particle

Photoresist

Screen Oxide
Partially Implanted Junctions
 Cleanroom Structure
Makeup Air Makeup Air
Fans

Equipment Area HEPA Filter Equipment Area

Class 1000 Class 1000
Process Class 1 Process
Tool Tool
Process Area

Return Air Raised Floor Pump, RF

with Grid Panels and etc.
Mini-environment
 Class 1000 cleanroom, lower cost
 Boardroom arrangement, no walls between
process and equipment
 Better than class 1 environment around
wafers and the process tools
 Automatic wafer transfer between process
tools
Mini-Environment Cleanroom

Makeup Air Makeup Air

Fans

HEPA Filter HEPA Filter

< Class 1
Class 1000
Process Process
Tool Class 1000 Tool

Return Air Raised Floor Pump, RF

with Grid Panels and etc.
 Gowning Area
Shelf of Gloves, Hair
and Shoe Covers Gown Racks Disposal Bins

Entrance Shelf of
Gloves
To
Cleanroom
Wash/Clean
Stations
Shelf of
Storage Gloves

Benches
IC Fabrication Process Module

Thin film growth,

dep. and/or CMP

Photolithography

Etching Ion Implantation

PR Stripping PR Stripping

RTA or Diffusion
Illustration of Fab Floor
Equipment Areas Process Bays

Corridor

Service Area

Sliding Doors Gowning Area

 Mini-environment Fab Floor

Process and
metrology
tools

Service Area

Emergency Exits Gowning Area

Wet Processes

Etch, PR strip, or clean Rinse Dry

 Horizontal Furnace
Wafers
Heating Coils

Quartz
Tube
Gas flow

Temperature Center Zone

Flat Zone

Distance
Vertical Furnace
Process Chamber
Heaters

Wafers

Tower
Schematic of a Track Stepper
Integrated System
Prep
Chamber Spin Coater Chill Plates
Wafer

Stepper

Wafer
Chill Plates Developer Hot Plates
Movement
Cluster Tool with Etch and Strip
Chambers
PR Strip PR Strip
Chamber Chamber

Etch Etch
Chamber Chamber

Transfer
Robot
Chamber

Loading Station Unloading Station

Cluster Tool with Dielectric CVD
and Etchback Chambers
O3-TOES Ar Sputtering
Chamber Chamber

PECVD
Chamber

Robot Transfer
Chamber

Loading Station Unloading Station

Cluster Tool with PVD Chambers
AlCu AlCu
Chamber Chamber

Ti/TiN Ti/TiN
Chamber Chamber

Transfer
Robot
Chamber

Loading Station Unloading Station

Dry-in Dry-out CMP System

Wafer Loading Polishing

and Standby Pad

Post-CMP Clean Polishing

Heads
Rinse
Multi-head Polisher
Dryer and Wafer
Unloading
Clean Station
Process Bay and Equipment Areas
Sliding Doors Process Tools

Tables For PC and

Metrology Tools
Equipment Area

Equipment Area
Process Area

Service Area
Wafer Loading Doors
Test Results

Failed die
 Chip-Bond Structure

Microelectronics Devices and Circuits

Chip Backside Chip (Silicon)

Metallization
Melt and
Solder
Condense
Substrate
Metallization Substrate (Metal or Ceramic)

200
 Wire Bonding

Metal Wire Wire Clamp

Bonding Pad Bonding Pad Bonding Pad

Formation of Press to make Head retreat
molten metal ball contact
 Wire Bonding

Bonding Pad Lead Bonding Pad Lead

Lead contact with Clamp closed with heat

pressure and heat on to break the wire
IC Chip with Bonding Pads

Bonding Pads
IC Chip Packaging
Chip
Bonding
Pad

Pins
Chip with Bumps

Bumps
Flip Chip Packaging

Bumps

Chip

Socket Pins
Bump Contact

Bumps
Chip

Socket Pins
Heating and Bumps Melt

Bumps
Chip

Socket Pins
Flip Chip Packaging

Chip

Socket Pins
Molding Cavity for Plastic Packaging
Top Chase Molding Cavity

Bonding Wires IC Chip

Lead Frame
Chip Bond Metallization
Pins

Bottom Chase
 Ceramic Seal

Bonding Wires IC Chip

Ceramic Cap
Cap Seal
Metallization Layer 2 Layer 2

Lead Frame, Layer 1

Pins

Chip Bond Metallization

Summary
 Overall yield
 Yield determines losing money or making
profit
 Cleanroom and cleanroom protocols
 Process bays
 Process, equipment, and facility areas
 Die test, wafer thinning, die separation, chip
packaging, and final test