Sequential Logic Circuits Introduction

Combinational Logic Circuits:

O/P Levels at any Instant Depend on I/P Variables Applied at That
Time
Assumption : Propagation Delay
Time Neglected
Boolean Functions Determine O/Ps
Combinational Circuits Can’t Store Information of Any Previous Events
Can’t Show O/P Behavior That Depends On Previously Applied Inputs
Classified as Non-regenerative Circuits:
Absence of Feedback Relationship between O/P & I/P
 Sequential Logic Circuits Introduction
Sequential Circuits : O/P Determined by Current I/P as well as Previous I/Ps

A Sequential Circuit is a Combinational Circuit & Memory (in Feedback Loop)

Regenerative Behavior of Sequential Circuits Due to :

Direct OR Indirect +VE Feedback From O/P to I/P
 Sequential Logic Circuits Introduction
Critical Components of Sequential Systems:
Basic Regenerative Circuits
Bistable Circuits
Monostable Circuits
Astable Circuits
General Classification of Non-regenerative & Regenerative Logic Circuits
 Sequential Logic Circuits Introduction
Bistable Circuits : Two Stable States
Reached Under Certain I/P & O/P
Conditions
Monostable Circuits : One Stable Operating Point
If Circuit goes to Unstable State O/P
Comes Back to Stable State
After a Certain Time
Astable Circuits : No Stable Operating Point
Bistable Circuits Most Widely Used O/P Oscillates between 2 States
Basic Latch & Flip-Flop Circuits
Registers
Memory Elements

Next : Electrical Behavior of Bistable Element & Its Applications

 Behavior of Bistable Elements
Bistable Element : Two Identical Cross-coupled Inverter Circuits
O/P Voltage of Inverter (1) = I/P Voltage of Inverter (2)
vo1 = vi2
O/P Voltage of Inverter (2) = I/P Voltage of Inverter (1)
vo2 = vi1
 Behavior of Bistable Elements
Static Input-Output Behavior of Both Inverters = ???

Plot of Voltage Transfer Characteristic of Inverter (1) wrt vo1 – vi2 Axis Pair

I/P & O/P Voltages of Inverter (2)

Correspond to O/P & I/P Voltages of Inverter (1)

The Two Voltage Transfer Characteristics

Intersect at 3 Points
 Behavior of Bistable Elements
Two of Operating Points are Stable
Situation : Circuit Initially Operating at one of the 2 Stable Points
State is Preserved till it is Forced Externally to Change its Operating Point

At Two Stable Operating Points Gain of Each Inverter Circuit < 1

Gain = ? 🡪 Slope of Voltage Transfer Curve
Implication :
Change of State i.e. Move Operating Point from One Stable Point to Other
Needs Large External Voltage
Voltage Gain of Inverter Loop > 1
 Behavior of Bistable Elements
3rd Operating Point : Voltage Gains of Both Inverters > 1
Situation : Circuit is Biased at this Point Initially
Small Voltage Perturbation Introduced at I/P of any Inverter
Amplification !
Operating Point Moves to One of the Stable Operating Points

3rd Operating Point is Unstable

2 Stable Operating Points : Bistable

 Energy Consideration: Bistable Elements

Total Potential Energy Level at Each of the Three Possible Operating Points
Potential Energy is at its Minimum at Two of the Three Operating Points
Voltage Gains of both Inverters = 0

Maximum Energy where Voltage Gains of Both Inverters is Maximum

At the Unstable Operating Point !

Circuit has Two Stable Operating Points 🡪 Two Energy Minima

One Unstable Operating Point 🡪 PE Maximum
CMOS 2-Inverter Bistable Element Circuit & Behaviour

Unstable Operating Point of Ckt : All 4 Xrs in Saturation

Maximum Loop Gain for the Circuit
Situation : Initial Operating Condition Set at Unstable Point
Small Voltage Perturbation Cause Large Changes in Operating Modes of Xrs

O/P Voltages of Two Inverters to Diverge & Eventually Settle at VOH & VOL
Which Direction will Each O/P Voltage Diverge ?
Depends on Initial Perturbation Polarity
CMOS 2-Inverter Bistable Element Circuit & Behaviour
Situation : Bistable Circuit
Operating at vo1 = vo2 = Vth

i.e. At Unstable Operating Point

Assume Cg >> Cd

I/P (Gate) Capacitance … Cg … of Each Inverter >> O/P (Drain) Capacitance Cd

Small-Signal Drain Current of Inverter in terms of Small-Signal Gate Voltage

Drain Current of Each Inverter is also Equal to Gate Current of the Other Inverter
CMOS 2-Inverter Bistable Element Circuit & Behaviour

Small-Signal Transconductance of Inverter : gm

Gate Voltages of Both Inverters in terms of Gate Charges : q1 & q2

Small-Signal Gate Current of Inverter in terms of :

Time
Derivative of its Small-Signal Gate Voltage

From Above Equations It can be Written that

CMOS 2-Inverter Bistable Element Circuit & Behaviour
Expressing to Write Gate Voltages in terms of Gate Charges :

What is the Time Behavior of Gate Charge q ?

Obtained by Combining the Two Differential Equations
Getting a 2nd Order Differential Equation

Expressed in a Simplified Form … using τ0 … Transit Time Constant ??

CMOS 2-Inverter Bistable Element Circuit & Behaviour

Time-domain Solution for q1 :

Initial Condition :

Note that vg1 = v02 … & vg2 = vo1

Replace Gate Charge of Both Inverters with Corresponding O/P Voltage Variables

We Get
CMOS 2-Inverter Bistable Element Circuit & Behaviour
For Large t : Expressions Simplified 🡪

Magnitude of both O/P Voltages Increases Exponentially with Time

What is the Polarity of the Initial Small Perturbation ? … ie Sign of dvo1(0) & dvo2(0)
O/P Voltages of both Inverters Diverge
from Initial value Vth to either VOL or VOH

Polarity of O/P-voltage Perturbation dvo1 must always be opposite to that of dvo2

Why ?
Charge-Conservation Principle
Hence : Two O/P Voltages always Diverge into Opposite Directions …
 Phase-Plane Representation of Bistable Event

Operating Point (vo1 = Vth & vo2 = Vth) is Unstable

Two Operating Points Shown Stable :
(vo1 = VOL , Vo2 = VOH) & (vo1 = VOH , vo2 = VOL)
Using Small-Signal Models at the Corresponding Operating Points
CMOS 2-Inverter Bistable Element Circuit & Behaviour
Situation : Bistable Circuit Settling from Unstable Operating Point to its Stable One
Imagine Signal Traveling Loop … Consisting of Two Cascaded Inverters … Several Times

Time-domain Behavior of O/P Voltage vo1 During this Period is Nearly =

CMOS 2-Inverter Bistable Element Circuit & Behaviour
Situation : Consider Time Interval = T
Signal Travels the Loop n Times
Equivalent to Signal Propagating Cascaded Inverter
Chain

Consisting 2n Inverters
If Loop Gain (Combined Voltage Gain of Two Cascaded Inverters) = A

We Obtain :
Expression Describes Time-domain Behavior of Diverging Process
Till it
Reaches Stable Points
 SR Latch Circuit
So Far 🡪 Bistable Element : Simple Memory Function of Holding Its State
Two Cross-Coupled Inverters
Two Stable Operating Modes
Circuit Preserves its State (Either One of
Two Possible Modes)
As Long as Power Supply Voltage
is Provided

Was Implemented with a Simple Two-Inverter Circuit

Lacks Provision to Allow its State to be Changed Externally

How to do this?
Need to Add Simple Switches to the Bistable Element
Switches Force / Trigger the Circuit from One State to the Other
 SR Latch Circuit
S-R Latch Circuit has 2 Complementary Outputs
Q&Q
Latch Definition : Set State : Output Q = Logic “1" ; & Q = Logic "0"
Reset state : Output Q = Logic “0" ;
& Q = Logic “1"

Gate-level Schematic of SR Latch – Has Two NOR2 Gates

Block Diagram Representation
Figure Out : When Both I/P Signals = Logic "0"
SR Latch Operates Like Simple Cross-coupled Bistable Element
Preserves Either One of its Two Stable Operating Points
Which were Determined by Previous Inputs
 SR Latch Circuit

If S = "0" & R = "1" 🡪 O/P Node Q is Forced to "0" … & Q is Forced to "1“
Latch is Reset for S = 0 ; & R = 1 … Regardless of its Previously Held State

If Both I/Ps … S & R = Logic 1 … Both O/P Nodes are Forced to Logic 0
Conflicts with Complementarity of Q & Q
Hence, This I/P Combination is Not Allowed

Truth Table of NOR-based SR Latch :

 SR Latch Circuit

CMOS Circuit Structure of SR latch

Has Two Triggering Inputs : S (set) & R (reset)
Also Called an SR Flip-Flop (Back and Forth Switching Possible)
??
Has Two CMOS NOR2 Gates
One I/P Terminals of Each NOR Gate Cross-coupled to O/P of Other
NOR Gate
 SR Latch Circuit
Examining Operation of CMOS SR Latch
in Detail

Consider : Operating Modes of Four nMOS transistors : M1, M2, M3, & M4
If Set I/P (S) = VOH ; & Reset I/P (R) = VOL
Both of Parallel-Connected Xrs M1 & M2 will be ON
Voltage on Node Q = Logic-Low Level of VOL = 0
Both M3 & M4 will be OFF
Voltage on Node Q = Logic-High Level of VOH = 1
If Reset I/P (R) = VOH ; & Set I/P (S) = VOL 🡪 Situation is Reversed
 SR Latch Circuit

Situation : Both I/P Voltages = VOL 🡪 Two Possibilities

Depending on Previous State of SR Latch : Either M2 or M3 will be ON
Both of Trigger Transistors M1 & M4 are OFF
Generates a Logic-Low Level of VOL = 0 at One of O/P Nodes
& The Complementary O/P Node is at VOH

Summary of Static Operation Modes & Voltage Levels of NOR-based CMOS SR Latch
 Transient Analysis of SR Latch
Consider An Event Which Results in a State Change
Initially Reset Latch Applied a Set Signal
Initially Set Latch Being Reset by Applying Reset Signal
In These Cases Both O/P Nodes Undergo Simultaneous Voltage Transitions
One O/P Rises from Logic-Low Level to Logic-High
Other O/P Node Falls from Initial Logic-High to Logic-Low

Amount of Time Required for Simultaneous Switching of Two O/P Nodes = ??

Simplified Answer : Assume Two Events Take Place in Sequence … Not Simultaneously
Overestimates Switching
Time
Find Total Parasitic Capacitance Associated with Each Node
Approximated Total Lumped Capacitance at Each O/P Node :
 Transient Analysis of SR Latch
Circuit Dia of SR Latch
Lumped Load capacitances
At Nodes Q & Q
Assumption : Latch Initially Reset

Set Operation is Being Performed by applying S = "1" and R = "0"

Estimate of Rise Time Associated with Node Q :
 Transient Analysis of SR Latch
Calculation of Switching Time trise,Q Needs Two Separate Calculations

for Rise & Fall Times of NOR2 Gates

We Consider Two Events Separately :
1. O/P Node Voltages (Q ) Falling from High to Low … Due to Turn-On of M1
2. Other Node Voltage (Q) Rising from Low to High … Due to Turn-Off of M3
Effect : Overestimation of Actual Switching Time for SR Latch

Both M2 & M4 can be Assumed to be OFF in this Process

Although M2 can be Turned ON as Q Rises
Shortens the Q Node Fall Time
 SR Latch Circuit Built with NAND2 Gates

Gate-level Schematic & Block Diagram Representation of NAND-based SR Latch Circuit

Small Circles at S & R I/P Terminals 🡪 Circuit Responds to Active Low I/Ps
See Truth Table
Timing Analysis : Similar to NOR-based SR latches can be Applied
 SR Latch Circuit Built with NAND2 Gates
One I/P of Each NAND Gate Used to Cross-Couple to O/P of Other NAND Gate
Second I/P Enables External Triggering

To Hold (preserve) a State : Both of External Trigger I/P Must be = Logic "1"
Operating Point of Circuit Changes by Pulling Set I/P to Logic Zero
Or by Pulling Reset I/P to Zero
 SR Latch Circuit Built with NAND2 Gates

If S = "0“ & R = "1" 🡪 Q Goes to Logic "1" … Q becomes Logic "0"

To Reset Latch : Logic "0" must be Applied to Reset (R) I/P
Conclusion : NAND-based SR Latch Responds to Active Low I/P Signals
(NOR-based SR Latch Responded to Active
High Inputs)
NAND-SR-Latch: If Both I/P Signals = Logic "0“
🡪 Both O/P Nodes Assume Logic-High
Level
 Clocked Latch & Flip-Flop Circuits
Clocked SR Latch :

Discussed SR Latches that are Asynchronous Sequential Circuits

Respond to Changes Occurring in I/Ps …. Circuit-Delay-Dependent Time Point
During their Operation

Synchronous Operation:
Circuit Response Controlled by Adding a Gating Clock Signal to the Circuit
Forces O/P to Respond to I/P Levels Only During Active Period of a Clock
Pulse

Assume Clock Pulse to be a Periodic Square Waveform

Applied Simultaneously to All Clocked Logic Gates in the System
 Clocked SR Latch

Gate-level Schematic of Clocked NOR-based SR Latch

If Clock (CK) = Logic "0" 🡪 I/P Signals have No Influence on Circuit Response
O/Ps of Two AND Gates Stay at Logic "0"
Forces SR Latch to Hold its Current State … Regardless of S & R I/Ps
Situation : Clock I/P Goes to Logic "1" …
Logic Levels Applied to S & R I/Ps Can Reach SR Latch … & Possibly Change its
State
Input Combination S = R = "1" is STILL Not Allowed in Clocked SR Latch
If Both S & R are at Logic " 1" … & Clock Pulse Appears
Both O/Ps go Momentarily to Zero
As Clock Pulse is = "0“ … State of Latch is Indeterminate
 Clocked SR Latch
Operation of Clocked SR Latch
Sample Sequence
CK, S, & R Waveforms
Corresponding O/P Waveform Q

Circuit is Strictly Level-Sensitive During Active Clock Phases

Any Changes Occurring in S & R I/P Voltages when CK Level = "1"
Reflected onto Circuit O/Ps
Implication :
A Narrow Spike or Glitch Occurring During Active Clock Phase Can Set/Reset Latch
Happens if Loop Delay is Shorter than Pulse Width
CMOS Implementation of Clocked NOR-based SR Latch

Uses Two Simple AOI Gates

Very Small Transistor Count

wrt Two AND2 & 2 NOR2
Gates
 Clocked NAND-based SR Latch

NAND-based SR Latch Implemented with Gating Clock I/P

Both I/P Signals S & R … as well as Clock Signal CK are Active Low
Changes in I/P Levels will be Ignored when CK = Logic "1"
I/Ps Influence O/Ps only when Clock is Active … CK = "0"

Circuit Implementation : OAI Structure

Analogous to AOI Realization of
Clocked NOR SR Latch Ckt
 Clocked NAND-based SR Latch – Alternate Way

Alternate Implementation :
Both I/P Signals & CK Signal are Active High
Latch O/P Q is Set when CK = "1“ , S = "1" , & R = “0"
Latch Reset when CK = "1“, S = “0“, & R = "1“

Latch Preserves its State till Clock Signal is Inactive … ie CK = “0“

Issue with this Implementation : Transistor Count is Higher than Active Low Version
 Clocked JK Latch
Issue of Simple & Clocked SR Latch Circuits … Having a Not-Allowed Input Combination
State Becomes Indeterminate when both I/Ps S & R are Activated at Same
Time
Solution : Add Two Feedback Lines from O/Ps to I/Ps
Called a JK Latch
All-NAND Implementation of JK Latch with Active High I/P & its Block Diagram
 JK Latch – NAND Implementation

J & K I/Ps of Ckt Similar to Set & Reset I/Ps of Basic SR Latch
Active High Clock Condition : Latch can be Set with I/P Combination (J = '1" K = "0")
Can be Reset with (J = "0" K = "1")
If both I/Ps = Logic "0" : Latch Preserves its Current State
If Both I/Ps = "1" … during Active Clock Phase ???
Latch Switches its State due to Feedback
JK Latch Holds its Current State when Clock is Inactive (CK = "0")
 NOR-based Implementation of Clocked JK Latch

NOR Gate Based Implementation & CMOS Realization of JK Latch

AOI-based Circuit Structure Used
Lower Xr Count
 JK Toggle Switch
Toggling Issue : If Both I/Ps = Logic "1" during Active Phase of Clock Pulse
Ckt O/P will Oscillate (Toggle) Continuously
Till Either Clock Becomes Inactive … OR
One of I/Ps = 0
Prevention : Clock Pulse Width < I/P-to-O/P Propagation Delay of JK Latch
ie Clock Must Go Low Before O/P Level has Chance
to Switch Again
This Constraint is Difficult to Implement
for Most Applications

If Clock Timing Constraint is Satisfied :

O/P of JK Latch Toggles Only Once for Each Value of Clock Pulse, if both I/Ps =
1
 Master-Slave Flip-Flop
Solution to Issue of Timing Limitations Seen in Clocked Latch Circuits
Use Two Latch Stages in a Cascaded Configuration
Important : Two Cascaded Stages Activated with Opposite Clock Phases … MS-FF

Master : I/P Latch … Activated when Clock Pulse is High

I/Ps J & K Allow Data to be Entered into FF … 1st Stage O/Ps Set as per Primary
I/Ps
Clock Pulse goes to Zero : Master Latch is Inactive
2nd -Stage Latch (Slave) Becomes Active
O/P Levels of Flip-Flop are Determined During This 2nd Phase
 Master-Slave Flip-Flop
Master & Slave Stages Decoupled from Each Other – Opposite Clocking
Change in Primary I/Ps Never Reflected Directly to O/Ps
Important Distinction!
 Issues: Master-Slave Flip-Flop

Issue of “One's Catching"

Situation : Clock Pulse is High … Glitch in One of I/Ps Causes Unwanted Transition
Glitch in J Line (or K Line) May Set (or Reset) Master Latch
Error is Propagated into Slave Stage During Next Phase

Possible Solution: Edge-Triggered Master-Slave Flip-Flop

NOR Realization Master-Slave Flip-Flop
 CMOS D-Latch and Edge-Triggered Flip-Flop
Covered So Far
Latch & Flip-Flop Circuits can be Implemented with CMOS Gates
Design is Straightforward
Conventional CMOS Implementation of Clocked JK Latch or MS-FF Need Lots of Xrs

Questions:

Can the Transistor Count Be Reduced ??

Can One Make Specific Versions of Seq Ckts Mainly with CMOS Transmission Gates ??
Will they Be Simpler?
Will they Require Fewer Xrs than Ckts Designed with Conventional
Structuring?

CMOS D-Latch
 CMOS D-Latch
Gate-Level Representation of D-latch
Clocked NOR-based SR Latch Circuit is Modified
Circuit has a Single I/P D … Directly Connected to “S” I/P of Latch
D is Inverted & Connected to “R” I/P of Latch
Therefore, O/P Q takes Value of I/P D … when Clock is Active (CK = "1“)
When Clock goes to Zero … O/P Preserves its State
CK Input Acts as an Enable Signal … Allows Data to be Accepted into D-latch

D-latch Used Digital Circuit Design for Temporary Storage of Data or as Delay Element
 CMOS Implementation of D-Latch
Basic Two-Inverter Loop & Two CMOS Transmission Gate (TG) Switches
TG at I/P Activated by CK Signal
TG in Inverter Loop Activated by Inverse of CK Signal … CK
Information is Accepted (latched) into Circuit when Clock is High
And Preserved as the State of the Inverter Loop when Clock is Low

Not Edge-Triggered Storage Element

O/P Changes according to
I/P
Latch is Transparent
while Clock is High
 CMOS Implementation of D-Latch
Visualized CMOS TGs as Switches
Time Interval when I/P & O/P are Valid (unshaded)
Valid D I/P Must be Stable
for a Short Time Before (setup time, tsetup)
& After (hold time, thold) –VE Clock
Transition

In this Time I/P Switch Opens & Loop Switch Closes

Inverter Loop Completed by Closing Loop Switch
O/P Preserves its Valid Level

Requirements for Setup time & Hold Time Critical

Violation Results in Chaotic Transient Behavior

& Unpredictable State After Transitional
 Version 2: CMOS Implementation of D-Latch

Circuit has Two Tristate Inverters … Driven by Clock Signal & its Inverse
1st Tri-State Inverter Acts as I/P Switch … Accepts I/P When Clock is High
At this Time 2nd Tristate Inverter is at its High-Impedance State
O/P Q Follows I/P Signal
When Clock Goes Low … I/P Buffer is Inactive
2nd Tristate Inverter Completes the 2-Inverter Loop …
Preserves its State Until the Next Clock Pulse
CMOS –VE (falling) Edge-Triggered Master-Slave D-FF

Two-Stage Master-Slave Flip-Flop Circuit Made by Cascading Two D-Latch Circuits

1st Stage (Master) Driven by Clock Signal
2nd Stage (Slave) Driven by Inverted Clock Signal
Master Stage is +VE Level-Sensitive … Slave Stage is –VE Level Sensitive
CMOS –VE (falling) Edge-Triggered Master-Slave D-FF

Simulated I/P & O/P Waveforms of CMOS –VE Edge-Triggered D Flip-Flop

O/P of Master Stage Latches Applied I/P (D) when Clock Signal is "1“
O/P of Slave Stage Becomes Valid when Clock Signal Drops to "0“
D-type Flip-Flop Essentially Samples the I/P at Every Falling Edge of Clock Pulse
CMOS –VE (falling) Edge-Triggered Master-Slave D-FF

Operation of DFF Ckt Seriously Affected if Master Experiences a Set-up Time Violation
In Example I/P D Switches from "0" to "1" Immediately Before Clock Transition Occurs
(set-up time violation)
Effect : Master Fails to Latch the Correct Value 🡪 Slave Produces Erroneous O/P
Careful Synchronization of Relative Timing of I/P & Clock is a Must
Layout of CMOS DFF Circuit
 NAND3-based +VE Edge-Triggered D Flip-Flop

6 NAND3 Gates

Initial : All Signal Values Except for S are 0 … i.e., (S,R, CK, D) = (1, 0, 0, 0), & Q = 0
2nd Phase : Both D & R Switch to 1, i.e., (S, R, CK, D) = (1, 1, 0, 1),
No Change in Q … Value of Q
Remains at 0
3rd Phase : If CK goes High, i.e., (S, R, CK, D) = (1, 1, 1, 1),
O/P of Gate 2 Switches to 0 🡪 Sets O/P of Last Stage SR Latch to 1
Thus O/P of this D-FF Switches to 1 at +VE-Going Edge of Clock CK
 Schmitt Trigger Circuit
Regenerative Ckt … Voltage Transfer Characteristic like an Inverter
Two Different Logic Threshold Voltage … for Increasing & for Decreasing I/P
Signals
Detects Low-to-High & High-to-Low Switching Events in Noisy Environments
Circuit Diagram & VTC
 Schmitt Trigger : Step-by-Step Analysis
Considering a +VE I/P Sweep … I/P Voltage Increases from 0 to VDD
i) At Vin = 0V : M1 & M2 Turned ON 🡪 VX = VY = VDD = 5V
At Same Time : M4 & M5 are Turned OFF … M3 is OFF …
M6 is ON … & Operates in Saturation Region
Calculating the Threshold Voltage of M6 … with 2φF = – 0.6 V
Vz = VDD – V T, 6 = 3.5 V

ii) At Vin = VT0,n = 1.0 V

M5 Starts to Turn ON … M4 is Still OFF
Vx = 5 V
iii) At Vin = 2.0 V :
Assume M4 is OFF … while both M5 & M6 Operate in
Saturation Region
 Schmitt Trigger : Step-by-Step Analysis

Solving Equation for Vz … Only One Physically Reasonable Root

Vz = 2.976 V
Checking Assumption Made … i.e. If M4 is indeed Turned OFF :
VGS,4 = 2 – 2.976 = – 0.976 < VT0,n = 1 OK

iv) At Vin = 3.5 V : Vz Continues to Decrease

Assuming M5 in Linear Region & M6 in Saturation … The Current Equation is :

Solving Equation for Vz … Vz =

2.2 V
 Schmitt Trigger : Step-by-Step Analysis
For M4 What is the Gate-to-Source Voltage ?
VGS,4 = 3.5 – 2.2 = 1.3 > TT0,n = 1
So at this Point M4 is Already ON
Previous Analysis … based on Assumption that M4 is NOT Conducting is Invalid
At this I/P Voltage Node ‘x’ is Being Pulled Down Toward "0"
Conclusion : Upper Logic Threshold Voltage Vth+ ~ 3.5 V

Next Consider a –VE I/P Sweep … I/P is Decreasing from VDD to 0

i) At Vin = 5.0 V :
M4 & M5 are ON … O/P Voltage is Vx = 0 V
pMOS Xrs M1 & M2 are OFF … M3 is in Saturation … thus

Vy = 1.5 V
 Schmitt Trigger : Step-by-Step Analysis
ii) At Vin = 4.0 V :
M1 is at the Edge of Turning ON … M2 is OFF … M3 is in Saturation
O/P Voltage is Still Unchanged

iii) At Vin = 3 0 V :
M1 is ON … And in Saturation … M3 is also in Saturation … Current Equation
:

Solution of this Equation Gives : Vy = 2.02 V

Find Gate-to-Source Voltage of M2 :
VGS,2 = 3.0 – 2.02 = 0. 98 > VT0,p = –1
Indicates M2 is still Turned OFF at this Point
 Schmitt Trigger : Step-by-Step Analysis
iv) At Vin = 1. 5 V:
If M2 is Still OFF … M1 will be in Linear Region & M3 is in Saturation Region

Solution of this Quadratic Equation gives Vy = 2.79 V

Can be Shown that … at this Point pMOS Xr M2 …. is Already Turned ON
Hence, O/P Voltage is being Pulled Up to VDD
Therefore, Lower Logic Threshold Voltage Vth ~ 1.5 V
Schmitt Trigger : SPICE Simulation
Thanks!
• Precharge Voltage:
• In a read operation, the bit lines are precharged to VDD/2, which is 1.3V/2 = 0.65V.
• Stored '1':
• When a '1' is stored, the cell capacitor (Cs) is charged to VDD (1.3V). During the read
operation, this charge is shared between the cell capacitor (Cs) and the bit line
capacitance (Cb). The voltage on the bit line (output voltage) is calculated as: Vout =
VDD/2 + (VDD * Cs) / (Cs + Cb) = 0.65V + (1.3V * 30fF) / (30fF + 300fF) = 0.65V
+ (390fV) / (330fF) = 0.65V + 1.18V = 1.83V.

• Stored '0':
• When a '0' is stored, the cell capacitor is discharged. During the read
operation, the voltage on the bit line remains at the precharge voltage
(VDD/2), which is 0.65V.
 Features Of SRAM:
1) Data is stored as long as supply is applied
2) Fast - so used where speed is important (e.g.,
caches)
3) Differential outputs
4) Low power consumption
5) Compatible with CMOS technology

Memory cells are the key components of any SRAM unit

An SRAM cell offers the following basic parameters.

1) Retention - An SRAM cell is able to retain the data indefinitely as long as it is powered.
2) Read - An SRAM cell is able to communicate its data. This operation does not affect the data i.e., Read
operation is non-destructive.
3) Write - The data of an SRAM cell can be set to any binary value regardless of its original data.
A number of SRAM cell topologies have been reported in the past decade. Among these topologies, resistive load
four-transistor (4T) cell, load less 4T cell and six transistor (6T) SRAM cell have received attention in practice, owing
to their symmetry in storing logic `one' and logic `zero'. The data retention in the 4T SRAM cells is ensured by the
leakage current of the access transistors. Hence, they are not proper candidates for low- power applications. On the
other hand, the data stability in a 6T SRAM cell is independent of the leakage current.

Draw the circuit diagram of Dual Port Static RAM and explain its operations.
1) Assume a load capacitance of 10μA/V0μA/VfF and equivalent resistance for
NMOS is Rn =62kΩ &Ω & PMOS is Rp =180μA/VkΩ &Ω for unit transistors
(W=1). Now, calculate the propagation delay of the circuit using RC delay method.

2) Consider the CMOS inverter circuit covered in the class. Assume fabrication
process with the
following device parameters: VDD =3V, μnCox =180μA/VμA/V2 , Vtn=0μA/V.8V,
Vtp=0μA/V.8V, μpCox=60μA/VμA/V2
a). Determine the size of pullup and pull down path to get the symmetric response.
b.) Assume a load capacitance of 10μA/V0μA/VfF and equivalent resistance for
NMOS is Rn =62kΩ &Ω &
PMOS is Rp =180μA/VkΩ &Ω for unit transistors (W=1). Now, calculate the
propagation delay of the
circuit using RC delay method.
c). Also, calculate the propagation delay of the circuit using average current method.
d). Compare both of the delays obtained in part b & part c and comment on the
difference in delay
if any