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i2c Eeprom Simulation in Verilog-2

The document presents a project on the design and verification of the I2C protocol for EEPROM communication, detailing its components and functionalities. It includes an overview of I2C and EEPROM, the implementation of modules, and the simulation results demonstrating successful data operations. Additionally, it discusses the advantages, disadvantages, and future scope of the project in embedded systems.

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sudheerkurakula1218
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5 views

i2c Eeprom Simulation in Verilog-2

The document presents a project on the design and verification of the I2C protocol for EEPROM communication, detailing its components and functionalities. It includes an overview of I2C and EEPROM, the implementation of modules, and the simulation results demonstrating successful data operations. Additionally, it discusses the advantages, disadvantages, and future scope of the project in embedded systems.

Uploaded by

sudheerkurakula1218
Copyright
© © All Rights Reserved
Available Formats
Download as PPTX, PDF, TXT or read online on Scribd
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Design of I2C protocol

&
Verification of EEPROM

Presented by:-
S. Pavan Sai - RO201082
SK. Shabeena - RO200763
B. Subhash - RO200217
M. Pravallika - RO200474
K. Sudheer - RO200903
Under the guidance
of:-
Ms. D. Havilah
Introduction
• I2C (Inter-Integrated Circuit) is a widely used serial
communication protocol ideal for connecting low-speed
peripherals.
• EEPROM (Electrically Erasable Programmable Read-Only
Memory) allows data storage that persists even after power-off,
crucial for embedded systems.
• This project simulates EEPROM behavior over I2C, enabling
write, read, and erase operations using Verilog testbenches.
• The simulation showcases real-time communication flow
between an I2C master and a slave EEPROM device, offering an
educational and diagnostic tool for digital designers.
• Useful for validating designs before FPGA implementation,
saving time and hardware costs..
What is I2C?
• I2C (Inter-Integrated Circuit) is a multi-master,
multi-slave, serial communication protocol
developed by Philips.
• Uses only two bidirectional lines:
• SDA (Serial Data)
• SCL (Serial Clock)
• Allows communication between microcontrollers
and peripherals (e.g., EEPROM, sensors, RTC).
• Supports device addressing using unique 7-bit or
10-bit addresses.
• Ensures reliable communication with
acknowledgment bits and clock synchronization.
Working of I2C protocol
What is EEPROM?
• Electrically Erasable Programmable Read-Only Memory
• Non-volatile memory used for data storage
• Can be written and erased electrically
Project Overview

• Simulate an EEPROM communication using I2C


protocol.
• Implemented modules:
• I2C Master
• I2C Slave (acts like EEPROM)
• I2C Top Module
• Testbench
I2C Master Module

• Generates clock (SCL)


• Initiates read/write operations
• Sends slave address and data
• Reads acknowledgment and data from slave
I2C Slave (EEPROM) Module

• Monitors SDA and SCL


• Matches slave address
• Sends acknowledgment
• Stores and returns data like EEPROM
Top Module Integration

• Connects Master and Slave via SDA and SCL


• Handles data routing and control signals
• Acts as a system-level verification module
Testbench Operations

• Write Operation: Send data to EEPROM


• Read Operation: Retrieve stored data
• Erase Operation: Overwrite with 0x00
• Displays values and simulates protocol behavior
Simulation Output
Result Summary

• Data successfully written, read, and erased


• Realistic simulation of EEPROM behavior
• Demonstrates complete I2C cycle
Applications of I2C

• Microcontrollers & Sensors: Temperature sensors,


accelerometers, and
• EEPROMs.
• Real-Time Clocks (RTC): Timekeeping modules in
embedded systems.
• Display Interfaces: OLED, LCD, and LED drivers.
• Power Management ICs: Battery monitoring and
power regulation.
• FPGA Communication: Connecting multiple ICs
within FPGA designs.
Advantages

• 1. Uses only two wires (SCL & SDA),


reducing pin count.
• 2. Multi-master and multi-slave support
allows flexible system design.
• 3. Efficient communication with error
detection (ACK/NACK).
• 4. Variable data transfer rates (100 kbps
to 3.4 Mbps).
Disadvantages

• Slower than SPI due to clock-based


control.
• Requires pull-up resistors, adding
hardware complexity.
• Limited data transfer rate for high-
speed applications
Future Scope
• Implement on real hardware using FPGA or
microcontroller
• platforms Extend to multi-slave I2C
communication scenarios
• Add support for page write and sequential
read operations
• Optimize design for low-power embedded
and IoT applications
Thank you!

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