Noida Institute of Engineering and Technology,

Greater Noida

Sequential Logic Circuits

Unit: 2

Logic design and Microcontroller

(ACSIOT-0302) Dr. Akanksha Singh
Assistant Professor
B Tech: 3 Sem. rd
CSE-IOT

Dr. Akanksha Singh LDMC UNIT- 2

04/20/2025 1
 Syllabus

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 Branch Wise Application

• Digital electronics is the basic building for every system while

in IOT we are using Sensors, Microprocessor and
microcontroller.
• Microcontrollers use network interfaces to interact with other
devices locally and to push the data to the IoT application for
any analysis.

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 Course Objective

• To understand and apply the fundamental concepts of logic

systems and various logic circuit optimization techniques.
• Understand techniques for the designing of combinational &
sequential circuits.
• Providing insights of Complete architecture of 8085
Microprocessor with assembly level programming
• Understand architecture of 8051 microcontroller. Also, analyze
the interfacing of 8051 Microcontroller with various I/O
devices.

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 Course Outcomes (COs)

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 Program Outcomes (POs)

• Program Outcomes are narrow statements that describe what the students
are expected to know and would be able to do upon the graduation.

• These relate to the skills, knowledge, and behavior that students acquire
through the programmed.

1. Engineering knowledge 9. Individual and teamwork

2. Problem analysis 10. Communication
3. Design/development of solutions 11. Project management and
4. Conduct investigations of complex finance
problems 12. Life-long learning
5. Modern tool usage
6. The engineer and society
7. Environment and sustainability
8. Ethics

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 Program Specific Outcomes (PSOs)

On successful completion of graduation degree, the CSE(IoT)

graduates will be able to:
• PSO1: Apply concept of IoT to solve real world problems for
societal wellbeing by leveraging latest tools.
• PSO2: Work as an individual or lead a team with good
communication and engage in life-long learning.
• PSO3: Apply ethical principles as a successful professional,
entrepreneur, and pursue higher education.

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 Program Educational Objectives (PEOs)

The Program Educational Objectives (PEOs) of B.Tech CSE(IoT)

program are as follows:
• PEO1: Engage in designing, manufacturing/fabricating, and
maintaining smart systems in the field of IoT.
• PEO2: Solve problems of social relevance through applying the
knowledge of basic science, IoT and pursue higher education
and research.
• PEO3: Engage in life-long learning, career enhancement, and
be able to adapt to dynamic needs of profession and society.
• PEO4: Work as an individual and as a team member in
multidisciplinary projects with effective communication.

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 CO-PO Mapping

COs PO1 PO2 PO3 PO4 PO5 PO6 PO7 PO8 PO9 PO10 PO11 PO12

1 3 2 - - - - - - - - - 2

2 3 3 2 - - - - - - - - 2

3 2 3 2 2 - - - - - - - 2

4 3 3 3 2 - - - - - - - 2

5 3 2 1 - - - - - - - - 2

AVERAGE 2.8 2.6 2 2 - - - - - - - 2

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 CO-PSO Mapping

COs PSO1 PSO2 PSO3

1 3 1 -

2 3 1 -

3 2 1 -

4 3 1 -

5 3 1 -

AVERAGE 2.8 1 -

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 CO-PEO Mapping

COs PEO1 PEO2 PEO3 PEO4

1 3 1 - 1

2 3 1 - -

3 2 2 - -

4 2 2 - -

5 3 2 - 1

AVERAGE 2.6 1.6 -

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 Unit Contents

• SR,JK,D,T, Master – Slave JK Flip Flop

• Excitation and characteristics Table of all Flip Flops
• Conversion from one type of Flip-Flop to another
• Design and Operation of Asynchronous Counters
• Ripple, Synchronous Counter
• Shift Register
• Synchronous Modulo N –Counters

Dr. Akanksha Singh LDMC

04/20/2025 12
UNIT- 2
 Unit Objective

The intended objectives of this unit are:

1. To learn various flip flops and their specifications.

2. To differentiate between latches and flip flops.

3. To analyze and design synchronous sequential circuits.

4. To explain shift registers and counters.

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 Prerequisites/ Recap

• Boolean Algebra is used to analyze and simplify the digital (logic)

circuits.
• It uses only the binary numbers i.e. 0 and 1.
• It is also called as Binary Algebra or logical Algebra.
• Binary logic consists of binary variables and a set of logical
operations.
• Here variable having two and only two distinct possible values: 1
and 0.
• There are three basic logical operations: AND, OR, and NOT.

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 Topic Objective

Topic Objective Mapping

with CO
To understand basics of sequential circuits. CO2
To have a basic understanding of latches. CO2

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 Prerequisite

Prerequisite:
• Basic knowledge of logic gates.
• Knowledge of combinational circuits.

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 Introduction

Sequential Logic Representation

• The word “Sequential” means that things happen in a “sequence”, one
after another and in Sequential Logic circuits, the actual clock signal
determines when things will happen next.

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 Introduction

• It consists of a combinational circuit to which memory elements are

connected to form a feedback path.
• The memory elements are devices capable of storing binary
information within them. The binary information stored in the
memory elements at any given time defines the state of the sequential
circuit.
• The sequential circuit receives binary information from external
inputs. These inputs, together with the present state of the memory
elements, determine the binary value at the output terminals.
• Flip-flops, Latches and Counters and which themselves can be made
by simply connecting together universal NAND Gates and/or NOR
Gates in a particular combinational way to produce the required
sequential circuit.

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 Introduction

• There are two main types of sequential circuits. Their classification

depends on the timing of their signals.
• A synchronous sequential circuit is a system whose behaviour can be
defined from the knowledge of its signals at discrete instants of time.
• The behaviour of an asynchronous sequential circuit depends upon
the order in which its input signals change and can be affected at any
instant of time.
• The memory elements commonly used in asynchronous sequential
circuits are time-delay devices.
• The basic memory elements are latches and flip-flops. Latches are
level sensitive and flip-flops are edge sensitive.

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 Latches

• A Latch is a special type of logical circuit.

• The latches have low and high two stable states.
• A latch has a feedback path, so information can be retained by the
device. Therefore latches can be memory devices, and can store one
bit of data for as long as the device is powered.
• The latches can be constructed from two NAND gates or two NOR
gates.
Types of Latches:
• SR Latch.
• D Latch.
• J-K Latch.
• T Latch.

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 SR Latch

SR Latch using NOR Gate:

• SR latch stands for set/reset latch.
S R Qn+1 Q̅ n+1 Operation

0 0 Qn Q̅ n No change

0 1 0 1 Reset

1 0 1 0 Set

1 1 X X Invalid

• The cross-coupled connection from the output of one gate to the input
of the other gate constitutes a feedback path.
• Each latch has two outputs, Q and Q', and two inputs, set and reset.

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 SR Latch

Operation:
• If S = 1 and R = 0, Q becomes 1. Let us explain how.
• NOR gate always gives output 0 when at least one of the inputs is 1.
• So when S is applied as 1 the output of gate G2 i.e. is 0 irrespective
of the condition of second input Q to the gate.
• Now is the input of gate G1 so both the inputs of G1 become 0 as R
is already 0. So, the output of G1 is now or 1.
• So whatever may be the previous condition of Q, it always becomes
Q = 1 and Q’ = 0 when S = 1 and R = 0. This is called the SET
condition of the latch.

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 SR Latch

• If S = 0 and R = 1, Q becomes 0. Let us explain how.

• As we already said, a NOR gate always gives output 0 when at least
one of the inputs is 1.
• So when R is applied as 1, the output of gate G1 i.e. Q is 0
irrespective of the condition of the second input to the gate.
• So, whatever may be the previous condition of Q, it always becomes
0 this 0 is then fed back to the input of gate G2. As here S is already
0, both inputs of G2 are 0. Hence the output of G2 i.e. will be 1. So,
Q = 0 and Q’ = 1 when, S = 0 and R = 1. This is called the RESET
condition of the latch.

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 SR Latch

• If S = 0 and also R = 0, Q remains the same as it was.

• First suppose Q is previously 1.
• Now the inputs of G2 are 0 and 1 as S=0 and Q=1. So output of G2 is
0.
• Now both inputs of G1 are 0 as R=0 and Q’ =0. So the output of G1
is 1.
• Now suppose Q is previously 0.
• Now both inputs of G2 are 0 as S = 0 and Q = 0. So the output of G2
is 1.
• Now the inputs of G1 are 0 and 1 as R=0 and Q= 1. So the output of
G1 is 0.
• So it is proved that Q remains the same as it is when S = 0 and also R
= 0 in SR latch of flip flop.

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 SR Latch
• If S = 1 and also R = 1, the condition of Q is totally unpredictable. Let us
explain how.
• First suppose Q is previously 1.
• Now both inputs of G2 are 1 as S = 1 and Q = 1. So output of G2 is 0.
• Now the inputs of G1 are 1 and 0 as R = 1 and Q’ = 0. So the output of
G1 is 0. That means Q is changed.
• Now Q is 0. So inputs of G2 are 1 and 0 as S = 1 and Q = 0. So the
output of G2 is 0. That means is unchanged.
• Now the inputs of G1 are 1 and 0 as R = 1 and Q’ = 0. So the output of
G1 is 0. That means Q is unchanged.
• So, when both S and R are 1, it becomes unpredictable whether the value
of output Q will be changed or unchanged. This condition of SR latch
normally avoided. As the latch is SET when S = 1(HIGH), the latch is
called Active High SR Latch.

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 SR Latch

SR Latch using NAND Gate:

S R Qn+1 Q̅ n+1 Operation

0 0 X X Invalid

0 1 1 0 Set

1 0 0 1 Reset

1 1 Qn Q̅ n No change

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 Gated SR Latch

• A gated SR latch (or clocked SR Latch) can only change its output
state when there is an enabling signal along with required inputs. For
this reason it is also known as a synchronous SR latch
• In other words, the latch is active when ENABLE signal is HIGH and
it is inactive when ENABLE signal is LOW.

E S R Qn+1 Q̅ n+1 Operation

No
0 X X Qn Q̅ n
Change
No
1 0 0 Qn Q̅ n
Change

1 0 1 0 1 Reset

1 1 0 1 0 Set

1 1 1 X X Invalid

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 Latch

Difference between Level Triggering & Edge Triggering:

Level Triggering Edge Triggering
In level triggering the circuit will In edge triggering the circuit
become active when the gating becomes active at negative or
pulse is on a particular level. positive edge of the clock signal.

An event occurs during the high voltage An event occurs at the rising edge or falling
level or low voltage level. edge.

Latches are level triggered. Filp-flops are edge triggered.

Asynchronous Synchronous

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 Recap
• Sequential circuits consists of a combinational circuit to which
memory elements are connected to form a feedback path.
• The memory elements are devices capable of storing binary
information within them. The binary information stored in the
memory elements at any given time defines the state of the sequential
circuit.
• A latch has a feedback path, so information can be retained by the
device. Therefore latches can be memory devices, and can store one
bit of data for as long as the device is powered.
Types of Latches:
• SR Latch.
• D Latch.
• J-K Latch.
• T Latch.

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 Daily Quiz
• What do you understand by sequential circuit?
• Differentiate between combinational and sequential circuits.
• Draw & explain NAND SR latch.
• Draw & explain NOR SR latch.
• What is the use of enable signal in latch?

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 MCQ
• The truth table for an S-R latch has how many VALID entries?
a) 1
b) 2
c) 3
d) 4
• The logic circuits whose outputs at any instant of time depends only on the
present input but also on the past outputs are called
a) Combinational circuits
b) Sequential circuits
c) Latches
d) Flip-flops
• How many types of sequential circuits are?
a) 2 c) 4
b) 3 d) 5
• The sequential circuit is also called ___________
a) Flip-flop
b) Latch
c) Strobe
d) Adder
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 Video Link

• https://nptel.ac.in/courses/117/106/117106086/
• https://www.youtube.com/watch?v=jm0PGDSSBkI&ab_channel
=IITKharagpurJuly2018
• https://www.youtube.com/watch?v=ibQBb5yEDlQ&ab_channel
=nptelhrd

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 Questions

• Differentiate between combinational and sequential circuits.

• Differentiate between level triggering and edge triggering?

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 Recap of Previous Topic
• Sequential circuits consists of a combinational circuit to which
memory elements are connected to form a feedback path.
• The memory elements are devices capable of storing binary
information within them. The binary information stored in the
memory elements at any given time defines the state of the sequential
circuit.
• A latch has a feedback path, so information can be retained by the
device. Therefore latches can be memory devices, and can store one
bit of data for as long as the device is powered.
Types of Latches:
• SR Latch.
• D Latch.
• J-K Latch.
• T Latch.

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 Flip flops & Their Conversion

Topic Objective Mapping

with CO
To have a basic understanding of flip flops. CO2
To understand flipflop conversion. CO2

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 Flip flops & Their Conversion

Prerequisite:
• Basic knowledge of logic gates.
• Basic knowledge of latches.
• Knowledge of combinational circuits.

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 Flip Flop

• A Flip Flop is a memory element that is capable of storing one bit of

information.
• It is also called as Bistable Multivibrator since it has two stable states
either 0 or 1.
• There are following 4 basic types of flip flops-

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 SR Flip Flop
Construction of SR Flip Flop By Using NAND Latch-
This method of constructing SR Flip Flop uses-
• NAND latch
• Two NAND gates
Logic Circuit-
• The logic circuit for SR Flip Flop constructed using NAND latch is as
shown below:

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 SR Flip Flop

Truth Table of SR Flip-flop:

CLK S R Qn+1 Q̅ n+1 Operati
on
1 0 0 Qn Q̅ n No
Change
1 0 1 0 1 Reset

1 1 0 1 0 Set

1 1 1 X X Invalid

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 S R Flip Flop

• Characteristic Table :
Qn S R Qn+1
0 0 0 0
0 0 1 0
0 1 0 1
0 1 1 X
1 0 0 1
1 0 1 0
1 1 0 1
1 1 1 X

• Characteristic Equation of SR Flip-flop.

Qn+1 = S + Qn R̅
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 S R Flip Flop

• Excitation Table : For a given combination of present state Q n and

next state Qn+1, excitation table tell the inputs required.
• The excitation table of any flip flop is drawn using its characteristic
table.

Qn Qn+1 S R
0 0 0 x

0 1 1 0

1 0 0 1

1 1 x 0

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 SR Flip-Flop

Drawbacks of SR Flip Flop:

• The one major disadvantage of the S-R flip flop is that in the
condition when the clock is triggered the inputs become high which is
an undesirable condition because it causes invalid input ,the condition
in which you can't predict the output.
• So, in short we can say that the outputs in S-R flip flop are undefined
in that condition.
• JK flip flop is a refined & improved version of SR Flip Flop that has
been introduced to solve the problem of indeterminate state that
occurs in SR flip flop when both the inputs are 1.
• Input J behaves like input S of SR flip flop which was meant to set
the flip flop.
• Input K behaves like input R of SR flip flop which was meant to reset
the flip flop.

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 JK Flip Flop
Construction of JK Flip Flop By Using SR Flip Flop Constructed
From NAND Latch-
• This method of constructing JK Flip Flop uses-
• SR Flip Flop constructed from NAND latch
• Two other connections
Logic Circuit-
• The logic circuit for JK Flip Flop constructed using SR Flip Flop
constructed from NAND latch is as shown below:
CLK J K Qn+1 Q̅ n+1 Operation
0 X X Qn Q̅ No Change
n
1 0 0 Qn Q̅ No change
n
1 0 1 0 1 Reset
1 1 0 1 0 Set
1 1 1 Q̅ Qn Toggle
n

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 JK Flip Flop

Characteristics Table
• The truth table for JK Flip Flop is as shown below

INPUTS OUTPUTS

Qn+1
Qn J K
(Next State)
0 0 0 0
0 0 1 0
0 1 0 1 Qn+1 = Q̅ nJ + Qn K̅
0 1 1 1
1 0 0 1
1 0 1 0
1 1 0 1
1 1 1 0

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 JK Flip Flop

Excitation Table-
• For a given combination of present state Q n and next state Qn+1,
excitation table tell the inputs required.
• The excitation table of any flip flop is drawn using its truth table.

Qn Qn+1 J K
0 0 0 X

0 1 1 X

1 0 X 1

1 1 X 0

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 JK Flip Flop
Differences between J K Flip Flop and S R Flip Flop
• Both JK flip flop and SR flip flop are functionally same.
• The only difference between them is-
• In JK flip flop, indeterminate state does not occur.
• In JK flip flop, instead of indeterminate state, the present state
toggles.
• In other words, the present state gets inverted when both the inputs
are 1.

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 JK Flip Flop
Drawbacks of JK Flip Flop (Race around condition)
• The main drawback of the JK flip flop is the race around
condition.
• It happens when both the input is 1.
• In race around condition output toggles more than one time.
• If that happens it will be very hard to predict the state of the flip
flop.
• Assume present state is 1 and we are applying J=1 and K=1. what
will happen the output toggles next state should be 0.
• But what happens in real scenario the output will not ended up
getting 0 it will continues to toggle 0101010101010 it will go like
that.

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 JK Flip Flop
• Race Around Condition In JK Flip-flop – For J-K flip-flop, if
J=K=1, and if CLK=1 for a long period of time, then Q output will
toggle as long as CLK is high, which makes the output of the flip-flop
unstable or uncertain. This problem is called race around condition in
J-K flip-flop.

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 JK Flip Flop
There are three methods to eliminate race around condition as
described below:
• Increasing the delay of flip-flop
• The propagation delay (delta t) should be made greater than the
duration of the clock pulse (T). But it is not a good solution as
increasing the delay will decrease the speed of the system.
• Use of edge-triggered flip-flop
• If the clock is High for a time interval less than the propagation
delay of the flip flop then racing around condition can be
eliminated. This is done by using the edge-triggered flip flop rather
than using the level-triggered flip-flop.
• Use of master-slave JK flip-flop
• If the flip flop is made to toggle over one clock period then racing
around condition can be eliminated. This is done by using Master-
Slave JK flip-flop.

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 D Flip Flop

• The D stands for "data"; this flip-flop stores the value that is on the
data line.
• It can be thought of as a basic memory cell.
• A D flip-flop can be made from a set/reset flip-flop by tying the set to
the reset through an inverter.
• One of the salient features of a D-type flip-flop is its ability to "latch"
and store and remember data.
• This property is used in creating a delay in progress of the data in the
circuit used.
• There are several applications in which a D-type flip-flop is used,
such as in frequency dividers and data latches.

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 D Flip Flop

Logic Circuit:
• The circuit diagram of D flip – flop is shown in below figure.

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 D Flip Flop

• Characteristic table : Excitation Table :

Qn Qn+1 D

0 0 0

0 1 1

1 0 0

1 1 1

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 T Flip Flop

• The T or "toggle" flip-flop changes its output on each clock edge,

giving an output which is half the frequency of the signal to the T
input.
• It is useful for constructing binary counters, frequency dividers, and
general binary addition devices.
• It can be made from a J-K flip-flop by tying both of its inputs high.
Construction
• We can construct a T flip – flop by connecting AND gates as input to
the NOR gate SR latch.
• These AND gate inputs are fed back with the present state output Q
and its complement Q’ to each AND gate.
• A toggle input (T) is connected in common to both the AND gates as
an input.

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 T Flip Flop

Logic Diagram :

CLK T Qn+1 Q̅ Operation

n+1

0 X Qn Q̅ No Change
n

1 0 Qn Q̅ No Change
n

1 1 Q̅ Qn Toggle
n

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 T Flip Flop

• Characteristic Equation

Qn T Qn+1
0 0 0

0 1 1

1 0 1

1 1 0

Qn+1 = T̅ Qn + T Q̅ n
• Excitation Table

Qn Qn+1 T

0 0 0

0 1 1

1 0 1

1 1 0

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 Master Slave J K Flip Flop

• The Master-Slave Flip-Flop is basically a combination of two JK flip-

flops connected together in a series configuration.
• Out of these, one acts as the “master” and the other as a “slave”.
• The output from the master flip flop is connected to the two inputs of
the slave flip flop whose output is feedback to inputs of the master
flip flop.
• In addition to these two flip-flops, the circuit also includes
an inverter.
• The inverter is connected to clock pulse in such a way that the
inverted clock pulse is given to the slave flip-flop.
• In other words if CLK=0 for a master flip-flop, then CLK=1 for a
slave flip-flop and if CLK=1 for master flip flop then it becomes 0 for
slave flip flop.

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 Master Slave J K Flip Flop

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 Master Slave J K Flip Flop
• Timing diagram for master slave flip-flop :

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 Recap of Previous Topic

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 Daily Quiz
• Differentiate between latches & flipflops.
• For the clocked SR flip-flop write the state table, draw the state
diagram and the state equation.
• What are the different types of flipflops?
• Explain Master slave flipflop.
• Explain race around condition.

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 MCQ
1. When both inputs of a J-K flip-flop cycle, the output will ___________
a) Be invalid
b) Change
c) Not change
d) Toggle
2. Which of the following is correct for a gated D-type flip-flop?
a) The Q output is either SET or RESET as soon as the D input goes
HIGH or LOW
b) The output complement follows the input when enabled
c) Only one of the inputs can be HIGH at a time
d) The output toggles if one of the inputs is held HIGH
3. A basic S-R flip-flop can be constructed by cross-coupling of which
basic logic gates?
a) AND or OR gates
b) XOR or XNOR gates
c) NOR or NAND gates
d) AND or NOR gates

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 Old Questions

• What is difference between flip flop and latches?

• What is race around condition?
• For the clocked JK flip-flop write the state table, draw the state
diagram and the state equation.
• What are the different types of flipflops?

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 Flip Flop

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 Conversion of flip-flops

We can convert one flip-flop into the remaining three flip-flops by

including some additional logic. So, there will be total of twelve flip-
flop conversions.
Follow these steps for converting one flip-flop to the other.
• Write characteristic table of desired flip-flop.
• Write the excitation table of given flip-flop.
• Using the excitation table of given flip-flop and given inputs
by taking present state and next state of desired flip-flop.
• Simplify the logic expression using k-map for excitation
inputs of given flip-flops.
• Draw a circuit using the above expression.

04/20/2025 Dr. Akanksha Singh LDMC UNIT- 2 64

 Conversion of flip-flops
Eg. Covert JK flip-flop to T flip-flop.

Qn T Qn+1 Qn Qn+1 J K
0 0 0 X
0 0 0
0 1 1 X
0 1 1
1 0 X 1
1 0 1
1 1 X 0
1 1 0

Using the above excitation table find inputs J & K by taking present
state and next state of T flip flop.

T Qn Qn+1 J K
0 0 0 0 X

0 1 1 X 0

1 0 1 1 X

1 1 0 X 1

04/20/2025 Dr. Akanksha Singh LDMC UNIT- 2 65

 Conversion of flip-flops

04/20/2025 Dr. Akanksha Singh LDMC UNIT- 2 66

 Conversion of flip-flops
Eg. Covert T flip-flop to D flip-flop.

Qn D Qn+1 Qn Qn+1 T
0 0 0
0 0 0
0 1 1
0 1 1
1 0 1
1 0 0
1 1 0
1 1 1

Using the above excitation table find inputs T by taking present state
and next state of D flip flop.
Q
D Qn+1 T
n
0 0 0 0

0 1 1 1

1 0 0 1

1 1 1 0
04/20/2025 Dr. Akanksha Singh LDMC UNIT- 2 67
 Conversion of flip-flops
Eg. Covert T flip-flop to D flip-flop.

04/20/2025 Dr. Akanksha Singh LDMC UNIT- 2 68

 Video Link

• https://nptel.ac.in/courses/117/106/117106086/
• https://www.youtube.com/watch?v=2ecMG_OciLo&ab_channel
=nptelhrdnptelhrd
• https://www.youtube.com/watch?v=2ecMG_OciLo&ab_channel
=nptelhrdnptelhrd

04/20/2025 Dr. Akanksha Singh LDMC UNIT- 2 69

 Daily Quiz
• Differentiate between latches & flipflops.
• Write and explain steps of flip flop conversion.
• What are the different types of flipflops?
• Explain Master slave flipflop.

04/20/2025 Dr. Akanksha Singh LDMC UNIT- 2 70

 Video Link

• https://nptel.ac.in/courses/117/106/117106086/
• https://www.youtube.com/watch?v=2ecMG_OciLo&ab_channel
=nptelhrdnptelhrd
• https://www.youtube.com/watch?v=2ecMG_OciLo&ab_channel
=nptelhrdnptelhrd

04/20/2025 Dr. Akanksha Singh LDMC UNIT- 2 71

 MCQ
1. To design a synchronous sequential circuit with 9 states how many
flip flops are required?
a) 4 c) 5
b) 9 d) 3
2. Following flip flop is used to eliminate race around condition:
c) JK flip flop
d) Master slave JK flip flop
e) SR flip flop
f) T flip flop
3. The flip flop is only activated by:
g) Positive edge triggering
h) Negative edge triggering
i) Either positive or negative edge triggering

04/20/2025 Dr. Akanksha Singh LDMC UNIT- 2 72

 Old Questions

• Realize
i. A JK flip flop using SP flip flop.
ii. A SR using NAND gates and explain its operation.

04/20/2025 Dr. Akanksha Singh LDMC UNIT- 2 73

 Weekly Assignment

• What is race around condition? How to eliminate race around

condition?
• Draw and explain master slave flip flop.
• Realize D flip flop using T flip flop.
• Realize a T flip flop using SR flip flop.

04/20/2025 Dr. Akanksha Singh LDMC UNIT- 2 74

 Recap of Previous Topic
• A Flip Flop is a memory element that is capable of storing one bit of
information.
• It is also called as Bistable Multivibrator since it has two stable states
either 0 or 1.
• There are following 4 basic types of flip flops- SR, JK, T, D.
• The main drawback of the JK flip flop is the race around condition.
• It happens when both the input is 1.
• In race around condition output toggles more than one time.
• Master slave flip flop is used to eliminate this condition.

04/20/2025 Dr. Akanksha Singh LDMC UNIT- 2 75

 Types of sequential circuits

Topic Objective Mapping with

CO
To have a basic understanding of asynchronous and CO2
synchronous sequential circuits.

04/20/2025 Dr. Akanksha Singh LDMC UNIT- 2 76

 Types of sequential circuits

Prerequisite:
• Basic knowledge of latches & flip flops.

04/20/2025 Dr. Akanksha Singh LDMC UNIT- 2 77

 Types of sequential circuits
Types of Sequential Circuits
• Following are the two types of sequential circuits −
• Asynchronous sequential circuits
• Synchronous sequential circuits
• Asynchronous sequential circuits
• If some or all the outputs of a sequential circuit do not change affect with
respect to active transition of clock signal, then that sequential circuit is
called as Asynchronous sequential circuit. That means, all the outputs
of asynchronous sequential circuits do not change affect the same time.

04/20/2025 Dr. Akanksha Singh LDMC UNIT- 2 78

 Types of sequential circuits
Synchronous sequential circuits
• If all the outputs of a sequential circuit change affect with respect to
active transition of clock signal, then that sequential circuit is called
as Synchronous sequential circuit. That means, all the outputs of
synchronous sequential circuits change affect at the same time.

04/20/2025 Dr. Akanksha Singh LDMC UNIT- 2 79

 Types of sequential circuits

04/20/2025 Dr. Akanksha Singh LDMC UNIT- 2 80

 Video Links

• https://www.youtube.com/watch?v=AkO20k_my6k&ab_channel=Nes
oAcademyNesoAcademyVerified
• https://www.youtube.com/watch?v=Qa6csfkK7_I&ab_channel=Neso
Academy
• https://www.youtube.com/watch?v=0_OZKWdCixw&ab_channel=N
esoAcademy

04/20/2025 Dr. Akanksha Singh LDMC UNIT- 2 81

 Daily Quiz

• How many types of sequential circuits are?

a) 2
b) 3
c) 4
d) 5
• The sequential circuit is also called ___________
a) Flip-flop
b) Latch
c) Strobe
d) Adder

04/20/2025 Dr. Akanksha Singh LDMC UNIT- 2 82

 Recap of Previous Topic
• Following are the two types of sequential circuits −Asynchronous
sequential circuits, Synchronous sequential circuits
• If some or all the outputs of a sequential circuit do not
change affect with respect to active transition of clock signal, then
that sequential circuit is called as Asynchronous sequential
circuit.
• If all the outputs of a sequential circuit change affect with respect
to active transition of clock signal, then that sequential circuit is
called as Synchronous sequential circuit.
• The finite state machines are classified into two types such as Mealy
state machine and Moore state machine.
• When the outputs depend on the current inputs as well as states, then
the FSM can be named to be a mealy state machine.

04/20/2025 Dr. Akanksha Singh LDMC UNIT- 2 83

 Design of Sequential Circuits

Topic Objective Mapping with

CO
To design clocked synchronous sequential circuits. CO3

04/20/2025 Dr. Akanksha Singh LDMC UNIT- 2 84

 Design of Sequential Circuits

Prerequisite:
• Basic knowledge of latches & flip flops.

04/20/2025 Dr. Akanksha Singh LDMC UNIT- 2 85

 Design of Sequential Circuits

Design of Sequential Circuits

• The design of a synchronous sequential circuit starts from a set of
specifications in a logic diagram or a list of Boolean functions from
which a logic diagram can be obtained. In contrast to a combinational
logic, which is fully specified by a truth table, a sequential circuit
requires a state table for its specification. The first step in the design of
sequential circuits is to obtain a state table or an equivalence
representation, such as a state diagram.
• A synchronous sequential circuit is made up of flip-flops and
combinational gates. The design of the circuit consists of choosing the
flip-flops and then finding the combinational structure which, together
with the flip-flops, produces a circuit that fulfils the required
specifications. The number of flip-flops is determined from the number
of states needed in the circuit.

04/20/2025 Dr. Akanksha Singh LDMC UNIT- 2 86

 Design of Sequential Circuits
Example 1: Design a synchronous sequential circuit whose state diagram is
shown in Figure. The type of flip-flop to be use is J-K.

• From the state diagram, we can generate the state table shown in Table. Note
that there is no output section for this circuit. Two flip-flops are needed to
represent the four states and are designated Q0Q1. The input variable is
assumed as x.
04/20/2025 Dr. Akanksha Singh LDMC UNIT- 2 87
 Design of Sequential Circuits

State Table is derived from the state diagram

04/20/2025 Dr. Akanksha Singh LDMC UNIT- 2 88

 Design of Sequential Circuits

We shall now derive the excitation table and the combinational

structure. The table is now arranged in a different form where the
present state and input variables are arranged in the form of a
truth table.

Qn Qn+1 J K
0 0 0 X
0 1 1 X

1 0 X 1

1 1 X 0

Excitation Table of JK flipflop

04/20/2025 Dr. Akanksha Singh LDMC UNIT- 2 89

 Design of Sequential Circuits

The combined table from the state table and excitation table is:

Present state Next state

Qn Qn+1 J K
Q0Q1 X=0 X=1 0 0 0 X
00 00 01 0 1 1 X

01 10 01 1 0 X 1
10 10 11
1 1 X 0
11 11 00

04/20/2025 Dr. Akanksha Singh LDMC UNIT- 2 90

 Design of Sequential Circuits
The simplified Boolean functions for the combinational circuit can now
be derived. The input variables are Q0, Q1, and x; the output are the
variables J0, K0, J1 and K1. The information from the truth table is
plotted on the Karnaugh maps shown in Figure

• The flip-flop input functions are derived:

04/20/2025 Dr. Akanksha Singh LDMC UNIT- 2 91

 Design of Sequential Circuits
• The logic diagram can be drawn from the given boolean equations:

04/20/2025 Dr. Akanksha Singh LDMC UNIT- 2 92

 Design of Sequential Circuits
Example 2: Design a synchronous sequential circuit whose state table is
shown in Figure. The type of flip-flop to be use is D.

• As we have to use D flip-flop, the excitation table of D Flip-flop is:

Qn Qn+1 D
0 0 0

0 1 1

1 0 0

1 1 1

04/20/2025 Dr. Akanksha Singh LDMC UNIT- 2 93

 Design of Sequential Circuits

The combined table from the state table and excitation table is:

Qn Qn+1 D
0 0 0
0 1 1
1 0 0
1 1 1

04/20/2025 Dr. Akanksha Singh LDMC UNIT- 2 94

 Design of Sequential Circuits
The simplified Boolean functions for the combinational circuit can now
be derived. The input variables are Q0, Q1, and x; the output are the
variables J0, K0, J1 and K1. The information from the truth table is
plotted on the Karnaugh maps shown in Figure

• The flip-flop input functions are derived:

04/20/2025 Dr. Akanksha Singh LDMC UNIT- 2 95

 Design of Sequential Circuits
• The logic diagram can be drawn from the given boolean equations:

04/20/2025 Dr. Akanksha Singh LDMC UNIT- 2 96

 Daily Quiz
• The table consists of present state and next state at input side and
flipflop inputs at output side of the table is called:
a) Truth Table
b) Characteristic table
c) Excitation table.
• Characteristics equation of S_R flip flop is:
a) Qn+1 = S + R Qn
b) Qn+1 = S' + R Qn
c) Qn+1 = S + R'Qn
d) Qn+1 = S'+ R'Qn
• What you understand by the term state table and state diagram?

04/20/2025 Dr. Akanksha Singh LDMC UNIT- 2 97

 Old Questions

• Write the basic steps for designing of clock sequential synchronous

circuit.
• Design a sequential circuit with two flip flop A and B and one input x.
When x=0 the state of the circuit remains the same when x = 1 the
circuit passes through the state transition from 00 to 01 to 11 to 10
and back to 00 and repeat.
• Design a sequential circuit for a given state diagram

04/20/2025 Dr. Akanksha Singh LDMC UNIT- 2 98

 Video Link

• https://nptel.ac.in/courses/117/106/117106086/
• https://www.youtube.com/watch?v=OGgLiGXHrsw&ab_channe
l=RajaramStudy
• https://www.youtube.com/watch?v=NbON135lf60&ab_channel
=NesoAcademy

04/20/2025 Dr. Akanksha Singh LDMC UNIT- 2 99

 Weekly Assignment

• Consider the following circuit involving three D-

type flip-flops used in a certain type of counter
configuration.

• Design a sequential circuit for the given state diagram using JK flip
flops.

04/20/2025 Dr. Akanksha Singh LDMC UNIT- 2 100

 Recap
• The design of a synchronous sequential circuit starts from a set
of specifications in a logic diagram or a list of Boolean
functions from which a logic diagram can be obtained.
• The first step in the design of sequential circuits is to obtain a
state table or an equivalence representation, such as a state
diagram.
• A synchronous sequential circuit is made up of flip-flops and
combinational gates.
• The design of the circuit consists of choosing the flip-flops and
then finding the combinational structure which, together with
the flip-flops, produces a circuit that fulfils the required
specifications.
• The number of flip-flops is determined from the number of
states needed in the circuit.

04/20/2025 Dr. Akanksha Singh LDMC UNIT- 2 101

 Counters

Topic Objective Mapping with

CO
To design asynchronous and synchronous counter. CO3

04/20/2025 Dr. Akanksha Singh LDMC UNIT- 2 102

 Counters

Prerequisite:
• Basic knowledge of designing of synchronous sequential circuits.

04/20/2025 Dr. Akanksha Singh LDMC UNIT- 2 103

 Counters

• Counter is a sequential circuit. A digital circuit which is used for a

counting pulses is known counter. Counter is the widest application of
flip-flops. It is a group of flip-flops with a clock signal applied.
Counters are of two types depending upon clock pulse applied.
• Asynchronous or ripple counters.
• Synchronous counters
• In Asynchronous Counter is also known as Ripple Counter, different
flip flops are triggered with different clock, not simultaneously. While
in Synchronous Counter, all flip flops are triggered with same clock
simultaneously and Synchronous Counter is faster than asynchronous
counter in operation.

04/20/2025 Dr. Akanksha Singh LDMC UNIT- 2 104

 Counters

Synchronous counter Asynchronous counter

• In synchronous counter, all flip flops are • In asynchronous counter, different flip
triggered with same clock simultaneously. flops are triggered with different clock,
• Synchronous Counter is faster than not simultaneously.
asynchronous counter in operation. • Asynchronous Counter is slower than
• Synchronous Counter does not produce any synchronous counter in operation.
decoding errors. • Asynchronous Counter produces
• Synchronous Counter is also called Parallel decoding error.
Counter. • Asynchronous Counter is also called
• Synchronous Counter designing as well Serial Counter.
implementation are complex due to • Asynchronous Counter designing as
increasing the number of states. well as implementation is very easy.
• Synchronous Counter will operate in any • Asynchronous Counter will operate
desired count sequence. only in fixed count sequence
• Synchronous Counter examples are: Ring (UP/DOWN).
counter, Johnson counter. • Asynchronous counter examples
• In synchronous counter delay is less. are: Ripple UP counter, Ripple DOWN
counter.
• In asynchronous counter, there is high
propagation delay.
04/20/2025 Dr. Akanksha Singh LDMC UNIT- 2 105
 Ripple Counter

3 bit or MOD 8 Ripple Counter

• In asynchronous counter we don’t use universal clock, only first flip flop is
driven by main clock and the clock input of rest of the following flip flop is
driven by output of previous flip flops.
• N ≤ 2n , where N is no of states and n is no of flip-flops.
N = 8 so no of flip flops is 3.

04/20/2025 Dr. Akanksha Singh LDMC UNIT- 2 106

 Ripple Counter

04/20/2025 Dr. Akanksha Singh LDMC UNIT- 2 107

 Ripple Counter

4 bit down Ripple Counter

• N ≤ 2n , where N is no of states and n is no of flip-flops.
no of flip flops is 4 the states at which the counter counts is 16.

04/20/2025 Dr. Akanksha Singh LDMC UNIT- 2 108

 Ripple Counter

4 bit down Ripple Counter

04/20/2025 Dr. Akanksha Singh LDMC UNIT- 2 109

 Ripple Counter

4 bit up counter using positive clock edge :

04/20/2025 Dr. Akanksha Singh LDMC UNIT- 2 110

 UP/DOWN Counter

• Both Synchronous and Asynchronous counters are capable of counting

“Up” or counting “Down”, but their is another more “Universal” type of
counter that can count in both directions either Up or Down depending
on the state of their input control pin and these are known
as Bidirectional Counters.
• Bidirectional counters, also known as Up/Down counters, are capable of
counting in either direction through any given count sequence and they
can be reversed at any point within their count sequence by using an
additional control input as shown below.

04/20/2025 Dr. Akanksha Singh LDMC UNIT- 2 111

 UP/DOWN Counter

04/20/2025 Dr. Akanksha Singh LDMC UNIT- 2 112

 Synchronous Counter

Synchronous counters :
Counter is clocked such that all the flip-flops are clocked simultaneously,
so that all the flip-flops change their output state at a same time. So the
speed of operation is increased.
Synchronous counter Design
1. Find the no flip-flops required
2. Write count sequence in tabular form
3. Draw excitation table for flip-flop inputs
4. Prepare k-map for each flip-flop inputs
5. Connect the circuit using flip-flops and other logical gates.

04/20/2025 Dr. Akanksha Singh LDMC UNIT- 2 113

 Synchronous Counter

Example: Design a 3 bit synchronous counter using T flip-flops.

Solution: For 3 bit counter state diagram is

04/20/2025 Dr. Akanksha Singh LDMC UNIT- 2 114

 Synchronous Counter
• Now from the state diagram draw the state table:

04/20/2025 Dr. Akanksha Singh LDMC UNIT- 2 115

 Synchronous Counter
• Next step is to transfer the flip-flop input functions to Karnaugh maps to
derive a simplified Boolean expressions

04/20/2025 Dr. Akanksha Singh LDMC UNIT- 2 116

 Synchronous Counter
• The boolean expressions are obtained from K Map

04/20/2025 Dr. Akanksha Singh LDMC UNIT- 2 117

 Synchronous Counter
• From the boolean expressions circuit diagram can be drawn:

04/20/2025 Dr. Akanksha Singh LDMC UNIT- 2 118

 Synchronous Counter
• Timing diagrams:

04/20/2025 Dr. Akanksha Singh LDMC UNIT- 2 119

 Ring Counters

• A ring counter has one of its outputs connect back to the input.
It is thus making a ring. There are two types of ring counters.
• Straight ring counter – The non-inverting output (Q) of the last
flip-flop is connected to the first flip-flop.
• Johnson ring counter/Twisted ring counter – The inverting
output of the last flip-flop is connected to the first flip-flop.

04/20/2025 Dr. Akanksha Singh LDMC UNIT- 2 120

 Ring Counters

4 bit ring counter

04/20/2025 Dr. Akanksha Singh LDMC UNIT- 2 121

 Ring Counters

Advantages and disadvantages of a ring counter:

• A small advantage of a ring counter is that it has an automatically
decoded output. However, ring counters have a major disadvantage
because they need to be initialized. A number needs to be loaded to
the ring counter before the start of the counting process. We had not
seen this with any other counter yet. Another disadvantage is that only
N states are present compared to the states of the binary counters.

04/20/2025 Dr. Akanksha Singh LDMC UNIT- 2 122

 Johnson Counters
Johnson Counters:
• In Johnson ring counter the inverted output of the last flip-flop is
connected to the input of the first flip-flop. The only difference
between the straight ring counter and the Johnson counter is that in
the Johnson counter the inverted output of the last flip-flop (as
opposed to the non-inverted output in the straight ring counter) is
connected as the input to the first flip-flop. Johnson counter is also
called the twisted-ring counter or switch-tail ring counter.

04/20/2025 Dr. Akanksha Singh LDMC UNIT- 2 123

 Johnson Counters
Truth Table of Johnson ring counter

• The truth table starts from 0000. This means that it is self-actuating.
• The Johnson counter does not need any input. Moreover, a Johnson counter
has more states than a straight ring counter. A binary counter has states, a
straight ring counter has N states, and a Johnson ring counter has 2N states.

04/20/2025 Dr. Akanksha Singh LDMC UNIT- 2 124

 Johnson Counters

Advantages / Disadvantages of Johnson Counter

Advantages
• More outputs as compared to ring counter.
• It has same number of flip flop but it can count twice the number of states
the ring counter can count.
• It only needs half the number of flip-flops compared to the standard ring
counter for the same MOD
• Disadvantages
• Only 8 of the 15 states are being used.
• It doesn’t count in a binary sequence.

04/20/2025 Dr. Akanksha Singh LDMC UNIT- 2 125

 Recap
• Counter is a sequential circuit. A digital circuit which is used for a
counting pulses is known counter. Counter is the widest application of
flip-flops. It is a group of flip-flops with a clock signal applied.
Counters are of two types depending upon clock pulse applied.
• Asynchronous or ripple counters.
• Synchronous counters
• In Asynchronous Counter is also known as Ripple Counter, different
flip flops are triggered with different clock, not simultaneously. While
in Synchronous Counter, all flip flops are triggered with same clock
simultaneously and Synchronous Counter is faster than asynchronous
counter in operation
• In Johnson ring counter the inverted output of the last flip-flop is
connected to the input of the first flip-flop.
• Ring counters are basically a type of counter in which the output of
the most significant bit is fed back as an input to the least significant
bit.
04/20/2025 Dr. Akanksha Singh LDMC UNIT- 2 126
 Video Links

• https://www.youtube.com/watch?v=32v8s0R0qIk&ab_channel=
TutorialsPoint%28India%29Ltd.TutorialsPoint%28India%29Lt
d.Verified
• https://nptel.ac.in/courses/117/106/117106086/

04/20/2025 Dr. Akanksha Singh LDMC UNIT- 2 127

 Daily Quiz

• To design a synchronous counter with 9 states how many flip flops are
required?
a) 4 c) 5
b) 9 d) 3
• In a 4-bit Johnson counter sequence, there are a total of how many states or
bit patterns?
a) 1
b) 3
c) 4
d) 8
• What do you understand by ring counter?
• If a 10-bit ring counter has an initial state 1101000000, what is the state after
the second clock pulse?
a) 1101000000
b) 0011010000
c) 1100000000
d) 0000000000
04/20/2025 Dr. Akanksha Singh LDMC UNIT- 2 128
 Old Questions

• What are the differences between synchronous and asynchronous

counter?
• Design a 4 bit synchronous counter using D flip flop.
• Design MOD 3 UP/DOWN synchronous counter.
• Explain 4bit Johnson counter with circuit diagram and waveforms.

04/20/2025 Dr. Akanksha Singh LDMC UNIT- 2 129

 Shift Registers

Topic Objective Mapping with

CO
To Explain shift registers. CO3

04/20/2025 Dr. Akanksha Singh LDMC UNIT- 2 130

 Shift Register

Prerequisite:
• To have a basic understanding of Flip flops.

04/20/2025 Dr. Akanksha Singh LDMC UNIT- 2 131

 Shift Register

• Shift Registers are sequential logic circuits, capable of storage and

transfer of data.
• This sequential device loads the data present on its inputs and then
moves or “shifts” it to its output once every clock cycle, hence the
name Shift Register.
• A shift register basically consists of several single bit “D-Type Data
Latches”, one for each data bit, either a logic “0” or a “1”, connected
together in a serial type chain arrangement so that the output from one
data latch becomes the input of the next latch and so on.

04/20/2025 Dr. Akanksha Singh LDMC UNIT- 2 132

 Shift Register
Types of Shift Registers
Generally, shift registers operate in one of four different modes
with the basic movement of data through a shift register being:
• Serial-in to Parallel-out (SIPO) - the register is loaded with
serial data, one bit at a time, with the stored data being
available at the output in parallel form.
• Serial-in to Serial-out (SISO) - the data is shifted serially “IN”
and “OUT” of the register, one bit at a time in either a left or
right direction under clock control.
• Parallel-in to Serial-out (PISO) - the parallel data is loaded into
the register simultaneously and is shifted out of the register
serially one bit at a time under clock control.
• Parallel-in to Parallel-out (PIPO) - the parallel data is loaded
simultaneously into the register, and transferred together to
their respective outputs by the same clock pulse.
04/20/2025 Dr. Akanksha Singh LDMC UNIT- 2 133
 Shift Register

Serial in - Serial out Shift Registers

• The SISO shift register is one of the simplest of the four configurations as
it has only three connections, the serial input (SI) which determines
what enters the left hand flip-flop, the serial output (SO) which is taken
from the output of the right hand flip-flop and the sequencing clock
signal (Clk). The logic circuit diagram below shows a generalized serial-in
serial-out shift register.

04/20/2025 Dr. Akanksha Singh LDMC UNIT- 2 134

 Shift Register

Serial in - Serial out Shift Registers

04/20/2025 Dr. Akanksha Singh LDMC UNIT- 2 135

 Shift Register

Serial in – Parallel out Shift Register

• These types of shift registers are used for the conversion of
data from serial to parallel.
• A 4-bits serial in – Parallel out shift register is illustrated in the
Image below.

• Lets assume that all the flip-flops ( FFA to FFD ) have just been
RESET ( CLEAR input ) and that all the outputs QA to QD are at
logic
04/20/2025level “0” ie, noDr.
parallel
Akanksha Singhdata output.
LDMC UNIT- 2 136
 Shift Register

The serial data 1011 pattern presented at the SI input. This data is
synchronized with the clock CLK.

04/20/2025 Dr. Akanksha Singh LDMC UNIT- 2 137

 Shift Register

Parallel in – Serial out Shift Register

• For this type of shift register, the data is supplied in parallel.
• As this type of shift register converts parallel data, such as an 8-bit data
word into serial format, it can be used to multiplex many different
input lines into a single serial DATA stream which can be sent directly
to a computer or transmitted over a communications line

04/20/2025 Dr. Akanksha Singh LDMC UNIT- 2 138

 Shift Register

Parallel in – Parallel out shift register

• For parallel in – parallel out shift register, the output data
across the parallel outputs appear simultaneously as the input
data is fed in.

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 Shift Register

Bidirectional Shift Registers

• If we shift a binary number to the left by one position, it is equivalent to
multiplying the number by 2 and if we shift a binary number to the right
by one position, it is equivalent to dividing the number by 2.To perform
these operations we need a register which can shift the data in either
direction.
• Bidirectional shift registers are the registers which are capable of shifting
the data either right or left depending on the mode selected. If the
mode selected is 1(high), the data will be shifted towards the right
direction and if the mode selected is 0(low), the data will be shifted
towards the left direction.
• In right shift operations, the binary data is divided by two. If this
operation is reversed, the binary data gets multiplied by two.
• A couple of NAND gates are configured as OR gates and are used to
control the direction of shift, either right or left.

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 Shift Register

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 Shift Register

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 Universal shift register

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 Recap

• Shift Registers are sequential logic circuits, capable of storage and

transfer of data.
• A shift register basically consists of several single bit “D-Type Data
Latches”, one for each data bit, either a logic “0” or a “1”, connected
together in a serial type chain arrangement so that the output from one
data latch becomes the input of the next latch and so on.
Types of Shift Registers
Generally, shift registers operate in one of four different modes with
the basic movement of data through a shift register being:
• Serial-in to Parallel-out (SIPO)
• Serial-in to Serial-out (SISO)
• Parallel-in to Serial-out (PISO)
• Parallel-in to Parallel-out (PIPO)

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 Daily Quiz
• A bidirectional 4-bit shift register is storing the nibble 1110. Its input is LOW. The
nibble 0111 is waiting to be entered on the serial data-input line. After two clock
pulses, the shift register is storing
a) 1110
b) 0111
c) 1000
d) 1001
• In a parallel in/parallel out shift register, D0 = 1, D1 = 1, D2 = 1, and D3 = 0. After
three clock pulses, the data outputs are ________
a) 1110
b) 0001
c) 1100
d) 1000
• The group of bits 10110111 is serially shifted (right-most bit first) into an 8-bit
parallel output shift register with an initial state 11110000. After two clock pulses, the
register contains ______________
a) 10111000
b) 10110111
c) 11110000
d) 11111100

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 Old Questions

• What are the differences between synchronous and

asynchronous counter?
• What do you mean by shift register? What is need of shift
register? Draw & explain bidirectional shift register.
• Draw & explain universal shift register.

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 Weekly Assignment

• What are the differences between synchronous and

asynchronous counter?
• Design MOD-5 ring counter & MOD -5 Johnson counter.
• What do you mean by shift register? What is need of shift
register? Draw & explain bidirectional shift register.
• Design MOD-5 asynchronous counter.
• Design MOD 3 UP/DOWN synchronous counter.
• Explain 4bit Johnson counter with circuit diagram and
waveforms. 10
• Design a 4 bit synchronous counter using D flip flop.

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 Video Link

• https://www.youtube.com/watch?v=Iecj9xmIfXM&ab_channel=
nptelhrd
• https://nptel.ac.in/courses/117/106/117106086/

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 Glossary Questions
• A synchronous sequential circuits is one in which the contents of the memory
can change only at discrete instants time or on the of transitions of a clock.
Since all the circuit action will take place under the control of a clock, so
these circuits are known as clocked sequential circuit. An asynchronous
sequential logic circuits is one whose outputs can change state at any instant
of time with the change of one or more of the inputs. The memory elements
used in these systems are delay type memory elements. It can be regarded as
combinational circuit with feed back. Flip-flops (FF) A FF is an electronic
device that has two stable states. One state is assigned the logic 1 value and
the other is the logic 0. In other words, the memory elements used in
sequential circuits are the flip flop. These circuits are binary cells capable of
storing one bit of information. A latch is a bistable circuit that is the
fundamental building block of a flip-flop. It exists in one of the two states
(e.g. 1 and 0), and in the absence of the input, it remains in that state. It has
two output y and y'.
1. List some of the advantages of synchronous sequential logic circuit.

2. Distinguish between combinational and sequential Logic Circuit?

3. How many types of sequential logic circuits?

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4. Differentiate between latches and flip flops.
 Sessional Question Paper

sessional 1

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 Old Question Paper

• 2023-24

• 2022-23

• 2021-22

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 OLD QUESTION PAPERS

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 OLD QUESTION PAPERS

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 OLD QUESTION PAPERS

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 REFERENCE

• R.P. Jain, “Modern Digital Electronics,” Tata McGraw Hill, 4th

edition, 2009.
• A. Anand Kumar, “Fundamental of Digital Circuits,” PHI 4th edition,
2018.
• W.H. Gothmann, “Digital Electronics- An Introduction to Theory and
Practice,” PHI, 2nd edition, 2006.
• D.V. Hall, “Digital Circuits and Systems,” Tata McGraw Hill, 1989.
• A. K. Singh, “Foundation of Digital Electronics & Logic Design,”
New Age Int. Publishers.
• Subrata Ghosal, “Digital Electronics,” Cengage publication, 2nd
edition, 2018

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 Thank You

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