Processor & Control

Unit
MIPS (Microprocessor without Interlocked Pipelined Stages) is a family of RISC
instruction set architecture (ISA) developed by MIPS Computer Systems.

 The earlier MIPS architectures were 32-bit.

A basic MIPS processor that includes the instruction sets are

The arithmetic-logic instructions: add, sub, and, or, slt

The memory-reference instructions: load word (lw) and store word (sw)

The branch instructions: branch equal (beq) and jump (j)

 MIPS Instruction format
•In MIPS there are only 3 ways to format instructions. They
are the R-format (register), the I- format (immediate), and the
J-format (jump).
6 bits 5 bits 5 bits 5 bits 5 bits 6 bits

R-Format Ex: add $s2, $s3, $s4

op rs rt rd shamt funct

6 bits 5 bits 5 bits 16 bits

I-Format Ex: addi $t2, $s3, 4

op rs rt offset

6 bits 26 bits

J-Format Ex: j 1020

op address
 I FORMAT INSTRUCTION
In MIPS, for I format instruction set, these are load word (lw), store word (sw).

Example: addi $t2, $s3, 4

MIPS-Datapath is a graphical MIPS CPU simulator. The datapath consists of all
units that hold or operate on data within a processor.
 All instructions start by using the program counter to supply the instruction address
to the instruction memory.
 After the instruction is fetched, the register operands used by an instruction are
specified by fields of that instruction.
 Once the register operands have been fetched, they can be operated on to compute a
memory address (for a load or store), to compute an arithmetic result (for an integer
arithmetic-logical instruction), or a compare (for a branch).
 If the instruction is an arithmetic-logical instruction, the result from the ALU must
be written to a register.
 If the operation is a load or store, the ALU result is used as an address to either store
a value from the registers or load a value from memory into the registers.
 The result from the ALU or memory is written back into the register file.
Pipelining is an implementation technique in which multiple
instructions are overlapped in execution. Today, pipelining
is nearly universal.
we already knew!
Try the laundry example:
Ann, Brian, Cathy, Dave
Each has one load of clothes to wash, dry, fold.

washer 30 dryer 40 folder 20

mins mins mins
 6 Hours
Time
30 40 30 40 20 30 40 20 30 40
20 20
A
Task Order

D
W
h
 3.5 Hours Observation
Time s A task has a series
stages;
of
30 40 40 40
Stage dependency:
40 20 e.g., wash before
A
Task Order

Multi
dry; tasks
overlapping
with
B Simultaneously use
stages;
resources
diff to speed
C Slowest
up; stage
the finish
determines
time;

D
 3.5 Hours Observations
Time No speed up for
30 40 40 40 individual task;
40 20 e.g., A still
A takes
Task Order

30+40+20=90
B But speed up for
average task execution
time;
C
e.g., 3.5*60/4=52.5 <
30+40+20=90

D
 Cola

Auto
 Pipeline

For example, a pipelined processor may process each

instruction in four steps, as follows:
F Fetch: read the instruction from the memory.
D Decode: decode the instruction and fetch the
source operand(s).
E Execute: perform the operation specified by the
instruction.
W Write: store the result in the destination location.
Pipeline
 Pipelining: Keep in Mind
• Pipelining does not reduce latency of a single task, it
increases throughput of entire workload
• Pipeline rate limited by longest stage
• potential speedup = number pipe stages
• unbalanced lengths of pipe stages reduces speedup
• Time to fill pipeline and time to drain it – when there is
slack in the pipeline – reduces speedup
Pipelining Hazards
• When the next instruction cannot execute in the following clock
cycle, then such events are called hazards

• Three different types:

• Structural Hazards
• Data hazards
• Control hazards
Structural Hazards
 Hardware resource conflicts among the instructions in the
pipeline cause structural hazards. Memory, a GPR Register, or an
ALU might all be used as resources here.
 When more than one instruction in the pipe requires access to the
very same resource in the same clock cycle, a resource conflict is
said to arise.
 In an overlapping pipelined execution, this is a circumstance
where the hardware cannot handle all potential combinations.
Structural Hazards
Structural Hazards
Take a look at the illustration above. In an IF machine cycle,
instructions are retrieved from memory in any system. Depending on
the instruction, Result Writing (RW) in the 4-stage pipeline may
access memory or one General Purpose Register. Instruction-1(I1) is
in the RW stage at t4, while Instruction-4(I4) is in the IF stage.

Alas! If I1 is a STORE instruction, both I4 and I1 are accessing the

same resource, which is memory.
In a timed condition, how can it be possible to access memory with
two commands from the same CPU? Impossible. This is referred to as
structural dependency.
 Data Hazards
• Data hazards occur when the pipeline must be stalled because one step must
wait for another to complete.
• An instruction in the pipeline requires data to be computed by a previous
instruction still in the pipeline
• In a computer pipeline, data hazards arise from the dependence of one
instruction on an earlier one that is still in the pipeline
• For the code sequence above, as soon as the ALU creates the sum for the add,
we can supply it
The result of the ADD instruction is written into the register X3 at t5 in
the example above. If bubbles aren’t used to postpone the following
SUB instruction, all the three operations will use data from X3, that is
earlier in the ADD process.
 Control Hazard
 Branch hazards are caused by branch instructions and are known as
control hazards. The flow of program/instruction execution is
controlled by branch instructions.
 In higher-level languages, conditional statements are used for
repetitive loops or condition testing (correlate with while, for, if,
case statements). These are converted into one of the BRANCH
instruction variations.
 Control Hazard
The Program Counter (PC) is loaded with the appropriate place for the
branch and jump instructions, which determines the programme flow.
The next instruction that is to be fetched and executed by the given
CPU is stored in the PC. Take a look at the instructions that follow:
In this scenario, fetching the I3 is pointless. What is the status of the
pipeline? The I3 fetch must be terminated while in I2. This can only
be determined once I2 has been decoded as JMP.
As a result, the pipeline cannot continue at its current rate, resulting in
a Control Dependency (hazard). If I3 is fetched in the meantime, it is
not just unnecessary work, but it is also possible that some data in
registers has been changed and needs to be reversed.

Identical scenarios arise in the case of conditional JMP or

BRANCH.
 Control is the most challenging aspect of processor design:
 it is both the hardest part to get right and the hardest part to make
fast.
 One of the hardest parts of control is implementing exceptions and interrupts.
 What is an Exception?
 An exception is an unexpected event from within the processor; arithmetic overflow is
an example of an exception.
 An interrupt is an event that also causes an unexpected change in control flow but
comes from outside of the processor.
 Many architectures and authors do not distinguish between interrupts and
exceptions.
MIPS convention uses the term exception to refer to any
unexpected change in control flow without distinguishing
whether the cause is internal or external
 There are two main methods used to communicate
the reason for an exception.
The method used in the MIPS architecture is to include a status
register (called the Cause register), which holds a field that
indicates the reason for the exception.
A second method is to use vectored interrupts. In a vectored
interrupt, the address to which control is transferred is
determined by the cause of the exception.