IFT 212:

COMPUTER
ARCHITECTURE AND
ORGANIZATION
LEARNING OUTCOMES
 Explain the organization of the classical von Neumann machine and its major functional units;
 Construct simple assembly language programme segments;
 Describe how fundamental high-level programming constructs are implemented at the
machine-language level;
 Discuss the concept of control points and the generation of control signals using hardwired or
microprogrammed implementations;
 Describe how the use of memory hierarchy (cache, virtual memory) is used to reduce the
effective memory latency; and
 Explain the concept of interrupts and describe how they are used to implement I/O control and
data transfers.
 COURSE CONTENTS
 Principles of computer hardware and instruction set architecture.
 Internal CPU organization and implementation
 Instruction format and types, memory, and I/O instructions.
 Dataflow, arithmetic, and flow control instructions, addressing modes, stack operations, and interrupts.
 Data path and control unit design.
 RTL, microprogramming and hardwired control.
 The practice of assembly language programming.
 Memory hierarchy. Cache memory, Virtual memory.
 Cache performance.
 Compiler support for cache performance.
 I/O organisations.
OVERVIEW OF COMPUTER
ARCHITECTURE, AND
ORGANIZATION

MODULE ONE
COMPUTER ORGANIZATION VS
ARCHITECTURE
 Computer Organization: The various operational units of
a Computer, and the interconnections that synthesize to
realize the architecture.
 Computer Architecture: The attributes of a computer
system that are visible to a machine language
programmer and have a direct impact on the logical
execution of programs. As with the analogous illustration
of buildings, the physical computer is divided into
several levels/strata / layers
INTRODUCTION
Computer is an electronic device or machine that accept data, process it and give the desired output.

As an electronic device, computer consist of electronic components like resistors, capacitor e.t.c

Although for most part human being can do whatever a computer can do but computer as a machine, is
expected to do it faster and easier with much accuracy.

Computer has found its way into innumerable areas of life. It affects some part of our lives. A
computer is faster and more accurate than people are, but must be given a complete set of instructions
that tell it exactly what to do at each step of its operation.

This set of instructions, called a program is prepared by one or more persons for each job the
computer is to do. Programs are placed in the computer memory unit in binary-coded form, with each
instruction having a unique code. The computer takes these instruction codes from memory one at a
time and performs the operation called for by the code.
FUNDAMENTALS OF COMPUTER DESIGN

ENIAC (Electronic Numerical Integrator And Computer) designed and constructed at the University of
Pennsylvania, was the world’s first general purpose electronic and digital computer. The project was a
response to U.S needs during World War II.

John Mauchy, a professor of electrical engineering at the university of Pennsylvania and John Eckert,
one of his graduate students, proposed to build a general-purpose computer using vacuum tubes for the
BRL’s application. In 1943, the Army accepted this proposal, and work began on the ENIAC. The
resulting machine was enormous, weighing 30 tons, occupying 1500 square feet of floor space, and
containing more than 18,000 vacuum tubes, when operating, it consumed 140 kilowatts of power. It was
also substantially faster than any electromechanical computer, capable of 5000 additions per second.

The ENIAC was completed in 1948, too late to be used in the war effort. The use of the ENIAC for a
purpose other than that for which it was built demonstrated its general-purpose nature. The ENIAC
continue to operate under BRL management until 1955 when it was disassembled.
WHAT IS THE ISSUE WITH THE ENIAC AND HOW CAN IT
BE SOLVED

The task of entering and altering programs for the ENIAC was extremely
tedious. The programming process can be easy if the program could be
represented in a form suitable for storing in memory alongside the data. Then,
a computer could get its instructions by reading from memory, and a program
could be set or altered by setting the values of a portion of memory. The idea
is known as the stored-program concept. The first publication of the idea was
in 1945 proposal by Von Neumann for a new computer, the EDVAC
(Electronic Discrete Variable Computer).
 VON NEUMANN’S ARCHITECTURE
• Introduction
• Proposed by John von Neumann in 1946 during the design of the IAS
(Institute for Advanced Study) in Princeton, New Jersey. It was one of the first
stored-program computers, meaning that it could store both instructions and
data in the same memory).
• Basis for all modern general-purpose computers.

• Key Features
• Single memory for storing both data and instructions.
• Sequential instruction execution: fetch, decode, execute.
• Components:
• Input Unit – For entering data and instructions.
• Memory – Shared space for data and instructions.
• Control Unit – Fetches, decodes, and executes instructions.
• Output Unit – Displays results.
STRUCTURE OF THE IAS COMPUTER [2]
THE VON NEUMANN MACHINE (IN OTHER
VIEWS)
 STRUCTURE OF THE IAS COMPUTER
The IAS Machine was made up of the following major parts:
1. A main memory (M), which stores both data and instructions
2. An arithmetic and logic unit (ALU) (CA) capable of operating on binary data and
digital logic information
3. A control unit (CC), which interprets the instructions in memory and causes them to be
executed
4. Input and output (I,O) equipment operated by the control unit

 (2) & (3) constitute (are part of) the processing unit…
 VON NEUMANN’S ARCHITECTURE
 EDVAC and Stored Program Concept
• Developed in 1945 by John von Neumann.
• Introduced the concept of storing program instructions in
memory alongside data.
• Milestones of the stored-program computer:
• Input Device: For data and instruction entry.
• Storage: Unified memory for instructions and data.
• Control Unit: Decodes and executes instructions.
• Output Device: Displays computation results.
 HARVARD ARCHITECTURE
• Overview
• Separate memory and pathways for instructions and data.
• Originated from the Harvard Mark I computer.

• Advantages
• Faster processing: Simultaneous instruction and data access.
• Different memory structures for data and instructions (e.g., sizes, types).

• Modern Usage
• Found in microcontrollers and RISC processors.
• Modified Harvard architecture adds flexibility by sharing a common address space
with separate instruction and data caches.
 VON-NEWMAN VS. HARVARD
ARCHITECTURE

Feature Von Neumann Harvard

Shared for instructions Separate for
Memory
and data instructions and data
Slower due to shared Faster due to
Speed
pathways independent pathways
General-purpose Embedded systems,
Example Use Case
computers microcontrollers
 BASIC COMPUTER ORGANIZATION
CPU: Core of computation and control.
• Memory: Stores program instructions and data.
• I/O Devices: Facilitate input and output operations.
• Datapath in CPU:
• ALU: Performs arithmetic and logic operations.
• Registers: Store intermediate results.
• Bus: Interconnects CPU components.

Arithmetic Logic Unit (ALU)

• Performs arithmetic and logical operations.
• Registers: Temporary storage for operands and results.
• Accumulator: Stores intermediate results.
 BASIC COMPUTER ORGANIZATION
 Central Processing Unit (CPU)
• Datapath:
• ALU (Arithmetic and Logic Unit): Performs calculations.
• Registers: Store temporary data and results.
• Bus: Connects components within the CPU.

• Control Unit:
• Fetches, decodes, and executes instructions.

 Modern Enhancements
• Modified Harvard Architecture:
• Combines instruction/data separation with shared memory for flexibility.

• Faster CPUs:
• Higher clock speeds, wider datapaths, and more efficient instruction handling.
GENERATIONS OF
COMPUTERS
Generation Primary Component Year developed

0th Generation Mechanical Computers 16th Century

1st Generation Vacuum Tubes (ENIAC) 1873
2nd Generation Transistors 1947
3rd Generation Integrated Circuits (ICs) 1949
4th Generation Large Scale ICs (LSI) 1974
5th Generation Very Large and Ultra Large 1986-1989
Scale ICs (VLSI & ULSI) 1989-2005
Current Generation System-on-a-chip / AI 2005 - date
 INSTRUCTION SET ARCHITECTURE (ISA)
 ISA stands for Instruction Set Architecture. It refers to the set of instructions that a
computer's CPU can execute, as well as the way these instructions are structured and how they
interact with memory, input/output devices, and other components. In essence, the ISA defines
the interface between software and hardware, making it a crucial aspect of computer
architecture.
 Generally speaking, when talking about ISA the following are mentioned:

1. Instruction Formats: The structure of the binary code that makes up each instruction (e.g.,
how the opcode, operands, and addressing modes are represented).
2. Registers: A set of small, fast storage locations within the CPU used to hold data and
addresses during processing. The ISA defines how many registers there are and how they are
used.
3. Data Types: Specifies the kinds of data (e.g., integers, floating-point numbers) the processor
can handle.
4. Control Instructions: Instructions that manage the flow of the program, such as jumps, loops,
or system calls.
 INSTRUCTION SET ARCHITECTURE (ISA)
There are two ways to classify ISAs,
1. Classification Based on Instruction Set Complexity
This classification focuses on how the CPU processes instructions:
• RISC (Reduced Instruction Set Computing)
• Uses a small, highly optimized set of simple instructions.
• Each instruction typically executes in one clock cycle.
• Examples: ARM, RISC-V, MIPS.

• CISC (Complex Instruction Set Computing)

• Uses a large set of complex instructions that can perform multiple operations
in one instruction.
• Requires multiple clock cycles for some instructions.
• Examples: x86 (Intel, AMD), VAX.
 INSTRUCTION SET ARCHITECTURE (ISA)
2. Classification Based on Operand Storage and Addressing
This classification focuses on how instructions access operands:
• Stack-based ISA- The operands are implicitly on top of the stack.
• Uses an implicit stack for operations.
• Example: Java Virtual Machine (JVM), Forth.

• Accumulator-based ISA - One operand is implicitly the accumulator

• Uses a special accumulator register for calculations.
• Example: Early computers like the Intel 8008, PDP-8.

• General Purpose Register (GPR) ISA - All operands are explicitly mentioned, and they are
primarily registers (memory access is done separately through load/store instructions in most
cases).
• Uses a set of registers for instructions instead of relying on a stack or accumulator.
• Most modern processors use this approach.
• Example: x86, ARM, RISC-V.
 INSTRUCTION LENGTH

The size of an instruction varies widely, ranging from as little as 8 bits in some microcontrollers to
hundreds of bits in some VLIW (Very Long Instruction Word) systems. Processors used in personal
computers, mainframes, and supercomputers typically have minimum instruction sizes between 8 and 64
bits.
 In the x86 architecture, the longest possible instruction is 15 bytes (120 bits) due to encoding limitations.
Within an instruction set, different instructions may have different lengths.
Fixed-Length Instructions:
• Most RISC architectures (e.g., ARM, RISC-V, MIPS) use fixed-length instructions, usually matching the
word size of the architecture (e.g., 32-bit or 64-bit). This simplifies instruction fetching and decoding.
Variable-Length Instructions:
• Many CISC architectures (e.g., x86) use variable-length instructions, which can be as short as 1 byte or
as long as 15 bytes. These provide flexibility but require more complex decoding hardware.
Mixed Encoding:
• Some architectures, such as ARM with the Thumb extension, support both 16-bit and 32-bit instructions.
The processor must switch between these modes explicitly, although ARMv8 Thumb-2 allows mixing
instructions more flexibly.
 Fixed-length instructions are generally easier to decode and optimize for speed since they avoid issues like
crossing cache lines or virtual memory page boundaries.
 MORE ON INSTRUCTION FORMAT
An instruction format defines the structure and layout of a machine language instruction,
which tells the CPU what operation to perform and which operands to use.
Each instruction is made up of several fields, and different types of instruction formats
exist depending on the architecture of the CPU. The most common fields in an instruction
format include:
1.Opcode (Operation Code): is a part of a computer instruction that identifies the specific
operation to be performed, such as "ADD", "SUB", or "LOAD", essentially telling the
processor what action to take on the data provided by the operands
2.Operands: refers to the data that an instruction in a computer program operates on, which
can be stored in a register, located at a memory address, or directly embedded within the
instruction itself as an "immediate value" - essentially a constant value that is part of the
instruction itself.
3.Addressing Mode: the method used by a CPU to identify and locate the data (operand)
needed to execute an instruction, essentially specifying how the operand's address is
interpreted within a machine instruction, whether it's directly stated, accessed through a
register, or calculated based on other values; common addressing modes include direct,
indirect, immediate, register, and indexed addressing
 COMMON TYPES OF INSTRUCTION FORMATS

Three-Address Format
•Structure: Opcode | Destination | Source 1 | Source 2
•Description: Specifies two source operands and one destination operand. All operands are
usually registers.
•Example: ADD R1, R2, R3 (R1 = R2 + R3)
•Usage: Found in RISC (Reduced Instruction Set Computing) architectures like MIPS.
COMMON TYPES OF INSTRUCTION FORMATS

Two-Address Format
•Structure: Opcode | Destination | Source
•Description: Specifies one source operand and one destination
operand. The result of the operation is stored in the destination, which
is also one of the source operands.
•Example: ADD R1, R2 (R1 = R1 + R2)
•Usage: Common in CISC (Complex Instruction Set Computing)
architectures like x86.
COMMON TYPES OF INSTRUCTION FORMATS

One-Address Format
•Structure: Opcode | Operand
•Description: Specifies only one operand. The other operand is usually
implied or uses a dedicated register like the accumulator.
•Example: ADD R1 (Accumulator = Accumulator + R1)
•Usage: Used in early computers with accumulators.
COMMON TYPES OF INSTRUCTION FORMATS
Zero-Address Format
•Structure: Opcode
•Description: No operands are specified because the instruction operates
on data from a stack. The operands are implicitly at the top of the stack.
•Example: ADD (Top two values from the stack are popped, added, and
result is pushed back onto the stack)
•Usage: Found in stack-based architectures like JVM (Java Virtual
Machine).
REGISTERS
 They are storage devices that are built within /into the CPU.
 They are different from memories, which are storage locations
that are external to the CPU.
 They are manipulated by the Control Unit to perform their
specific functions
 Their sizes are in bits or bytes (not in MB as in memories), for
holding either data, addresses or instructions.
REGISTERS (CONTD.)
 See registers like the writing pad / jotter / scratchpad of
the busy microprocessor that is executing a program /
instruction currently:
1. Keeps data that are needed quickly & frequently;
2. Stores address of the next instruction to be executed;
3. Stores signals from other internal and external
sources / devices.
REGISTERS (CONTD.)
 Two of the major classes / categories of registers in the
modern microprocessor include:
1. General Purpose Registers (GPRs) – These are registers
that are visible (accessible) to the end user / programmer.
They exist in several dozens in current processors, and
are used to keep intermediate results / data values;
2. Special Purpose Registers (SPRs) – These perform
specific functions in the microprocessor operations, and
are typically not accessible to the end user / programmer;
GPRS
 General Purpose Registers (GPRs) in modern processors typically include:

1. Accumulator Register (Ax) – A special-purpose register used in arithmetic

and logic operations. Stores intermediate results of calculations performed
by the ALU (Arithmetic Logic Unit).Often directly involved in operations
like addition, subtraction, and logical comparisons. Typically, the result of
an operation is stored back in the accumulator
2. Base Register – used as a base pointer for memory access;
3. Counter Register – used a counter for executing loops, and for shifting
operations;
4. Data Register – Data Register (DR or MDR - Memory Data Register): A
general-purpose register used to temporarily store data being transferred
between memory and the CPU. Acts as a buffer between the memory and
the processor. Holds data fetched from memory before it is used by the CPU
or data waiting to be stored in memory.
SPRS
 Special Purpose Registers (GPRs) in modern processor
typically include:
1. Program Counter (PC) Register / Instruction Pointer –
stores the address of the next instruction to be executed
by the processor;
2. Instruction Register (IR) – holds the instruction
currently being executed by the processor;
SPRS (CONTD.)
3. Memory Address Register (MAR) – either stores the
memory address from which data will be fetched to the
CPU or the address to which data will be sent and stored;
4. Memory Data Register (MDR) – holds data that has just
been fetched from memory for processor use, or that is
waiting to be written to memory after processor use /
execution. It is also known as the Memory Buffer Register
(MBR);
5. Status / Flag Registers (FRs) – a cluster of registers that
store information about the current state of the processor;
SPRS (CONTD.)
6. Input / Output Address Register (I/OAR) – stores /
specifies the address of a particular I/O device;
7. Input / Output Buffer Register (I/OBR) – used for the
exchange of data between an I/O module and the CPU;
8. Instruction Buffer Register (IBR) – acts as a temporary
store for instruction enroute to or fro the memory and
processor.
REGISTERS (CONTD.)
 Other classes / categories of registers in the modern
microprocessor include:
3. Segment Registers – hold the segment address of various items;
4. Index & Pointer Registers – store information relating to the
offset part of an address;
5. Control Registers;
6. Debug Registers;
7. Test Registers;
8. Protected Mode Segmentation Registers; etc.
PROCESSOR REGISTER
 A processor register is a fast, small storage location within the CPU,
typically implemented using flip-flops or SRAM. Registers can be general-
purpose (GPRs) or special-purpose (SPRs) and may be read-only, write-
only, or both, depending on their function.
 Load/store architectures (e.g., ARM, RISC-V, MIPS) require explicit load
and store instructions to access memory, whereas CISC architectures (e.g.,
x86) allow some instructions to operate directly on memory. Regardless of
the architecture, frequently accessed data is loaded into registers for arithmetic,
logical, and control operations.
 Registers exist at the top of the memory hierarchy, providing the fastest
access to data. However, modern CPUs often implement register renaming to
optimize execution and prevent pipeline hazards.
 Program Status Word (PSW) & Flags:

• The PSW contains control and status flags that reflect the CPU's current
state.
• Flags such as Carry Flag (CF), Zero Flag (ZF), Overflow Flag (OF), and Sign
Flag (SF) are commonly used for conditional execution.
• Different architectures implement different flag registers (e.g., x86, ARM, and
8085 all have variations).
 PROCESSOR REGISTER

Register Transfer Notation (RTN):

•RTN is used to describe data movement between registers and memory.
•Example: R3 ← [PLACE] means that the contents of memory location "PLACE" are copied into register R3.
Register-Transfer Level (RTL):
•RTL is an abstraction used in digital circuit design, describing how data moves between
registers and how combinational logic processes it.
•It is widely used in hardware description languages (HDLs) like Verilog and VHDL.
Register Pressure & Optimization:
•High register pressure occurs when most registers are in use, requiring frequent spills to memory.
•RISC architectures (e.g., MIPS, ARM) typically have larger register sets and lower register pressure,
whereas CISC architectures (e.g., x86) use advanced addressing modes and optimizations to mitigate
register shortages.
PROCESSOR OPERATIONS
The interactions that take place during the operations of a
typical modern microprocessor are classified as:
1. Processor-memory: Data may be transferred from processor to
memory or from memory to processor;
2. Processor-I/O: Data may be transferred to or from a peripheral
device by transferring between the processor and an I/O module;
3. Data processing: The processor may perform some arithmetic or
logic operation on data;
4. Control: An instruction may specify that the sequence of execution
be altered.
THE MEMORY SUBSYSTEM
 The memory referred to here is the Random Access Memory
(RAM).
 It is a volatile store, and only stores data when power is on. It is a
rather expensive storage device.
 The Read Only Memory (ROM) is the non-volatile sibling to the
RAM, which is usually programmed at the point of system
fabrication & and manufacturing.
 It consists of many memory cells (storage units) of a fixed size.
Each cell has an address associated with it: 0, 1, … n
THE MEMORY SUBSYSTEM
(CONTD.)
 A cell is the minimum unit of access in memory operations
(fetch/store a complete cell). All accesses to memory are
related to a specified address.
 The time taken to fetch/store a cell is the same for all
memory cells.
 In the stored program concept, when the computer is
running, both data and programs are stored in memory.
THE MEMORY SUBSYSTEM
(CONTD.)
 In the memory (RAM), there is the need to distinguish
between the address vs the content of a memory cell.
This is analogous to residential address zip codes vs the
residents themselves. That’s why we have the MAR
(memory address register) & the MDR (memory data
register)
 Cell contents are retrieved with reference to the cell
address.
THE MEMORY SUBSYSTEM
(CONTD.)
 Memory Operations are either of the types fetch or
store.
1. Fetch: This operation retrieves a copy of the content of
a memory cell using the specified memory address. It
does not alter the content of the cell, but simply copies
the value in the memory cell.
2. Store: Inserts a specified value into the memory cell
specified by an address. This operation alters /
overwrites the previous value of the memory cell.
 THE MEMORY
SUBSYSTEM
(CONTD.)

The Typical
Structure of
the Memory
Subsystem
 THE MEMORY
SUBSYSTEM
(CONTD.)

Storage
Device
Hierarchy
[Source: Silberschatz et al
(2013)]
THE INPUT / OUTPUT (I/O)
SUBSYSTEM
This subsystem incorporates devices (e.g. display
units, keyboard, mouse, scanners, etc.) that enable
the computer to communicate with the real world,
as well as devices (hard drives, floppy drives, tape
drives, optical drives, etc.) that enable the computer
to store and retrieve information (Mass Storage)
THE INPUT / OUTPUT (I/O)
SUBSYSTEM (CONTD.)
Data in Mass Storage (also known as external
storage) is accessed using either direct access
(direct access is the process of reading and writing data
on a storage)or sequential access (as in tape
drives)
THE INPUT / OUTPUT (I/O)
SUBSYSTEM (CONTD.)
 I/O devices are controlled by an independent unit known
as the device controller.
 Modern CPUs have multiple device controllers
interconnected through a common bus path.
 Each device controller takes charge of a specific device
and has some local buffer storage and a set of special-
purpose registers which it utilizes
 THE INPUT / OUTPUT (I/O) SUBSYSTEM
(CONTD.)

The
An interrupt signal is an
Structure
electrical or software-generated
signal that informs the CPU that
of the I/O
an event requiring immediate
attention has occurred. It forces
Subsyste
the CPU to pause its current
execution and handle the event
m
through an Interrupt Service
Routine (ISR). An I/O buffer (Input/Output buffer) is a temporary storage area
used to hold data while it is being transferred between two
devices or between a device and memory. The purpose of an I/O
buffer is to compensate for differences in the rate at which data
is read from or written to devices.
THE INPUT / OUTPUT (I/O)
SUBSYSTEM (CONTD.)
 The device controller is responsible for moving the data
between the peripheral devices that it controls and its local
buffer storage.
 Each device controller has a device driver that understands it
and provides the rest of the operating system with a uniform
interface to the peripheral device that it controls
 This frees the processor to do something else while I/O
(device) controller reads/writes data from/to device into I/O
buffer.
INPUT / OUTPUT (I/O) OPERATION
When there is a request for an I/O operation:
 The device driver loads the appropriate registers into the
device controller and examines the contents of these
registers to determine what action to take (such as “read
a character from the keyboard”, “send an information to
the display unit”, etc.)
 The device controller then starts the transfer of data
from the peripheral device to its local buffer.
INPUT / OUTPUT (I/O) OPERATION
(CONTD.)
 Upon transfer completion, the device controller informs the
device driver via an interrupt that it has finished its operation
 The device driver returns control to the operating system
(with status information), possibly returning the data or a
pointer to the data if the operation was a read.
 A Device-status table contains entry for each I/O device
indicating its type, address, and state; the operating system
indexes into the I/O device table to determine device status
and to modify table entry to include interrupt
THE ARITHMETIC & LOGIC
SUBSYSTEM
 This subsystem (the Arithmetic & Logic Unit, or ALU) is
responsible for performing the arithmetic and logic
operations for which we know the computers of today to be
capable of.
 It is, in essence, the ‘brain’ of the computer as it were, and as
we know it to be today.
 It is home to the special memory locations, called registers,
which we have already extensively considered and discussed
in our previous lecture.
THE ARITHMETIC & LOGIC
SUBSYSTEM (CONTD.)
The Structure of the ALU
Subsystem
 Buses, which are logical
data and signal paths,
interconnect the registers
to the ALU circuitry, and
help to move data and
information to and from
the ALU circuitry and the
registers.
THE CONTROL UNIT
SUBSYSTEM
 The Control Unit could be described as the errand boy of
the busy computer.
 The unit of work done in the computer is ‘instructions’;
hence, the control unit deals with processing and
executing instructions in the computer system.
 THE CONTROL UNIT SUBSYSTEM (CONTD.)
The Typical
Structure
of the
Control
Unit

An instruction decoder is a component within the CPU

The (PC) Program Counter The Instruction Register (Central Processing Unit) that interprets the binary instruction
is a special register in the is a special-purpose fetched from memory and converts it into signals that control
CPU that holds the memory register within a CPU the various parts of the processor to execute the instruction.
address of the next that holds the current When a program is running, instructions are fetched into the
instruction to be executed instruction being CPU, usually into the Instruction Register (IR). The
in a program. executed instruction decoder then takes this instruction and decodes it to
understand
THE CONTROL UNIT SUBSYSTEM
(CONTD.)
a) reads an instruction from memory
 the instruction’s address is in the PC
b) interprets the instruction, generating signals
that tell the other components what to do
 an instruction may take many machine cycles to complete
THE CONTROL UNIT SUBSYSTEM
(CONTD.)
 The processes by which The Instruction Cycle
the Control Unit carries
out its function is
described as the
Instruction Cycle.
THE CONTROL UNIT SUBSYSTEM
(CONTD.)
 The processes by which the Control Unit carries out its
function is described as the Instruction Cycle.
 A computer’s instructions and their formats is known as
its Instruction Set Architecture (ISA).
 WHAT DRIVES THE WORK OF A COMPUTER?
 Designing a computer system involves a balance of hardware, software, and technological
considerations. Let's break it down:
1. Hardware Design
• Functional Organization: Determines how different components of the computer interact
and communicate.
• Logic Design: Focuses on the detailed design of circuits that execute operations.
• Implementation: Involves practical aspects like designing integrated circuits (ICs),
packaging, cooling, and power management.
2. Software Design
• Includes defining the Instruction Set Architecture (ISA), which forms the interface
between hardware and software.
• Architects must align the ISA with modern software trends to ensure compatibility,
efficiency, and performance.
THE CONCEPT OF ARCHITECTURE IN COMPUTERS
• Definition:
• "Architecture" is the art and science of designing systems with a balance of function,
technology, and aesthetics.
• Responsibility of a Computer Architect:
• Define system performance requirements.
• Specify interconnections between components.
• Maintain harmony between hardware and software design.

 Key Concept: Instruction Set Architecture (ISA)

• The ISA defines what the programmer sees—the machine's instruction set.
• It acts as a boundary between hardware and software.
• Decisions on ISA influence hardware design, and vice versa.
 MICROARCHITECTURE
 also called computer microarchitecture

• It refers to how a processor (CPU) is internally designed and

implemented.
• It includes details like instruction pipelines, cache design, execution
units, registers, and control paths.
• Different microarchitectures can implement the same ISA, allowing systems to run the
same programs but with varying performance.
 IMPLEMENTATION OF A MACHINE
 The Role of Microarchitecture
• Microarchitecture is central to achieving high performance.
• While the ISA remains consistent across generations,
microarchitecture evolves with advancements in technology and
design practices.
• Designers balance functionality, efficiency, and scalability to
meet the needs of current and future software.
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DATAFLOW, ARITHMETIC AND FLOW
CONTROL INSTRUCTIONS,
ADDRESSING MODES, STACK
OPERATIONS, INTERRUPTS, AND
DATA PATH & CONTROL UNIT DESIGN
 DATAFLOW, ARITHMETIC, AND FLOW CONTROL
INSTRUCTIONS
Dataflow instructions govern how data moves between the CPU, memory, and
registers. These include:
• Load (MOV, LDR) – Moves data from memory to a register.
• Store (STR, ST) – Saves data from a register to memory.
• Transfer (PUSH, POP) – Moves data between registers and the stack.
• Exchange (XCHG) – Swaps data between two registers.
 DATAFLOW, ARITHMETIC, AND FLOW CONTROL
INSTRUCTIONS
Arithmetic Instructions
These perform mathematical operations such as:
• Addition (ADD, ADC – Add with Carry)
• Subtraction (SUB, SBB – Subtract with Borrow)
• Multiplication (MUL – Unsigned, IMUL – Signed)
• Division (DIV – Unsigned, IDIV – Signed)
• Increment (INC) and Decrement (DEC) – Modify values by 1
 DATAFLOW, ARITHMETIC, AND FLOW CONTROL
INSTRUCTIONS
 Flow Control Instructions

Flow control instructions dictate the sequence of execution:

• Unconditional Jumps (JMP, CALL, RET) – Transfer execution to another part of the
program.
• Conditional Jumps (JZ, JNZ, JC, JNC, JL, JG, etc.) – Execute based on flag conditions.
• Loop Control (LOOP, LOOPNZ, LOOPZ) – Repeat execution based on counter values.
ADDRESSING MODES
 - Immediate Addressing
 - Register Addressing
 - Direct Addressing
 - Indirect Addressing
 - Indexed Addressing
 - Examples with CPU instructions
STACK OPERATIONS
 - Push and Pop instructions
 - Stack Pointer (SP) Management
 - Stack-based Function Calls
 - Example of Recursive Stack Usage
INTERRUPTS
 - Types of Interrupts: Hardware & Software
 - Interrupt Vector Table
 - Interrupt Handling Mechanism
 - Examples: Keyboard Interrupt, System Calls
DATA PATH AND CONTROL
UNIT DESIGN
 - Components of Data Path
 - ALU, Registers, Buses, Multiplexers
 - Control Unit: Hardwired vs Microprogrammed Control
 - Design Considerations for Efficient CPU Operations