MIRPUR UNIVERSITY OF SCIENCE AND TECHNOLOGY (MUST), MIRPUR

DEPARTMENT OF ELECTRICAL ENGINEERING

DIGITAL SYSTEM DESIGN
EE-474

Module No. 07: Behavioral Modeling (Cont’d)

Engr. Jabbar Younis

Lecturer
 Learning Objectives

• Explain conditional statements using if and else

• Describe multiway branching, using case, casex and casez statements
• Define sequential and parallel blocks
• Understand naming of Blocks and disabling of named blocks
• Use behavioral modeling statements in practical examples

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 Key Points

• Conditional Statements

• Multi-way Branching

• Loops

• Sequential and parallel blocks

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 Conditional Statements

• Conditional statements are used for making decisions

based upon certain conditions
• These conditions are used to decide whether or not a
statement should be executed
• Keywords if and else are used for conditional statements

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 Conditional Statements (Types)
//Type 1 conditional statement. No else statement.
//Statement executes or does not execute.
if (<expression>) true_statement ;
//Type 2 conditional statement. One else statement
//Either true_statement or false_statement is evaluated
if (<expression>) true_statement ; else false_statement ;
//Type 3 conditional statement. Nested if-else-if.
//Choice of multiple statements. Only one is executed.
if (<expression1>) true_statement1 ;
else if (<expression2>) true_statement2 ;
else if (<expression3>) true_statement3 ;
else default_statement ;
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 Conditional Statements (Example)
//Type 1 statements
if(!lock) buffer = data;
if(enable) out = in;
//Type 2 statements
if (number_queued < MAX_Q_DEPTH)
begin
data_queue = data;
else
number_queued = number_queued + 1;
$display("Queue Full. Try again");
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 Conditional Statements (Example)
//Type 3 statements
//Execute statements based on ALU control signal.
if (alu_control == 0)
y = x + z;
else if(alu_control == 1)
y = x - z;
else if(alu_control == 2)
y = x * z;
else
$display("Invalid ALU control signal");
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 Mulit-way Branching
• The nested if-else-if can become unwieldy if there are too many
alternatives
• A shortcut to achieve the same result is to use the case statement
• The keywords case, endcase, and default are used in the case statement
case (expression)
alternative1: statement1;
alternative2: statement2;
alternative3: statement3;
...
...
default: default_statement;
endcase

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 Mulit-way Branching (Example)
//Execute statements based on the ALU control signal
reg [1:0] alu_control;
...
...
case (alu_control)
2'd0 : y = x + z;
2'd1 : y = x - z;
2'd2 : y = x * z;
default : $display("Invalid ALU control signal");
endcase
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 4-to-1 Multiplexer using Case Statement
module mux4_to_1 (out, i0, i1, i2, i3, s1, s0);
// Port declarations from the I/O diagram
output out;
input i0, i1, i2, i3;
input s1, s0;
reg out;
always @(s1 or s0 or i0 or i1 or i2 or i3)
case ({s1, s0}) //Switch based on concatenation of control signals
2'd0 : out = i0;
2'd1 : out = i1;
2'd2 : out = i2;
2'd3 : out = i3;
default: $display("Invalid control signals");
endcase
endmodule
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 Case Statement (Cont’d)
• The case statement compares 0, 1, x, and z values in the
expression and the alternative bit for bit.
• If the expression and the alternative are of unequal bit width,
they are zero filled to match the bit width of the widest of
the expression and the alternative.
• We will define a 1-to-4 demultiplexer for which outputs are
completely specified, that is, definitive results are provided
even for x and z values on the select signal.

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 1-to-4 Demultiplexer
module demultiplexer1_to_4 (out0, out1, out2, out3, in, s1, s0);
// Port declarations from the I/O diagram
output out0, out1, out2, out3;
reg out0, out1, out2, out3;
input in;
input s1, s0;
always @(s1 or s0 or in)
case ({s1, s0}) //Switch based on control signals
2'b00 : begin out0 = in; out1 = 1'bz; out2 = 1'bz; out3 =
1'bz; end
2'b01 : begin out0 = 1'bz; out1 = in; out2 = 1'bz; out3 = 1'bz; end
2'b10 : begin out0 = 1'bz; out1 = 1'bz; out2 = in; out3 =
1'bz; end
2'b11 : begin out0 = 1'bz; out1 = 1'bz; out2 = 1'bz; out3 =
in; end

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 1-to-4 Demultiplexer
//Account for unknown signals on select. If any select signal is x
//then outputs are x. If any select signal is z, outputs are z.
//If one is x and the other is z, x gets higher priority.
2'bx0, 2'bx1, 2'bxz, 2'bxx, 2'b0x, 2'b1x, 2'bzx :
begin
out0 = 1'bx; out1 = 1'bx; out2 = 1'bx; out3 = 1'bx;
end
2'bz0, 2'bz1, 2'bzz, 2'b0z, 2'b1z :
begin
out0 = 1'bz; out1 = 1'bz; out2 = 1'bz; out3 = 1'bz;
end
default: $display("Unspecified control signals");
endcase
endmodule

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 casex, casez Keywords
• There are two variations of the case statement
• They are denoted by keywords, casex and casez
• casez treats all z values in the case alternatives or the case
expression as don't cares. All bit positions with z can also
represented by ? in that position.
• casex treats all x and z values in the case item or the case
expression as don't cares. The use of casex and casez allows
comparison of only non-x or -z positions in the case
expression and the case alternatives. The use of casez is
similar. Only one bit is considered to determine the next
state and the other bits are ignored.
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 casex, casez (Example)
reg [3:0] encoding;
integer state;
casex (encoding) //logic value x represents a don't care bit.
4'b1xxx : next_state = 3;
4'bx1xx : next_state = 2;
4'bxx1x : next_state = 1;
4'bxxx1 : next_state = 0;
default : next_state = 0;
endcase
Thus, an input encoding = 4'b10xz would cause next_state = 3 to be
executed.
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 Loops
• There are four types of looping statements in Verilog:
• while
• for
• repeat
• forever
• All looping statements can appear only inside an
initial or always block.
• Loops may contain delay expressions

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 While Loop
• The keyword while is used to specify this loop
• The while loop executes until the while- expression is
not true
• If the loop is entered when the while-expression is
not true, the loop is not executed at all
• If multiple statements are to be executed in the loop,
they must be grouped typically using keywords begin
and end.

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 While Loop (Example)
//Illustration 1: Increment count from 0 to 127. Exit at count 128.
//Display the count variable.
integer count;
initial
count = 0;
while (count < 128) //Execute loop till count is 127. exit at count
128
begin
$display("Count = %d", count);
count = count + 1;
end
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While Loop (Example)

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 For Loop
• The keyword for is used to specify this loop
• The for loop contains three parts:
• An initial condition
• A check to see if the terminating condition is true
• A procedural assignment to change value of the control
variable

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For Loop (Example)

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 Repeat Loop
• The keyword repeat is used for this loop
• The repeat construct executes the loop a fixed
number of times
• A repeat construct cannot be used to loop on a
general logical expression
• A repeat construct must contain a number, which can
be a constant, a variable or a signal value.

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 Repeat Loop (Example)
//Illustration 1 : increment and display count from 0 to 127
integer count;
initial
begin
count = 0;
repeat(128)
begin
$display("Count = %d", count);
count = count + 1;
end
end
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Repeat Loop (Example)

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 Forever Loop
• The keyword forever is used to express this loop
• The loop does not contain any expression and
executes forever until the $finish task is
encountered
• The loop is equivalent to a while loop with an
expression that always evaluates to true, e.g., while
(1)
• A forever loop can be exited by use of the disable
statement

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 Forever Loop (Example)
//Example 1: Clock generation .Use forever loop instead of always block
reg clock;
initial
begin
// posedge to latch data
clock = 1'b0;
forever #10 clock = ~clock; //Clock with period of 20 units
end
//Example 2: Synchronize two register values at every positive edge of clock
reg clock;
reg x, y;
initial
forever @(posedge clock) x = y;
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 Sequential and Parallel Blocks
• Block statements are used to group multiple
statements to act together as one
• There are two types of blocks:
• sequential blocks
• parallel blocks

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 Sequential Blocks
• The keywords begin and end are used to group
statements into sequential blocks
• Sequential blocks have the following characteristics:
• The statements in a sequential block are
processed in the order they are specified.
• If delay or event control is specified, it is relative
to the simulation time when the previous
statement in the block completed execution

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Sequential Blocks (Example)

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 Parallel Block
• Parallel blocks, specified by keywords fork and join,
provide interesting simulation features
• Parallel blocks have the following characteristics:
• Statements in a parallel block are executed
concurrently.
• Ordering of statements is controlled by the delay or
event control assigned to each statement.
• If delay or event control is specified, it is relative to
the time the block was entered.

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Parallel Block (Example)

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 Parallel Block (Race Condition)
//Parallel blocks with deliberate race condition
reg x, y;
reg [1:0] z, w;
initial
fork
x = 1'b0;
y = 1'b1;
z = {x, y};
w = {y, x};
join

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 Nested Blocks
• Blocks can be nested
//Nested blocks
initial
begin
x = 1'b0;
fork
#20 w = {y, x};
#5 y = 1'b1;
#10 z = {x, y};
join
end
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 Named Blocks

• Blocks can be given names.

• Local variables can be declared for the named block.
• Named blocks are a part of the design hierarchy.
Variables in a named block can be accessed by using
hierarchical name referencing.
• Named blocks can be disabled, i.e., their execution
can be stopped.

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 Named Blocks (Example)
//Named blocks
module top;
initial
begin: block1 //sequential block named block1
integer i; //integer i is static and local to block1
... ... end
// can be accessed by hierarchical name, top.block1.i
initial
fork: block2 //parallel block named block2
reg i; // register i is static and local to block2
... ... join
// can be accessed by hierarchical name, top.block2.i

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 Disabling Named Blocks
• The keyword disable provides a way to terminate the
execution of a named block. disable can be used to get out
of loops, handle error conditions, or control execution of
pieces of code, based on a control signal.
• Disabling a block causes the execution control to be passed
to the statement immediately succeeding the block
• The difference is that a break statement can break the
current loop only, whereas the keyword disable allows
disabling of any named block in the design.

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 Disabling Named Blocks (Example)
reg [15:0] flag;
integer i; //integer to keep count
initial
begin
flag = 16'b 0010_0000_0000_0000;
i = 0;
begin: block1 //The main block inside while is named block1
while(i < 16)
begin
if (flag[i])
begin
$display("Encountered a TRUE bit at element number %d", i);
disable block1; //disable block1 because you found true bit.
end
i = i + 1; end
end end

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 References

• VERILOG HDL”-A guide to digital design and synthesis by Samir

Palnitkar, Prentice Hall Publisher

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End of Lecture