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Bus and Memory Transfers

The document discusses the common bus system used for transferring information between registers in digital computers, utilizing multiplexers and control signals to manage data flow. It explains the use of three-state buffers for bus construction, highlighting their ability to maintain a high-impedance state to prevent loading effects. Additionally, it covers memory transfer operations, detailing read and write processes with symbolic representations for clarity.

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hima bindu
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35 views

Bus and Memory Transfers

The document discusses the common bus system used for transferring information between registers in digital computers, utilizing multiplexers and control signals to manage data flow. It explains the use of three-state buffers for bus construction, highlighting their ability to maintain a high-impedance state to prevent loading effects. Additionally, it covers memory transfer operations, detailing read and write processes with symbolic representations for clarity.

Uploaded by

hima bindu
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
Available Formats
Download as PPTX, PDF, TXT or read online on Scribd
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Bus and Memory

Transfers
Mrs. Himabindu
SVIT
Introduction
• A common bus system is an efficient way to transfer information between
registers in a digital computer.
• Instead of having separate lines for each register-to-register connection, a
common bus system consists of a set of common lines, one for each bit of a
register. This allows binary information to be transferred one bit at a time.
• Control signals determine which register is selected by the bus during each
transfer.
• Multiplexers are commonly used to construct such bus systems.
• For example, if we have four registers, each with four bits, we
would use four 4-to-1 multiplexers, with each multiplexer
handling one bit position of the registers.

• The selection lines of the multiplexers determine which register's


data is placed on the bus.
Control Signals
• In this type of bus system, the control signals, often denoted as S1
and S0, specify which register is selected by the bus.

• For example, if S1S0 is 00, the 0 data inputs of all multiplexers


are selected, causing the bus to receive data from register A.

• Similarly, other combinations of S1S0 select registers B, C, or D.


• In a more general case, a bus system can multiplex k registers,
each with n bits, to produce an n-line common bus. The number
of multiplexers required is equal to n, and each multiplexer must
have k data input lines.
• For example, to create a common bus for eight registers of 16 bits
each, you would need 16 multiplexers, one for each line in the
bus. Each multiplexer would have eight data input lines and three
selection lines to multiplex one significant bit from the eight
registers.
• Transferring data from a bus into one of many destination registers is achieved
by connecting the bus lines to the inputs of all destination registers and
activating the load control of the specific destination register selected. The
symbolic representation for such a bus transfer may involve mentioning the bus
explicitly or implicitly.

For instance, "BUS ← C, R1 ← BUS"

• signifies that the content of register C is placed on the bus, and then the content
of the bus is loaded into register R1 by activating its load control input.
• Alternatively, if the presence of the bus is known in the system, a
more concise statement like

"R1 ← C"
• can be used, and the designer knows which control signals must
be activated to facilitate the transfer through the bus.
Three-State Bus Buffers
• A bus system can be constructed with three-state gates instead of
multiplexers.
• A three-state gate is a digital circuit that exhibits three states. Two of
the states are signals equivalent to logic 1 and 0 as in a conventional
gate. The third state is a high-impedance state.
• The high-impedance state behaves like an open circuit, which means
that the output is disconnected and does not have a logic significance.
Three-state gates may perform any conventional logic, such as AND
or NAND. However, the one most commonly used in the design of a
bus system is the buffer gate.
Graphic symbol of a three-state
buffer gate
• The high-impedance state of a three-state gate provides a special
feature not available in other gates.

• Because of this feature, a large number of three-state gate outputs can


be connected with wires to form a common bus line without
endangering loading effects.
The construction of a bus system with three-
state buffers
• The outputs of four buffers are connected together to form a single
bus line.

• The control inputs to the buffers determine which of the four normal
inputs will communicate with the bus line.

• No more than one buffer may be in the active state at any given time.
The connected buffers must be controlled so that only one three-state
buffer has access to the bus line while all other buffers are maintained
in a high-impedance state.
• One way to ensure that no more than one control input is active at any
given time is to use a decoder, as shown in the diagram.

• When the enable input of the decoder is 0, all of its four outputs are 0,
and the bus line is in a high-impedance state because all four buffers
are disabled.

• When the enable input is active, one of the three-state buffers will be
active, depending on the binary value in the select inputs of the
decoder.
Memory Transfer
• A memory word will be symbolized by the letter M.

• The particular memory word among the many available is selected by


the memory address during the transfer. It is necessary to specify the
address of M when writing memory transfer operations.

• This will be done by enclosing the address in square brackets


following the letter M.
• Read: The transfer of information from a memory word to the outside
environment is called a read operation.

• Example:

Read: DR ← M[AR]

• This causes a transfer of information into DR from the memory word


M selected by the address in AR.
• Write: The transfer of new information to be stored into the memory is called a
write operation.

• The write operation transfers the content of a data register to a memory word M
selected by the address. Assume that the input data are in register R1 and the
address is in AR. The write operation can be stated symbolically as follows:

Write: M[AR] ← R1
• This causes a transfer of information from R1 into the memory word M
selected by the address in AR.

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