lecture 2- Instruction Set Architecture
lecture 2- Instruction Set Architecture
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Basic processor architecture
Memory
MAR MDR
Control
PC R0
R1 General purpose
IR registers
ALU
Instruction that is R(n-1)
-
currently being
n general purpose
executed registers Processor
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Basic processor architecture (contd..)
Control Data
Path Path
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Fetch/Execute cycle
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Memory organization
Recall:
Information is stored in the memory as a collection of bits.
Collection of bits stored or retrieved simultaneously which
called a word.
Number of bits in a word is called word length.
Word length can be 16 to 64 bits.
Another collection which is more basic than a word:
Collection of 8 bits known as a “byte”
Bytes are grouped into words, word length can also be
expressed as a number of bytes instead of the number
of bits:
Word length of 16 bits, is equivalent to word length of 2
bytes.
Words may be 2 bytes (older architectures), 4 bytes (current
architectures), or 8+ bytes (modern architectures).
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Memory organization (contd..)
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Memory organization (contd..)
Byte 0
•Memory is viewed as a sequence of
bytes.
•Address of the first byte is 0
•Address of the last byte is 2k - 1,
where k is the number of bits used
to hold memory address
•E.g. when k = 16,
Address of the first byte is 0
Address of the last byte is 65535
•E.g. when k = 2,
Address of the first byte is ?
Address of the last byte is ?
k
Byte 2 -1
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Memory organization (contd..)
Byte 0 Word #0
Byte 1
Byte 2
MAR Byte 3
Byte 4 Word #1 MDR
MAR register
contains the
address of the
memory location
addressed
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Memory operations
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Instruction types
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Instruction types (contd..)
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Specifying operands in instructions
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Source and destination operands
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Source and destination operands (contd..)
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Instruction types
Instructions can also be classified based on the number
of operand addresses they include.
3, 2, 1, 0 operand addresses.
3-address instructions are almost always instructions
that implement binary operations.
E.g. Add A, B, C (C = A + B)
k bits are used to specify the address of a memory
location, then 3-address instructions need 3*k bits to
specify the operand addresses.
3-address instructions, where operand addresses are
memory locations are too big to fit in one word.
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Instruction types (contd..)
Immediate mode
Operand is given explicitly in the instruction.
E.g. Move #200, R0
Can be used to represent constants.
Register, Absolute and Immediate modes contained
either the address of the operand or the operand itself.
Some instructions provide information from which the
memory address of the operand can be determined
That is, they provide the “Effective Address” of the
operand.
They do not provide the operand or the address of the
operand explicitly.
Different ways in which “Effective Address” of the
operand can be generated.
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Addressing modes (contd..)
Main
memory
B Operand A B
R1 B Register B Operand
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Addressing Modes (contd..)
Autoincrement mode:
Effective address of the operand is the contents of a
register specified in the instruction.
After accessing the operand, the contents of this register
are automatically incremented to point to the next
consecutive memory location.
(R1)+
Autodecrement mode
Effective address of the operand is the contents of a
register specified in the instruction.
Before accessing the operand, the contents of this register
are automatically decremented to point to the previous
consecutive memory location.
-(R1)
Autoincrement and Autodecrement modes are useful for
implementing “Last-In-First-Out” data structures.
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Addressing modes (contd..)
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Thank You for Listening !
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