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Delay Generation in 8085

The document discusses methods for generating delays in 8085 microprocessors using instruction execution times, including techniques such as NOP instructions, and using 8-bit and 16-bit registers as counters. It explains how to calculate delays based on T-States and frequency, providing formulas for total delay in loops and nested loops. Additionally, it includes examples and calculations for generating specific delays, such as a 0.25-second delay at a given frequency.

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20 views17 pages

Delay Generation in 8085

The document discusses methods for generating delays in 8085 microprocessors using instruction execution times, including techniques such as NOP instructions, and using 8-bit and 16-bit registers as counters. It explains how to calculate delays based on T-States and frequency, providing formulas for total delay in loops and nested loops. Additionally, it includes examples and calculations for generating specific delays, such as a 0.25-second delay at a given frequency.

Uploaded by

saverfile434
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
Available Formats
Download as PPTX, PDF, TXT or read online on Scribd
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Delay Generation and Calculation

in 8085 Microprocessors
Kushal Roy (IIT Roorkee), Dept of ECE,
HIT Haldia
When the delay subroutine is executed, the
microprocessor does not execute other tasks. For
the delay we are using the instruction execution
times. executing some instructions in a loop, the
delay is generated. There are some methods of
generating delays. These methods are as follows.

Using NOP instructions


Using 8-bit register as counter
Using 16-bit register pair as counter
Delays
• Each instruction passes through different combinations of
Fetch, Memory Read, and Memory Write cycles.
• Knowing the combinations of cycles, one can calculate how
long such an instruction would require to complete.
– B for Number of Bytes
– M for Number of Machine Cycles
– T for Number of T-State.

3
Delays
• Knowing how many T-States an instruction requires, and
keeping in mind that a T-State is one clock cycle long, we can
calculate the time using the following formula:

Delay = No. of T-States / Frequency

• For example a “MVI” instruction uses 7 T-States. Therefore, if


the Microprocessor is running at 2 MHz, the instruction would
require 3.5 mSeconds to complete.

4
Delay loops
• We can use a loop to produce a certain amount of time delay
in a program.

• The following is an example of a delay loop:


MVI C, FFH 7 T-States
LOOP DCR C 4 T-States
JNZ LOOP 10 T-States

• The first instruction initializes the loop counter and is


executed only once requiring only 7 T-States.
• The following two instructions form a loop that requires 14 T-
States to execute and is repeated 255 times until C becomes
5 0.
Delay Loops
• We need to keep in mind though that in the last iteration of the loop, the JNZ
instruction will fail and require only 7 T-States rather than the 10.
• Therefore, we must deduct 3 T-States from the total delay to get an accurate
delay calculation.
• To calculate the delay, we use the following formula:
Tdelay = TO + TL
– Tdelay = total delay
– TO = delay outside the loop
– TL = delay of the loop

• TO is the sum of all delays outside the loop.

• TL is calculated using the formula


6 TL = T X Loop T-States X N10
Delay Loops
• Using these formulas, we can calculate the time
delay for the previous example:

• TO = 7 T-States
– Delay of the MVI instruction

• TL = (14 X 255) - 3 = 3567 T-States


– 14 T-States for the 2 instructions repeated 255 times
(FF16 = 25510) reduced by the 3 T-States for the final JNZ.

• TDelay = (7 + 3567) X 0.5 mSec = 1.787 mSec


– Assuming f = 2 MHz
7
Using a Register Pair as a Loop Counter
• Using a single register, one can repeat a loop for a maximum
count of 255 times.

• It is possible to increase this count by using a register pair for


the loop counter instead of the single register.
– A minor problem arises in how to test for the final count
since DCX and INX do not modify the flags.
– However, if the loop is looking for when the count
becomes zero, we can use a small trick by ORing the two
registers in the pair and then checking the zero flag.

8
Using a Register Pair as a Loop Counter
• The following is an example of a delay loop set
up with a register pair as the loop counter.
LXI B, 1000H 10 T-States
LOOP DCX B 6 T-States
MOV A, C 4 T-States
ORA B 4 T-States
JNZ LOOP 10 T-States

9
Using a Register Pair as a Loop Counter
• Using the same formula from before, we can
calculate:
• TO = 10 T-States
– The delay for the LXI instruction

• TL = (24 X 4096) - 3 = 98301 T- States


– 24 T-States for the 4 instructions in the loop repeated 4096 times
(100016 = 409610) reduced by the 3 T-States for the JNZ in the last
iteration.

• TDelay = (10 + 98301) X 0.5 mSec = 49.155 mSec


10
Nested Loops
• Nested loops can be easily Initialize loop 2

setup in Assembly language Body of loop 2

by using two registers for Initialize loop 1


the two loop counters and
Body of loop 1
updating the right register
in the right loop. Update the count1

– In the figure, the body of No Is this


Final
loop2 can be before or Count?

after loop1. Yes


Update the count 2

No Is this
Final
Count?

Yes

11
Nested Loops for Delay
• Instead Register Pairs, a nested loop structure
can be used to increase the total delay
produced.
MVI B, 10H 7 T-States
LOOP2 MVI C, FFH 7 T-States
LOOP1 DCR C 4 T-States
JNZ LOOP1 10 T-States
DCR B 4 T-States
JNZ LOOP2 10 T-States

12
Delay Calculation of Nested Loops
• The calculation remains the same except that it the formula must be
applied recursively to each loop.
– Start with the inner loop, then plug that delay in the calculation of the
outer loop.

• Delay of inner loop


– TO1 = 7 T-States
• MVI C, FFH instruction
– TL1 = (255 X 14) - 3 = 3567 T-States
• 14 T-States for the DCR C and JNZ instructions repeated 255 times
(FF16 = 25510) minus 3 for the final JNZ.
– TLOOP1 = 7 + 3567 = 3574 T-States

13
Delay Calculation of Nested Loops
• Delay of outer loop
– TO2 = 7 T-States
• MVI B, 10H instruction
– TL1 = (16 X (14 + 3574)) - 3 = 57405 T-States
• 14 T-States for the DCR B and JNZ instructions and 3574
T-States for loop1 repeated 16 times (1016 = 1610) minus 3 for the final JNZ.
– TDelay = 7 + 57405 = 57412 T-States

• Total Delay
– TDelay = 57412 X 0.5 mSec = 28.706 mSec

14
Increasing the delay
• The delay can be further increased by using
register pairs for each of the loop counters in
the nested loops setup.
• It can also be increased by adding dummy
instructions (like NOP) in the body of the loop.

15
Write a program to generate a delay of
0.25 sec if the crystal frequency is 5MHz

Operating frequency is half of crystal


frequency 2.5MHz
Time for one T-state = .4 micro sec
Number of
T-state required = RT/Time for 1 T-state
=1000000
Calculate the value of Count to generate
0.25 sec delay.
LXI B, count
BACK: DCX B
MOVA,C
ORA B
JNZ BACK

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