Interrupts

Kushal Roy (IIT Roorkee), Dept of ECE,

HIT Haldia
 The 8085
Interrupts
• The 8085 has 5 interrupt inputs.
– The INTR input.
• The INTR input is the only non-vectored interrupt.
• INTR is maskable using the EI/DI instruction pair.

– RST 5.5, RST 6.5, RST 7.5 are all automatically

vectored.
• RST 5.5, RST 6.5, and RST 7.5 are all maskable.

– TRAP is the only non-maskable interrupt in the

8085
• TRAP is also automatically vectored
 The 8085
Interrupts

Interrupt name Maskable Vectored

INTR Yes No
RST 5.5 Yes Yes
RST 6.5 Yes Yes
RST 7.5 Yes Yes
TRAP No Yes
 8085 Software Interrupts
Restart Equivalent
Instruction to

RST0 CALL

0000H
• The 8085 recognizes 8 RESTART RST1 CALL
instructions: RST0 - RST7.
0008H
– each of these would send the RST2 CALL
execution to a predetermined
hard-wired memory 0010H
location: RST3 CALL

0018H
RST4 CALL

0020H
RST5 CALL

0028H
RST6 CALL
 The 8085 Maskable/Vectored
Interrupts
• The 8085 has 4 Masked/Vectored interrupt inputs.
– RST 5.5, RST 6.5, RST 7.5
• They are all maskable.
• They are automatically vectored according to the following
table:
Interrupt Vector
RST 5.5 002CH
RST 6.5 0034H
RST 7.5 003CH

– The vectors for these interrupt fall in between the vectors for the
RST instructions. That’s why they have names like RST 5.5
(RST 5 and a half).
 7 6 5 4 3 2 1 0

M7.5

M6.5

M5.5
MSE
SDO

R7.5
SDE
XXX
}
RST5.5 Mask
Serial Data Out 0- Available
RST6.5 Mask
1 - Masked
RST7.5
Mask

Enable Serial Data Mask Set Enable

0 - Ignore bit 7 0 - Ignore bits 0-2
1 - Send bit 7 to 1 - Set the masks according
SOD pin to bits 0-2

Not Used Force RST7.5 Flip Flop to reset

wwU sinw.Lea rn En

e SIM Instruction to Modify the

gin g th
eering .iInterrupt Masks
n

• Example: Set the interrupt masks so that

RST5.5 is enabled, RST6.5 is masked, and
RST7.5 is enabled.
– First, determine the contents of the
accumulator

M7.5

M6.5

M5.5
- Enable

MSE
SDO

R7.5
SDE

XXX
5.5 bit 0 = 0
- Disable 6.5 bit 1 = 1
- Enable 7.5 bit 2 = 0 0 0 0 0 1 0 1 0
- Allow setting the masks bit 3 = 1
- Don’t reset the flip flop bit 4 = 0
- Bit 5 is not used bit 5 = 0 Contents of accumulator are: 0AH
- Don’t use serial data bit 6 = 0
- Serial data is ignored bit 7 = 0

EI ; Enable interrupts including INTR

MVI A, 0A ; Prepare the mask to enable RST 7.5, and 5.5, disable 6.5
SIM ; Apply the settings RST masks
 How RIM sets the Accumulator’s
different bits
7 6 5 4 3 2 1 0

M5.5
M7.5
M6.5
P6.5
P7.5

P5.5
SDI

IE
}
RST5.5 Mask
Serial Data In 0- Available
RST6.5 Mask
1 - Masked
RST7.5
RST5.5 Interrupt Pending Mask
RST6.5 Interrupt
Pending RST7.5 Interrupt Enable
Value of the Interrupt Enable
Interrupt Pending
Flip Flop
 TRAP
• TRAP is the only non-maskable interrupt.
– It does not need to be enabled because it cannot be
disabled.
• It has the highest priority amongst interrupts.
• It is edge and level sensitive.
– It needs to be high and stay high to be recognized.
– Once it is recognized, it won’t be recognized again until
it goes low, then high again.

• TRAP is usually used for power failure and

emergency shutoff.
 The 8085
Interrupts
Interrupt Masking
Maskable Vectored Memory
Name
Method

INTR Yes DI / EI No No

RST 5.5 / DI / EI
Yes Yes Yes
RST 6.5 SIM
DI / EI
RST 7.5 Yes Yes Yes
SIM

TRAP No None Yes No