2022 05 24 Jackyman i2c Design Review
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jackyman chen2022 05 24 Jackyman i2c Design Review
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jackyman chenReduced I2c slave
design review
2022/05/24 jackyman
I2C slave interface
Apb_bus_interface I2c signal control
PRESETn SDA
PCLK SCL
I2C_PSEL SDA_OE
PADDR[11:2] INT_SIG To coretex m0
interrupt
PENABLE
I2c signal description
I2C module PRESETn
PWRITE
PWDATA[31:0]
PRDATA[31:0]
PREADY
I2C register(1)
i2c_tx_rx_length Address: 0x30006000 default value: 14’h0000
I2C_TX_RX_LENGTH
[14:0]
R only
i2c_module_rst Address: 0x30006004 default value: 32’h0000_0000
I2C_MODULE_RST
[0:0]
W only , write any value to rst
i2c_device_id Address: 0x30006008 default value: 7’h41
I2C_DEVICE_ID
[6:0]
R/W both, can change to any value and can’t be reset.
I2C register(2)
I2c_config_reg Address: 0x30006010 default value: 2’h2
I2c_config_reg
bit[1] bit[0]
(i2c status) r only “1” means device (user sel device nack) Both r/w, write 1 to
no read/write action . make device respond nack to host when
data is not ready.
I2C sda & scl latch
I2C start stop control(data latch scl)(1)
正常情形 data 包 clock 所以在
data edge latch scl ,latch
到的數值一定是 0 若是 可以 latch
到數值 代表 start/stop/restart
發生
I2C start stop control(data latch scl)(2)
wire start_cond = ~start2&start1&idle_phase;
wire stop = (stop2|stop3);
I2C slave bcnt and byte1 ctrl
I2C slave device_id and read/write(1)
I2C slave device_id and read/write(2)
I2C slave device_id and read/write(3)
wire write_op_source = device_match&~sdata[0];
wire read_op_source = device_match&sdata[0];
I2C slave ack and nack control
I2C slave ack and nack control
assign sda_oe = (device_no_match_sig|i2c_user_sel_dev_nak|i2c_auto_nak)? 1'b0:((slave_ack&(rx_data_phase|addr_phase))|(~sda_valid));
assign sda_valid =tx_data_phase?sda_out:1'b1 ;
I2C state machine diagram
IDLE
User_sel_device_nack/ Start_cond
device id no match
I2c_restart
ADDR_PHASE
write_op Read_op
Rx_phase Tx_phase Stop/User_sel_device_nack
Stop/user_sel_device_nack
I2C state machine control(1)
I2C state machine control(2)write
I2C state machine control(3)read
I2c read _start
I2c read _end
I2C data send and received(1)
I2C data send and received(2)
I2C data send and received(3)
I2C data send and received(4)
I2C data send and received(5)
I2C int and en control
I2C negedge control
always@(negedge PCLK or negedge hyb_i2c_reset)begin
if(~hyb_i2c_reset) receive_count_d <= 1'b0;
else receive_count_d <=receive_count;
end
always@(negedge PCLK or negedge hyb_i2c_reset)begin
if(~hyb_i2c_reset) transmit_count_d<=1'b0;
else transmit_count_d<=transmit_count;
End
always@(negedge PCLK or negedge hyb_i2c_reset)begin
if(~hyb_i2c_reset) start2_d <= 1'b0;
else start2_d <= start2;
end
always@(negedge PCLK or negedge hyb_i2c_reset)begin
if(~hyb_i2c_reset) I2C_PSEL_EXT<= 1'b0;
else I2C_PSEL_EXT<= I2C_PSEL;
end
