Computer Architecture & Organization

Input / Output
Chapter Objectives
• After studying this chapter, you should be
able to:
• Explain the use of I/O modules as part of a
computer organization.
• Understand the difference between
programmed I/O and interrupt-driven
I/O and discuss their relative merits.
• Present an overview of the operation of
direct memory access.
• Present an overview of direct cache
access.
• Explain the function and use of I/O
Introduction
• The third key element of a computer system is a
set of I/O modules.
• An I/O module contains logic for performing a
communication function between the peripheral
and the bus.
• Why does one not connect peripherals directly to
the system bus?
—Wide variety of peripherals with various
methods of operation.
—Different data transfer rate.
—Different data formats.
• All slower than CPU and RAM
• Need I/O modules
Input/Output Module
• Why we need the input/output module?
—Interface to CPU and Memory
—Interface to one or more peripherals
Generic Model of I/O Module
External Devices
• provide a means of exchanging data
between the external environment and
the computer.
• An external device attaches to the
computer by a link to an I/O module.
• The link is used to exchange control,
status, and data between the I/O module
and the external device.
• An external device connected to an I/O
module is often referred to as a peripheral
device or, simply, a peripheral.
External devices
We can broadly classify external devices
into three categories:
• Human readable - for communicating with
the computer user.
—Screen, printer, keyboard
• Machine readable - for communicating
with equipment
—Monitoring and control, sensors, magnetic disk
• Communication - for communicating with
remote devices.
—Modem
—Network Interface Card (NIC)
External Device Block Diagram
External device block diagram
• The interface to the I/O module is in the form of
control, data, and status signals.
• Control signals determine the function that the
device will perform, such as send data to the I/O
module (INPUT or READ), accept data from the
I/O module (OUTPUT or WRITE), report status, or
perform some control function particular to the
device (e.g., position a disk head).
• Data are in the form of a set of bits to be sent to
or received from the I/O module.
• Status signals indicate the state of the device.
Examples are READY/ NOT-READY to show
whether the device is ready for data transfer.
ED block Diagram
• Control logic associated with the device
controls the device’s operation in
response to direction from the I/O module.
• The transducer converts data from
electrical to other forms of energy during
output and from other forms to electrical
during input.
• Typically, a buffer is associated with the
transducer to temporarily hold data being
transferred between the I/O module and
the external environment.
I/O Module Function
• Control & Timing
• CPU Communication
• Device Communication
• Data Buffering
• Error Detection
Control and Timing
• to coordinate the flow of traffic between
internal resources and external devices.
• For example, the control of the transfer of
data from an external device to the
processor might involve the following
sequence of steps:
—CPU checks I/O module device status
—I/O module returns status
—If ready, CPU requests data transfer
—I/O module gets data from device
—I/O module transfers data to CPU
—Variations for output, DMA, etc.
CPU communication
• Processor communication involves the
following:
— Command decoding: The I/O module accepts commands
from the processor, typically sent as signals on the control
bus. For example, an I/O module for a disk drive might
accept the following commands: READ SECTOR, WRITE
SECTOR, SEEK track number, and SCAN record ID.
— Data: Data are exchanged between the processor and the
I/O module over the data bus.
— Status reporting: Because peripherals are so slow, it is
important to know the status of the I/O module. Common
status signals are BUSY and READY. There may also be
signals to report various error conditions. Address
recognition: Just as each word of memory has an address,
so does each I/O device. Thus, an I/O module must
recognize one unique address for each peripheral it
controls.
Error detection
• For error detection and reporting to the
CPU.
• One class of errors includes mechanical
and electrical malfunctions reported by
the device (e.g., paper jam, bad disk
track).
• Another class consists of unintentional
changes to the bit pattern as it is
transmitted from device to I/O module.
I/O Module Structure
• The module connects to the rest of the computer
through a set of signal lines (e.g., system bus lines).
• Data transferred to and from the module are
buffered in one or more data registers.
• status registers provide current status information. A
status register may also function as a control
register, to accept detailed control information from
the processor.
• The logic within the module interacts with the
processor via a set of control lines. The processor
uses the control lines to issue commands to the I/O
module.
• Finally, the I/O module contains logic specific to the
interface with each device that it controls.
I/O Module Structure Diagram
I/O Module Decisions
• Hide or reveal device properties to CPU
• Support multiple or single device
• Control device functions or leave for CPU
• Also O/S decisions
—e.g. Unix treats everything it can as a file
Input Output Techniques
• Three techniques are possible for I/O
operations:
—Programmed I/O
—Interrupt driven
—Direct Memory Access
Input Output Techniques
• Programmed
—data are exchanged between the processor
and the I/O module.
• Interrupt driven
—the processor issues an I/O command,
continues to execute other instructions, and is
interrupted by the I/O module when the latter
has completed its work.
• Direct Memory Access (DMA)
—the I/O module and main memory exchange
data directly, without processor involvement.
Three Techniques for
Input of a Block of Data
Programmed I/O
• CPU has direct control over I/O
—Sensing status
—Read/write commands
—Transferring data
• CPU waits for I/O module to complete
operation
• Wastes CPU time
Programmed I/O - detail
• CPU requests I/O operation
• I/O module performs operation
• I/O module sets status bits
• CPU checks status bits periodically
• I/O module does not inform CPU directly
• I/O module does not interrupt CPU
• CPU may wait or come back later
I/O Commands
• To execute an I/O-related instruction, the
processor issues an address, specifying
the particular I/O module and external
device, and an I/O command.
• 4 types of I/O commands an I/O module
may receive addressed by a processor
—Control - telling module what to do
– e.g. rewind / spin up disk
—Test - check status
– e.g. power? Error?
—Read/Write
– Module transfers data via buffer from/to device
Addressing I/O Devices
• Under programmed I/O data transfer is
very like memory access (CPU viewpoint)
• Each device given unique identifier
• CPU commands contain identifier
(address)
I/O Mapping
• Memory mapped I/O
— Devices and memory share an address space
— I/O looks just like memory read/write
— No special commands for I/O
– Large selection of memory access commands available
• Isolated I/O
— Separate address spaces
— Need I/O or memory select lines
— Special commands for I/O
– Limited set
Interrupt Driven I/O
• Overcomes CPU waiting
• No repeated CPU checking of device
• I/O module interrupts when ready
Interrupt Driven I/O
Basic Operation
• CPU issues read command
• I/O module gets data from peripheral
whilst CPU does other work
• I/O module interrupts CPU
• CPU requests data
• I/O module transfers data
Simple Interrupt
Processing
CPU Viewpoint
• Issue read command
• Do other work
• Check for interrupt at end of each
instruction cycle
• If interrupted:-
—Save context (registers)
—Process interrupt
– Fetch data & store
• See Operating Systems notes
Design Issues
• How do you identify the module issuing
the interrupt?
• How do you deal with multiple interrupts?
—i.e. an interrupt handler being interrupted
Identifying Interrupting Module (1)
• Different line for each module
—PC
—Limits number of devices
• Software poll
—CPU asks each module in turn
—Slow
Identifying Interrupting Module (2)
• Daisy Chain or Hardware poll
—Interrupt Acknowledge sent down a chain
—Module responsible places vector on bus
—CPU uses vector to identify handler routine
• Bus (arbitration) Master
—Module must claim the bus before it can raise
interrupt
—e.g. PCI & SCSI
Multiple Interrupts
• Each interrupt line has a priority
• Higher priority lines can interrupt lower
priority lines
• If bus mastering only current master can
interrupt
Drawbacks of Programmed and Interrupt-
Driven I/O
• Interrupt-driven I/O, though more efficient than
simple programmed I/O, still requires the active
intervention of the processor to transfer data
between memory and an I/O module, and any
data transfer must traverse a path through the
processor.
• Thus, both these forms of I/O suffer from two
inherent drawbacks:
—The I/O transfer rate is limited by the speed
with which the processor can test and service
a device.
—The processor is tied up in managing an I/O
transfer; a number of instructions must be
executed for each I/O transfer.
Direct Memory Access
• Interrupt driven and programmed I/O
require active CPU intervention
—Transfer rate is limited
—CPU is tied up
• DMA is the answer
DMA Function
• Additional Module (hardware) on bus
• DMA controller takes over from CPU for I/O
• is capable of mimicking the processor and,
indeed, of taking over control of the system
from the processor.
• DMA module must use the bus only when the
processor does not need it, or it must force
the processor to suspend operation
temporarily.
• The latter technique is more common and is
referred to as cycle stealing, because the
DMA module in effect steals a bus cycle.
Typical DMA Module Diagram
DMA Operation
• CPU tells DMA controller:-
—Read/Write
—Device address
—Starting address of memory block for data
—Amount of data to be transferred
• CPU carries on with other work
• DMA controller deals with transfer
• DMA controller sends interrupt when
finished
DMA Transfer
Cycle Stealing
• DMA controller takes over bus for a cycle
• Transfer of one word of data
• Not an interrupt
—CPU does not switch context
• CPU suspended just before it accesses bus
—i.e. before an operand or data fetch or a data
write
• Slows down CPU but not as much as CPU
doing transfer
Aside
• What effect does caching memory have
on DMA?
• What about on board cache?
• Hint: how much are the system buses
available?
DMA Configurations (1)

• Single Bus, Detached DMA controller

• Each transfer uses bus twice
—I/O to DMA then DMA to memory
• CPU is suspended twice
DMA Configurations (2)

• Single Bus, Integrated DMA controller

• Controller may support >1 device
• Each transfer uses bus once
—DMA to memory
• CPU is suspended once
DMA Configurations (3)

• Separate I/O Bus

• Bus supports all DMA enabled devices
• Each transfer uses bus once
—DMA to memory
• CPU is suspended once
Fly-By
• While DMA using buses processor idle
• Processor using bus, DMA idle
—Known as fly-by DMA controller
• Data does not pass through and is not
stored in DMA chip
—DMA only between I/O port and memory
—Not between two I/O ports or two memory
locations
• Can do memory to memory via register
• 8237 contains four DMA channels
—Programmed independently
—Any one active
—Numbered 0, 1, 2, and 3
I/O Channels
• I/O devices getting more sophisticated
• e.g. 3D graphics cards
• CPU instructs I/O controller to do transfer
• I/O controller does entire transfer
• Improves speed
—Takes load off CPU
—Dedicated processor is faster
Interfacing
• Connecting devices together
• Bit of wire?
• Dedicated processor/memory/buses?
• E.g. FireWire, InfiniBand
Questions
• List three broad classifications of external,
or peripheral, devices.
• What are drawbacks of Programmed and
Interrupt-Driven I/O
• What are the major functions of an I/O
module?
• List and briefly define three techniques for
performing I/O.
• What is the difference between memory-
mapped I/O and isolated I/O?
• What is DMA controller and its use?