Memory Definitions

• Memory ─ A collection of storage cells together with the

necessary circuits to transfer information to and from
them.
• Memory Organization ─ the basic architectural structure
of a memory in terms of how data is accessed.
• Random Access Memory (RAM) ─ a memory organized
such that data can be transferred to or from any cell (or
collection of cells) in a time that is not dependent upon the
particular cell selected.
• Memory Address ─ A vector of bits that identifies a
particular memory element (or collection of elements).

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 Memory Definitions (Continued)
• Typical data elements are:
– bit ─ a single binary digit
– byte ─ a collection of eight bits accessed together
– word ─ a collection of binary bits whose size is a typical unit of
access for the memory. It is typically a power of two multiple of
bytes (e.g., 1 byte, 2 bytes, 4 bytes, 8 bytes, etc.)
• Memory Data ─ a bit or a collection of bits to be stored
into or accessed from memory cells.
• Memory Operations ─ operations on memory data
supported by the memory unit. Typically, read and write
operations over some data element (bit, byte, word, etc.).

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 Memory Organization
• Organized as an indexed array of words. Value of the
index for each word is the memory address.
• Often organized to fit the needs of a particular computer
architecture. Some historically significant computer
architectures and their associated memory organization:
– Digital Equipment Corporation PDP-8 – used a 12-bit address to
address 4096 12-bit words.
– IBM 360 – used a 24-bit address to address 16,777,216 8-bit
bytes, or 4,194,304 32-bit words.
– Intel 8080 – (8-bit predecessor to the 8086 and the current Intel
processors) used a 16-bit address to address 65,536 8-bit bytes.

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 Memory Block Diagram
n Data Input Lines
n
• A basic memory system is
shown here: k Address Lines Memory
k Unit
• k address lines are decoded to
2 k
Words
address 2 words of memory.
k
1 n Bits per Word
• Each word is n bits. Read
1
• Read and Write are single Write
control lines defining the
simplest of memory operations. n

n Data Output Lines

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 Memory Organization Example

• Example memory
contents: Memory Address Memory
– A memory with 3 Binary Decimal Content
address bits & 8 data bits 000 0 10001111
has: 001 1 11111111
– k = 3 and n = 8 so 23 = 8 010 2 10110001
addresses labeled 0 to 7. 011 3 00000000
– 23 = 8 words of 8-bit data 100 4 10111001
101 5 10000110
11 0 6 00110011
111 7 11001100

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 Basic Memory Operations
• Memory operations require the following:
– Data ─ data written to, or read from, memory as required
by the operation.
– Address ─ specifies the memory location to operate on.
The address lines carry this information into the memory.
Typically: n bits specify locations of 2n words.
– An operation ─ Information sent to the memory and
interpreted as control information which specifies the type
of operation to be performed. Typical operations are
READ and WRITE. Others are READ followed by
WRITE and a variety of operations associated with
delivering blocks of data. Operation signals may also
specify timing info.

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 Basic Memory Operations (continued)
• Read Memory ─ an operation that reads a data value stored in
memory:
– Place a valid address on the address lines.
– Wait for the read data to become stable.
• Write Memory ─ an operation that writes a data value to
memory:
– Place a valid address on the address lines and valid data on the data
lines.
– Toggle the memory write control line
• Sometimes the read or write enable line is defined as a clock
with precise timing information (e.g. Read Clock, Write
Strobe).
– Otherwise, it is just an interface signal.
– Sometimes memory must acknowledge that it has completed the
operation.
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 Memory Operation Timing
• Most basic memories are asynchronous
– Storage in latches or storage of electrical charge
– No clock
• Controlled by control inputs and address
• Timing of signal changes and data observation is critical to the operation
• Read timing:
20 ns
Clock T1 T2 T3 T4 T1

Address Address valid

Memory
enable
Read/
Write

Data Data valid

output
65 ns
Read cycle
KU College of Engineering
Lecture 22 Elec 204: Digital Systems Design
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 Memory Operation Timing
• Write timing:
20 ns

Clock T1 T2 T3 T4 T1

Address Address valid

Memory
enable
Read/
Write
Data
input Data valid

75 ns
Write cycle
• Critical times measured with respect to edges of write pulse (1-0-1):
– Address must be established at least a specified time before 1-0 and held for
at least a specified time after 0-1 to avoid disturbing stored contents of other
addresses
– Data must be established at least a specified time before 0-1 and held for at
least a specified time after 0-1 to write correctly
KU College of Engineering
Lecture 22 Elec 204: Digital Systems Design
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 RAM Integrated Circuits

• Types of random access memory

– Static – information stored in latches
– Dynamic – information stored as electrical charges on capacitors
• Charge “leaks” off
• Periodic refresh of charge required
• Dependence on Power Supply
– Volatile – loses stored information when power turned off
– Non-volatile – retains information when power turned off

KU College of Engineering
Lecture 22 Elec 204: Digital Systems Design
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 Static RAM  Cell
• Array of storage cells used to implement static RAM
• Storage Cell Select
– SR Latch
– Select input for
control
– Dual Rail Data B C
S Q
Inputs B and B
– Dual Rail Data
C
Outputs C and C R Q
B
RAM cell

KU College of Engineering
Lecture 22 Elec 204: Digital Systems Design
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 Static RAM  Bit Slice
• Represents all circuitry that is required for 2n 1-bit words
Word Select
– Multiple RAM cells select
0
B
XC
– Control Lines: S Q

C Word
• Word select i B R Q X select
0
RAM cell
– one for each word RAM cell
Word
• Re ad / Write select
1
• Bit Select Word
select
Select RAM cell

2n  1
– Data Lines: X Word
S Q select
• Data in 2n  1
X RAM cell
R Q
• Data out RAM cell
Read/Write
logic

Data in
S Q Data out
Data in Read/ Bit
Write select
R Q

Write logic Data out

Read logic
Read/ Bit
Write select
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Lecture 22 Elec 204: Digital Systems Design
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 2n-Word  1-Bit RAM IC 4-to-16 Word select
Decoder 0
A3 A3 23 1
2 RAM cell
• To build a RAM IC A2 A2 22 3

from a RAM slice, A1 A1 1

4
5
2
we need: 6 RAM cell
A0 A0 20 7
– Decoder  decodes 16 x 1
RAM
8
9
the n address lines to 10

2n word select lines Data

input
Data
output
11
12

– A 3-state buffer  13
14

– on the data output Read/

Write
15

permits RAM ICs to Memory

enable
RAM cell

be combined into a Read/Write

RAM with c  2n words (a) Symbol logic

Data input Data in

Data out
Read/ Bit
Write select
Data
Read/Write output
Chip select
(b) Block diagram
KU College of Engineering
Lecture 22 Elec 204: Digital Systems Design
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 Cell Arrays and Coincident Selection

• Memory arrays can be very large =>

– Large decoders
– Large fanouts for the bit lines
– The decoder size and fanouts can be reduced by approximately n by
using a coincident selection in
a 2-dimensional array
– Uses two decoders, one for words and one for bits
– Word select becomes Row select
– Bit select becomes Column select
• See next slide for example
– A3 and A2 used for Row select
– A1 and A0 for Column select

KU College of Engineering
Lecture 22 Elec 204: Digital Systems Design
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 Cell Arrays and Coincident Selection
Row decoder
2-to-4
Decoder 0
A3 21
RAM cell RAM cell RAM cell RAM cell
0 1 2 3
A2 20
1

Row RAM cell RAM cell RAM cell RAM cell

select 4 5 6 7
2

RAM cell RAM cell RAM cell RAM cell

8 9 10 11

RAM cell RAM cell RAM cell RAM cell

12 13 14 15

Read/Write Read/Write Read/Write Read/Write

logic logic logic logic

Data in Data in Data in Data in

Data out Data out Data out Data out
Read/ Bit Read/ Bit Read/ Bit Read/ Bit
Write select Write select Write select Write select
Data input
Read/Write

X X X X
Column select Data
0 1 2 3 output
Column 2-to-4 Decoder
decoder with enable
21 20 Enable

A1 A0
Chip select

KU College of Engineering
Lecture 22 Elec 204: Digital Systems Design
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 Making Larger Memories Data In
Decoder
• Using the CS lines, we A1 D-In
A0
can make larger D3
R/W
CS D-Out
memories from smaller
ones by tying all address, A1 D-In
A0
data, and R/W lines in R/W
CS D-Out
D2
parallel, and using the
decoded higher order A1 D-In
A0
address bits to control R/W
CS D-Out
D1
CS.
• Using the 4-Word by 1- A1 D-In
A0
Bit memory from before, R/W
CS D-Out
A3 S1 D0
we construct a 16-Word A2 S0
by A1
Data Out
1-Bit memory.  A0
R/W
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Lecture 22 Elec 204: Digital Systems Design
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 Making Wider Memories
Data In 3210

• To construct wider memories from A1 D-In

narrow ones, we tie the address and A0
R /W
control lines in parallel and keep C S D-O ut
the data lines separate.
• For example, to make a 4-word by A1 D-In
A0
4-bit memory from 4, 4-word by 1- R /W
bit memories  C S D-O ut

• Note: Both 16x1 and 4x4 memories

A1 D-In
take 4-chips A0
and hold 16 bits of data. R /W
C S D-O ut

A1 A1 D-In
A0 A0
R /W R /W
C S D-O ut
CS

Data O ut 3210

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Lecture 22 Elec 204: Digital Systems Design
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