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congestion

Routing congestion occurs when there are insufficient routing tracks for the number of routes needed, particularly in designs below 65nm cell heights. Global and local congestion can arise from factors such as low placement density, high cell density, and inadequate routing resources due to power grid requirements. Solutions to mitigate congestion include adjusting cell placement, reducing local density, and employing congestion-driven placement strategies.

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4 views9 pages

congestion

Routing congestion occurs when there are insufficient routing tracks for the number of routes needed, particularly in designs below 65nm cell heights. Global and local congestion can arise from factors such as low placement density, high cell density, and inadequate routing resources due to power grid requirements. Solutions to mitigate congestion include adjusting cell placement, reducing local density, and employing congestion-driven placement strategies.

Uploaded by

srujannagaram06
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
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Congestion

Routing congestion, which results when


too many routes need to go through an
area with insufficient “routing tracks,”
What is Routing Congestion and why should we care?

• Below 65nm cell heights dictate a decrease from 10-12


routing tracks through them to just 9. This means there are
even fewer routing resources per cell.
• Use of pins on the “metal 2” layer is becoming more
common, providing easier pin access but decreasing routing
resources.
• Metal resources must be dedicated to the power grid for
higher power densities, higher frequencies, or complex
power architectures such as multi-supply voltage or power
shutoff, This means fewer resources for signal routes and a
greater probability of congestion
Global Congestion

• Global interconnect congestion can occur even when there


is low placement density—in fact, in some cases low
placement density can even cause congestion because of
the need for long connections and additional buffering.

• chips with a limited number of routing layers for cost


reasons can also cause global congestion.
Local Congestion

Floorplan congestion : This occurs when the floorplan has macros


and other routing blockages that are too close together to get
enough routes through to connect to the macros. For instance, the
congestion can occur in slots between memories or around
corners of memories. Identifying this type of congestion obviously
requires that a production floorplan be used as an input.
Floorplan-induced congestion
Placement density congestion :

• When there are too many cells too close together (high
placement utilization), then routing all the connections
between them creates congestion.

• This can be the result of the entire design’s utilization being


too high, or perhaps it is localized to a block or region. Often
this happens when timing is tightly constrained.
• Logic-induced congestion:
A high amount of connectivity contained within a small
physical area can overwhelm available routing resources.

ex: large multiplexor. There are just too many connections


that need to be made in too small a space.
Logic-induced congestion
Fixing Congestion

Debug Congestion:

• Cell placement density is high?


• High pin/connectivity density?
• Wrong macro placement?
• Dense power network?

Fix:
• Add placement blockages in channels
• Reduce local cell density using density screens
• Reordering scan chain to reduce congestion
• Placement with congestion-driven& area-recovery options
• Continue the iterations until good congestion results.

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