Lesson 4: Combinational

Circuits

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 COMBINATIONAL LOGIC
CIRCUITS
• A combinational circuit is the digital logic circuit in which the output
depends on the combination of inputs at that point of time with total
disregard to the past state of the inputs. (Output depends only on the
current state of the inputs)
• The digital logic gate is the building block of combinational circuits.
• The function implemented by combinational circuit is depend upon the
Boolean expressions.
• Combinational circuits have no memory, no timing (clocks) or no feedback
loops
• On the other hand, sequential logic circuits, consists of both logic gates
and memory elements such as flip-flops. Sequential circuits have feed back
mechanisms.
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• Figure below shows the combinational circuit having n
inputs and and m outputs. The n number of inputs
shows that there are 2^n possible combinations of
bits at the input. Therefore, the output is expressed in
terms m Boolean expressions.

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• Examples of Combinational circuits:
• All logic circuits considered in the previous lessons
• Decoder, Encoder, Multiplexer, De-multiplexer, Adders, subtructors and
comparator
• Examples of Sequential circuits:
• Flip flops(JK,SR,T,D) and latches(SR,D)

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DECODERS
• A decoder is a logic circuit that accepts a set of inputs that represents a binary
number and activates only the output that corresponds to that input number.
• In other words, a decoder circuit looks at its inputs, determines which binary
number is present there, and activates the one output that corresponds to
that number; all other outputs remain inactive.
• It is a combinational circuit that converts N bits of binary information of input
lines to a maximum of 2N unique output lines.
• In its general form, a decoder has N input lines to handle N bits and form one
to 2 N output lines to indicate the presence of one or more N-bit combinations
• An AND gate can be used as the basic decoding element because it produces a
HIGH output only when all inputs are HIGH
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General Decoder Diagram

A0
O0
N inputs A1 DECODER
O1

A2 O2
M outputs(2N )

AN-1 OM-1
Only one output
input
is HIGH for each
codes
input code
# There are 2N possible input combinations, from A0 to AN1.
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• Because each of the N inputs can be 0 or 1, there 2N are possible input combinations
or codes. For each of these input combinations, only one of the M outputs will be
active HIGH (1); all the other outputs are LOW (0).
• Many decoders are designed to produce active-LOW outputs, where only the
selected output is LOW while all others are HIGH. This situation is usually indicated
by the presence of small circles on the output lines in the decoder diagram.
• Note that for a given input code, the only output that is active (HIGH) is the one
corresponding to the decimal equivalent of the binary input code (e.g., output O 6
goes HIGH only when CBA = 1102 = 610).
• Some decoders do not utilize all of the 2N possible input codes but only certain ones.
For example, a BCD-to-decimal decoder has a four-bit input code and ten output lines
that correspond to the ten BCD code groups 0000 through 1001. Decoders of this
type are often designed so that if any of the unused codes are applied to the input,
none of the outputs will be activated.
• Usually decoders are designed as an N to M line decoder where N= input lines and
M= output lines
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2 to 4 line Decoder (1 of 4)
A0
O0 A0 O0
A1
A1
O1 O1

O2 O2

O3 O3
EN EN

(a)Logic symbol for active HIGH

(b)Logic symbol for active LOW

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• If an active-LOW output (74138, one of the output will
low and the rest will be high) is required for each
decoded number, the entire decoder can be
implemented with
• NAND gates
• Inverters

• If an active-HIGH output (74139, one of the output will

high and the rest will be low) is required for each
decoded number, the entire decoder can be
implemented with
• AND gates
• Inverters

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Design of 2 –to-4 decoder (Active High Outputs)

Logic Symbol Truth table

The output expression
Logic circuit
Active Low outputs
Decoders with Enable Inputs
• Some decoders have one or more ENABLE inputs that are used to
control the operation of the decoder. For example, refer to the
decoder in Figure (a) above and visualize having a common ENABLE
line connected to a fourth input of each gate.
• With this ENABLE line held HIGH, the decoder will function normally,
and A0 A1 input code will determine which output is HIGH.
• With ENABLE held LOW, however, all of the outputs will be forced to
the LOW state regardless of the levels at the A0 A1 inputs. Thus, the
decoder is enabled only if ENABLE is HIGH.

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Truth table of 2-4 Decoder (Active High)
INPUTS ENABLE OUTPUTS
A1 A0 EN O3 O2 O1 O0
X X 0 0 0 0 0 O0= A1’AO’
0 0 1 0 0 0 1 O1= A1’AO
0 1 1 0 0 1 0 O2= A1AO ‘
1 0 1 0 1 0 0 O3= A1AO
1 1 1 1 0 0 0

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Implementation of 2 to 4 with
Enabled input
A1
A0

O0

O
1

0
2

O3

EN
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• As we can see in the truth table for each input combination, one
output line is activated i.e. the output line corresponding to the input
combination becomes 1 while other lines remain inactive(LOW).
• For example an input of 01 at the input will activate line O1.
• Notice also that each output of the decoder is actually a minterm
resulting from certain combination of inputs i.e. O0 = A1’AO’(Minterm
Mo ) corresponds to output 00, O1= A1’A0 ’(Minterm M1 ) corresponds
to output 01

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2-to-4-Line Decoder
(with Enable input)-Active LOW output

EN

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• The circuit operates with complemented outputs and a complement
enable input. The decoder is enabled when EN is equal to 0.
• Only one output can be equal to 0 at any given time, all other outputs
are equal to 1.
• The output whose value is equal to 0 represents the minterm selected
by inputs A and B
• The circuit is disabled when EN is equal to 1

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3-to-8 line Decoder
• In a 3-8 decoder, there are three inputs and eight outputs.
• This decoder can be referred to in several ways. It can be called a 3-
line-to- 8-line decoder, because it has three input lines and eight
output lines.
• It could also be called a binary-octal decoder or converters because it
takes a three bit binary input code and activates the one of the eight
outputs corresponding to that code.
• It is also referred to as a 1-of-8 decoder, because only 1 of the 8
outputs is activated at one time

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BCD -to- Decimal decoders

•The BCD- to-decimal decoder converts each BCD code into one of Ten
Positionable decimal digit indications. It is frequently referred as a 4-
line -to- 10 line decoder
•The method of implementation is that only ten decoding gates are
required because the BCD code represents only the ten decimal digits 0
through 9.
•Each of these decoding functions is implemented with NAND gates to
provide active -LOW outputs. If an active HIGH output is required,
AND gates are used for decoding

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Logic diagram of BCD - decimal decoder
(Active LOW output)

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Applications of Decoders
•Decoders are used in many types of applications. One example
is in computers for I/O selection as in previous slide

•Computer must communicate with a variety of external devices

called peripherals by sending and/or receiving data through what
is known as input/output (I/O) ports

•Each I/O port has a number, called an address, which uniquely

identifies it. When the computer wants to communicate with a
particular device, it issues the appropriate address code for the
I/O port to which that particular device is connected . The binary
port address is decoded and appropriate decoder output is
activated to enable the I/O port (I/O addressing)

•Binary data are transferred within the computer on a data bus,

which is a set of parallel lines

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Other Applications
• The applications of decoder involve in the
making of various electronic projects.
• War- Field -Flying Robot with a Night Vision Flying Camera
• Robotic Vehicle with Metal Detector
• RF-based Home Automation System
• Speed Synchronization of Multiple Motors in Industries
• Automatic Wireless Health Monitoring System in Hospitals for Patients
• Secret Code Enabled Secure Communication using RF Technology
ENCODERS
• A digital circuit that performs the reverse operation of a decoder.
• Encoders are digital ICs used for encoding. By encoding, we mean generating a digital
binary code for every input.
• An encoder has a number of input lines , ONLY one of which is activated at a given
time, and produce an N bit output code, depending on which input is activated.
• For example in an active HIGH input encoder, ONLY one input can be logic 1 at any
given time. All other inputs must be zeros (0’s)
• We can say that an encoder has 2N inputs and N output lines
• An encoder accepts an active LOW/HIGH level on one of its inputs representing digits
such as decimal or octal and converts it to a coded output such as BCD or binary
• NB: Output lines generate the binary code corresponding to active input

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Block diagram for active high
input encoder
I0
O0
I1 O1
2N inputs only ENCODER
one HIGH at a I2 O2
time N outputs

IM-1 ON-1
Output lines generate the binary
code corresponding to active
M= Number of inputs input
N= Number of outputs
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4 to 2 encoder (active HIGH
inputs)
• Accepts 4 inputs lines and produce 2 bits output code
corresponding to the activated input

I0
O0 LSB
I1 O1 MSB
4 to 2
I2 ENCODER
I3

M=4, N=2
LOGIC SYMBOL

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Truth table
INPUTS OUTPUTS
I3 I2 I1 I0 O1 O0
0 0 0 1 0 0
0 0 1 0 0 1
0 1 0 0 1 0
1 0 0 0 1 1

O0 = I1 + I3
O1 = I2 + I3

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Logic circuit – 4 to 2

I I I I
3 2 1 0

O0 = I + I
1 2
3

O = I + I
1
2 3

Note that the I0 is not connected to the logic gates because the
encoder outputs will normally be at 0 0 when none of the inputs
I1 to I3 is HIGH
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An Octal to binary encoder (8 line to 3 line
encoder) with active HIGH inputs
• Accepts eight input lines and produce three bit
output code corresponding to the activated input.
• It has eight inputs, one for each of the octal digits and
three outputs that generate the corresponding binary
number

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8 to 3 line encoder (active HIGH
inputs)

I0
O0 LSB
I1 O1 MSB
8 to 3
I2 ENCODER O2

I7

M=8, N=3
LOGIC SYMBOL

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Truth table
INPUTS OUTPUTS
I7 I6 I5 I4 I3 I2 I1 I0 O2 O1 O0
0 0 0 0 0 0 0 1 0 0 0
0 0 0 0 0 0 1 0 0 0 1
0 0 0 0 0 1 0 0 0 1 0
0 0 0 0 1 0 0 0 0 1 1
0 0 0 1 0 0 0 0 1 0 0
0 0 1 0 0 0 0 0 1 0 1
0 1 0 0 0 0 0 0 1 1 0
1 0 0 0 0 0 0 0 1 1 1
O0 = I1 + I3 + I5 + I7
O1 = I2 + I3 + I6 + I7
O2 = I4 + I5 + I6 + I7

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8 to 3 line encoder Logic circuit

I I I I I I I I
7 6 5 4 3 2 1 0

O0 = I + I + I +I
1 3 5 7

O
1
= I + I + I +I
2 3 6 7

O2
= I + I +I +I
4 5 6 7

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• Limitations :
• I0 has no effect on the output
• Only one input can be activated at a given time
• Application:
• Handling multiple devices requests
But, no simultaneous requests
• Establishing priorities solve the problem of multiple
requests (thus priority encoders)

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Priority Encoders
• In this type of encoder, a priority is assigned to each input so that, when
more than one input is simultaneously active, the input with the highest
priority is encoded.
• For example if I5 and I7 are active at the same time line I5 will be ignored and
I7 will be encoded
• Therefore, the output code will be 111
• You will note that with the previous encoders if two or more inputs are
active simultaneously, the output produces undefined conditions.
• Priority encoders are used extensively in digital and computer systems as
microprocessor interrupt controllers where they detect the highest priority
input.
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Design 8 line to 3 line priority encoder with
active high inputs

Logic Symbol
Truth table
INPUTS OUTPUT CODES
D7 D6 D5 D4 D3 D2 D1 D0 Q2 Q1 Q0
0 0 0 0 0 0 0 1 0 0 0
0 0 0 0 0 0 1 X 0 0 1
0 0 0 0 0 1 X X 0 1 0
0 0 0 0 1 X X X 0 1 1
0 0 0 1 X X X X 1 0 0
0 0 1 X X X X X 1 0 1
0 1 X X X X X X 1 1 0
1 X X X X X X X 1 1 1

Where X equals “don't care”, that is it can be at a logic “0” level or at a

logic “1” level.

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Output Expressions 1/2
Output Expressions 2/2

Then the final Boolean expression for the priority

encoder including the zero inputs is defined as:
• In practice these zero inputs would be ignored allowing the
implementation of the final Boolean expression for the outputs of the
8-to-3 priority encoder.
MULTIPLEXER (Data selector)
• Multiplexing means transmitting a large number of information units
over a smaller number of channels or lines.
• Therefore, a digital multiplexer or a data selector is a logic circuit that
accepts several digital data inputs and selects one of them at any
given time to pass to the output.
• The routing of the desired data inputs to the output is controlled by
SELECT inputs often referred to as ADDRESS inputs
• Normally, there are 2N input lines and N select lines whose bit
combinations determine which input is selected
• It has 1 output
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Block diagram for MUX

2N (input source) 1

MUX
Output Destination

N (Select lines)

SIT 112_INTRODUCTION TO DIGITAL ELECTRONICS 43

 MUX types

Normally MUX are designed as a 2N to 1 MUX

There are 2N inputs and N select lines
 2-to-1 (1 select line) 2:1
 4-to-1 (2 select lines) 4:1
 8-to-1 (3 select lines) 8:1
 16-to-1 (4 select lines) 16:1

SIT 112_INTRODUCTION TO DIGITAL ELECTRONICS 44

4-to-1 MUX
MP3 player
docking system

Laptop sound D0
card D1
D2 Y Surround sound
Digital satellite D3 system

Digital cable TV

(MSB)A B (LSB)

SIT 112_INTRODUCTION TO DIGITAL ELECTRONICS 45

Truth table
A B OUTPUT (Y)
0 0 Y= D0 (MP3)
0 1 Y=D1 (Laptop)
1 0 Y=D2 (Satellite)
1 1 Y=D3 ( Cable TV)

SIT 112_INTRODUCTION TO DIGITAL ELECTRONICS 46

Logic circuit
D
0
1

D
1
2 Y

D
2
3

D3
4

A B
SELECT LINES

SIT 112_INTRODUCTION TO DIGITAL ELECTRONICS 47

• In general Y= D0A’B’ + D1A’B + D2AB’ + D3AB
• With B =0 AND A=0, the above expression becomes
Y= D0.1.1 + D1.1.0 + D2.0.1 + D3.0.0
=> Y = D0 thus gate 1 is enabled which indicates that Y will be identical
to the input Do which in turn can be a fixed logic level or a time varying
logic signal

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Multiplexer Applications
• Data selection
• Data routing
• Operation sequencing
• Parallel to serial conversion

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 DEMULTIPLEXER (Data
distributor)
• A multiplexer takes several inputs and transmits one of them to the
output.
• A demultiplexer performs the reverse operation. It takes a single input
and distribute it over several outputs.
• Demultiplexing is the process of receiving information from one channel
and distributing it over several channels
• It can also be defined as a device that receives information on a single
line and transmits this information on one of the 2N possible output lines.
• The selection of a single output line is controlled by bit values of N select
lines

SIT 112_INTRODUCTION TO DIGITAL ELECTRONICS 50

Types of DEMUX
• 1- to – 2 ( 1 selet line) 1:2
• 1-to-4 (2 selet lines) 1:4
• 1-to-8 (3 selet lines) 1:8
• 1-to-16 (4 selet lines) 1:16

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Logic symbol

1 2N

DEMUX
Input source Output (destination)

Select lines

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1:4 DEMUX

B/W Laser printer

O0

O1 Fax machine

DEMUX
I
Computer O2

O3 Colour ink jet printer

Pen plotter

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Truth table
SELECT LINES OUTPUT
A B Selected destination
0 0 B/W Laser printer
0 1 Fax machine
1 0 Colour ink jet printer
1 1 Pen plotter

SELECT LINES OUTPUT

A B O3 O2 O1 O0
0 0 0 0 0 I
0 1 0 0 I 0
1 0 0 I 0 0
1 1 I 0 0 0

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Output expressions
• O0= A’.B’.I
• O1= A’.B.I
• O2=A.B’.I
• O3=A.B.I
Logic circuit
I O0

O1

O
2

O3

A B
SELECT LINES

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• Note the serial data (I) is applied to all the AND gates
• The data select lines A and B enable only one AND gate at a time.
• The serial data at the input will be passed by the selected gate to one
of the four outputs O0 to O3

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