The 8085 Microprocessor Architecture

Dr. Kuda Nageswara Rao,

B.E., M.Tech., Ph.D

Associate Professor Dept. of Computer Science & Systems Engineering ANDHRA UNIVERSITY

Email : [email protected] Mobile : 99638 47111

8085
40 pin DIP. +5V 3 - 5MHz
ADD BUS DATA BUS CONTROL STATUS POWER SUPPLY AND FREQ EXTERNALLY INITIATED SIGNALS SERIAL I/O PORTS

5V GND
40 20 X1 X2
21 28 HIGH ORDER ADD BUS

SID 5 SOD 4 TRAP 6 RST7.5 7 RST6.5 8 RST5.5 9 INTR 10 READY 35 HOLD 39 RESET IN 36 INTA 11 HLDA 38

12 19 MUX ADD/ DATA BUS

37

30 ALE 29 S0 33 S1 34 IO/M 32 RD 31 WR

RESET OUT

CLK OUT

8085 functional block diagram

Interrupt control Serial I/O control
MUX

Accumu

Temp Reg

Instru Register (8)

Reg Select

Flags

Instru Decoder

W Z Temp Reg (8) Temp Reg (8) B C (8) (8) D E (8) (8) H L (8) (8) Stack pointer (16) Program counter (16) Incrementer/decrementer Latch (16)

Address buffer (8)

Data/Add buffer (8)

Timing & control

The 8085 and Its Busses

The 8085 is an 8-bit general purpose microprocessor that can address 64K Byte of memory. It has 40 pins and uses +5V for power. It can run at a maximum frequency of 3 MHz. The pins on the chip can be grouped into 6 groups: Address Bus. Data Bus. Control and Status Signals. Power supply and frequency. Externally Initiated Signals. Serial I/O ports.

External control signals

INTR interrupt request. Input signal INTA interrupt acknowledge. o/p signal. RST7.5,RST 6.5, RST5.5 restart interrupts. Vectored interrupts. Higher priority. TRAP - Nonmaskable interrupt. Highest priority. Hold request for the control of buses. O/P signal HLDA Hold Acknowledge. I/P signal READY I/P signal. When low Mp waits for integral number of clock cycles until it goes high.

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Bus control signals

IO/M RD MEMR IOWR

8085
MEMWR WR IOWR

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ADD/DATA bus
A15

A8 ALE AD7 AD6 AD5 G DQ

Address bus. higher 8 bit

AD0

OC GND

Address bus. Lower 8 bit Data bus

Address bus 16 bits

A8 to A15 unidirectional. Higher 8 bit AD0 to AD7 multiplexed with data. This pins are bidirectional when used as data bus.

Data bus 8 bit long: AD0 to AD7

The Address and Data Busses

The address bus has 8 signal lines A8 A15 which are unidirectional. The other 8 address bits are multiplexed (time shared) with the 8 data bits. So, the bits AD0 AD7 are bi-directional and serve as A0 A7 and D0 D7 at the same time. During the execution of the instruction, these lines carry the address bits during the early part, then during the late parts of the execution, they carry the 8 data bits. In order to separate the address from the data, we can use a latch to save the value before the function of the bits changes.

Control signals
ALE active high output used to latch the lower 8 address bits. RD, WR - active low output signals. IO/M output signal to differentiate memory and IO operation. S1 and S0 status output signal. Identify various operations.
Machine cycle IO/M S1 S0 Control signals

Opcode fetch
Memory read Memory write I/O read I/O write Interrupt Ackn Halt Hold Reset

0
0 0 1 1 1 Z Z Z

1
1 0 1 0 1 0 X X

1
0 1 0 1 1 0 X X

RD=0
RD=0 WR=0 RD=0 WR=0 INTA=0 RD, WR =Z and INTA=1

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The Control and Status Signals

There are 4 main control and status signals. These are: ALE: Address Latch Enable. This signal is a pulse that become 1 when the AD0 AD7 lines have an address on them. It becomes 0 after that. This signal can be used to enable a latch to save the address bits from the AD lines. RD: Read. Active low. WR: Write. Active low. IO/M: This signal specifies whether the operation is a memory operation (IO/M=0) or an I/O operation (IO/M=1). S1 and S0 : Status signals to specify the kind of operation being performed .Usually un-used in small systems.

Frequency Control Signals

There are 3 important pins in the frequency control group. X0 and X1 are the inputs from the crystal or clock generating circuit. The frequency is internally divided by 2. So, to run the microprocessor at 3 MHz, a clock running at 6 MHz should be connected to the X0 and X1 pins.
CLK (OUT): An output clock pin to drive the clock of the rest of the system. We will discuss the rest of the control signals as we get to them.

Microprocessor Communication and Bus Timing

To understand how the microprocessor operates and uses these different signals, we should study the process of communication between the microprocessor and memory during a memory read or write operation. Lets look at timing and the data flow of an instruction fetch operation. (Example 3.1)

Steps For Fetching an Instruction

Lets assume that we are trying to fetch the instruction at memory location 2005. That means that the program counter is now set to that value. The following is the sequence of operations: The program counter places the address value on the address bus and the controller issues a RD signal. The memorys address decoder gets the value and determines which memory location is being accessed. The value in the memory location is placed on the data bus. The value on the data bus is read into the instruction decoder inside the microprocessor. After decoding the instruction, the control unit issues the proper control signals to perform the operation.

Timing Signals For Fetching an Instruction

Now, lets look at the exact timing of this sequence of events as that is extremely important. (figure 3.3) At T1 , the high order 8 address bits (20H) are placed on the address lines A8 A15 and the low order bits are placed on AD7AD0. The ALE signal goes high to indicate that AD0 AD8 are carrying an address. At exactly the same time, the IO/M signal goes low to indicate a memory operation. At the beginning of the T2 cycle, the low order 8 address bits are removed from AD7 AD0 and the controller sends the Read (RD) signal to the memory. The signal remains low (active) for two clock periods to allow for slow devices. During T2 , memory places the data from the memory location on the lines AD7 AD0 . During T3 the RD signal is Disabled (goes high). This turns off the output Tri-state buffers in the memory. That makes the AD7 AD0 lines go to high impedence mode.

Demultiplexing AD7-AD0
From the above description, it becomes obvious that the AD7 AD0 lines are serving a dual purpose and that they need to be demultiplexed to get all the information. The high order bits of the address remain on the bus for three clock periods. However, the low order bits remain for only one clock period and they would be lost if they are not saved externally. Also, notice that the low order bits of the address disappear when they are needed most. To make sure we have the entire address for the full three clock cycles, we will use an external latch to save the value of AD7 AD0 when it is carrying the address bits. We use the ALE signal to enable this latch.

Demultiplexing AD7-AD0
8085
A15-A8 ALE AD7-AD0 Latch

A7- A0

D7- D0

Given that ALE operates as a pulse during T1, we will be able to latch the address. Then when ALE goes low, the address is saved and the AD7 AD0 lines can be used for their purpose as the bi-directional data lines.

Cycles and States

From the above discussion, we can define terms that will become handy later on: T- State: One subdivision of an operation. A T-state lasts for one clock period. An instructions execution length is usually measured in a number of T-states. (clock cycles). Machine Cycle: The time required to complete one operation of accessing memory, I/O, or acknowledging an external request. This cycle may consist of 3 to 6 T-states. Instruction Cycle: The time required to complete the execution of an instruction. In the 8085, an instruction cycle may consist of 1 to 6 machine cycles.

Generating Control Signals

The 8085 generates a single RD signal. However, the signal needs to be used with both memory and I/O. So, it must be combined with the IO/M signal to generate different control signals for the memory and I/O. Keeping in mind the operation of the IO/M signal we can use the following circuitry to generate the right set of signals:

A closer look at the 8085 Architecture

Previously we discussed the 8085 from a programmers perspective.
Now, lets look at some of its features with more detail.

The ALU
In addition to the arithmetic & logic circuits, the ALU includes the accumulator, which is part of every arithmetic & logic operation. Also, the ALU includes a temporary register used for holding data temporarily during the execution of the operation. This temporary register is not accessible by the programmer.

The Flags register

There is also the flags register whose bits are affected by the arithmetic & logic operations. S-sign flag The sign flag is set if bit D7 of the accumulator is set after an arithmetic or logic operation. Z-zero flag Set if the result of the ALU operation is 0. Otherwise is reset. This flag is affected by operations on the accumulator as well as other registers. (DCR B). AC-Auxiliary Carry This flag is set when a carry is generated from bit D3 and passed to D4 . This flag is used only internally for BCD operations. (Section 10.5 describes BCD addition including the DAA instruction). P-Parity flag After an ALU operation if the result has an even # of 1s the pflag is set. Otherwise it is cleared. So, the flag can be used to indicate even parity. CY-carry flag Discussed earlier

More on the 8085 machine cycles

The 8085 executes several types of instructions with each requiring a different number of operations of different types. However, the operations can be grouped into a small set. The three main types are: Memory Read and Write. I/O Read and Write. Request Acknowledge.
These can be further divided into various operations (machine cycles).

Opcode Fetch Machine Cycle

The first step of executing any instruction is the Opcode fetch cycle. In this cycle, the microprocessor brings in the instructions Opcode from memory. To differentiate this machine cycle from the very similar memory read cycle, the control & status signals are set as follows: IO/M=0, s0 and s1 are both 1. This machine cycle has four T-states. The 8085 uses the first 3 T-states to fetch the opcode. T4 is used to decode and execute it. It is also possible for an instruction to have 6 T-states in an opcode fetch machine cycle.

Memory Read Machine Cycle

The memory read machine cycle is exactly the same as the opcode fetch except:
It only has 3 T-states The s0 signal is set to 0 instead.

The Memory Read Machine Cycle

To understand the memory read machine cycle, lets study the execution of the following instruction: 3E 2000H MVI A, 32 2001H 32 In memory, this instruction looks like: The first byte 3EH represents the opcode for loading a byte into the accumulator (MVI A), the second byte is the data to be loaded. The 8085 needs to read these two bytes from memory before it can execute the instruction. Therefore, it will need at least two machine cycles. The first machine cycle is the opcode fetch discussed earlier. The second machine cycle is the Memory Read Cycle. Figure 3.10 page 83.

Machine Cycles vs. Number of bytes in the instruction

Machine cycles and instruction length, do not have a direct relationship. To illustrate lets look at the machine cycles needed to execute the following instruction. STA 2065H
This is a 3-byte instruction requiring 4 machine cycles and 13 T-states. 32H 2010H 2011H 65H The machine code will be stored 20H 2012H in memory as shown to the right This instruction requires the following 4 machine cycles:
Opcode fetch to fetch the opcode (32H) from location 2010H, decode it and determine that 2 more bytes are needed (4 T-states). Memory read to read the low order byte of the address (65H) (3 T-states). Memory read to read the high order byte of the address (20H) (3 T-states). A memory write to write the contents of the accumulator into the memory location.

The Memory Write Operation

In a memory write operation:
The 8085 places the address (2065H) on the address bus Identifies the operation as a memory write (IO/M=0, s1=0, s0=1). Places the contents of the accumulator on the data bus and asserts the signal WR. During the last T-state, the contents of the data bus are saved into the memory location.

Memory interfacing
There needs to be a lot of interaction between the microprocessor and the memory for the exchange of information during program execution. Memory has its requirements on control signals and their timing. The microprocessor has its requirements as well. The interfacing operation is simply the matching of
these requirements.

Memory structure & its requirements

Data Lines

RAM
Input Buffer WR

ROM

Address Lines

CS

Address Lines

CS

Output Buffer

RD

Output Buffer

RD

Data Lines

Date Lines

The process of interfacing the above two chips is the same. However, the ROM does not have a WR signal.

Interfacing Memory
Accessing memory can be summarized into the following three steps: Select the chip. Identify the memory register. Enable the appropriate buffer. Translating this to microprocessor domain: The microprocessor places a 16-bit address on the address bus. Part of the address bus will select the chip and the other part will go through the address decoder to select the register. The signals IO/M and RD combined indicate that a memory read operation is in progress. The MEMR signal can be used to enable the RD line on the memory chip.

Address decoding
The result of address decoding is the identification of a register for a given address. A large part of the address bus is usually connected directly to the address inputs of the memory chip. This portion is decoded internally within the chip. What concerns us is the other part that must be decoded externally to select the chip. This can be done either using logic gates or a decoder.

The Overall Picture

Putting all of the concepts together, we get:
A15- A10
Chip Selection Circuit

8085
A15-A8
ALE AD7-AD0 Latch
CS

A9- A0
A7- A0

1K Byte Memory Chip

WR RD

IO/M

D7- D0
RD

WR