Computer Architecture and

organization

M.Nivedita
Assistant Professor
SCOPE
VIT Chennai
 Books
 David A. Patterson and John L. Hennessy, Computer
Organization and Design -The Hardware / Software Interface
6th Edition, Morgan Kaufmann, 2020.

 Computer Architecture and Organization-Designing for

Performance, William Stallings, Tenth edition, Pearson
Education series, 2016 .

 Carl Hamacher, Zvonko Vranesic, Safwat Zaky, Computer

organization, Mc Graw Hill, Fifth edition, Reprint 2011.
 Assesment

 CAT – I - 15
 CAT – II - 15
 Digital ASSIGNMENT - 30
 Term End Exam - 40
 Objective
 How computers work, basic principles.
 How to analyze their performance.
 How computers are designed and built.
 To teach arithmetic of computers.
 To provide knowledge of memory technologies, interfacing
techniques and subsystem devices and the issues in that.
 Motivation
This knowledge will be useful if you need to

 Design/build a new version of a computer

 Improve software performance
 Purchase a computer
 Provide a solution with an embedded computer
 What is computer
architecture?
• Computer architecture deals with the functionality of every hardware unit of
a CPU. i.e. what a specific hardware unit works in a computer

•Computer architecture is a specification detailing how a set of software and

hardware technology standards interact to form a computer system or
platform.
 What is computer
Organization?
• Computer organization deals with the implementation of every
hardware unit of a CPU. i.e. how a specific hardware unit
works in a computer

• It refers to the operational units of the hardware device and

interconnections between various hardware devices realize the
architectural specifications.
 All Intel x86 family will share the same basic
architecture.
 The IBM System/370 family will share the same basic

architecture.
 This helps to enable code compatibility.(backwards)
 But organisation is different for different versions.
 I/O Chan
Link
ISA
API
Interfaces
Technology
IR

Regs

Machine Organization

Applications Computer
Architect Measurement &
Evaluation
 Structure and Function
 Structure is the way in which components relate to each
other.

 Function is the operation of individual components as

part of the structure. The computer functions are,
◦ Data processing
◦ Data storage
◦ Data movement
◦ Control
 Functional View
Operating Environment (Source, Destination of Data)

Data Movement
apparatus

Control Mechanism

Data Storage Data Processing Facility

Facility
 Data Movement

movement

control

Storage Processing
 Storage

Movement

Control

Storage Process
Processing from/to storage

Movement

Control

Storage Process
Processing from storage to I/O

Movement

Control

Storage Process
 Structure

Communication Lines
Peripherals
Computer

Storage
Processing
 Structure - Top Level

Peripherals Computer

Central Main
Processing Memory
Unit

Computer
Systems
Interconnection

Input
Output
Communication
lines
 Structure - The CPU

CPU

Computer Arithmetic
Registers and
I/O Login Unit
System CPU
Bus
Internal CPU
Memory Interconnection

Control
Unit
 Structure - The Control Unit

Control Unit

CPU
Sequencing
ALU Login
Control
Internal
Unit
Bus
Control Unit
Registers Registers and
Decoders

Control
Memory
 Structural components
 CPU – Processor
 Main Memory – Stores data
 I/O – Moves the data
 System Interconnection
 Control Unit – controls operation
 ALU – data processing
 Registers – storage internal to CPU
 CPU Interconnection
 ENIAC

◦ ENIAC (Electronic Numerical Integrator And Computer)

◦ 1st general-purpose electronic digital computer.
◦ Designed by John Mauchly and John Presper Eckert at University of
pennsylvania.
◦ Funded by US BRL (Ballistic Research Lab) to develop range and
trajectory tables for new weapons
 Until then, BRL employeed more than 200 people who, using desktop
calculators to solve the necessary ballistics equations
◦ The proposal accepted in 1943, the machine completed in 1946, and
dismantled in 1955
◦ Characteristics
 30 tons, 15000 square feet, 18000 vacuum tubes, 140 KW power
dissipation
 Decimal machine
 20 accumulators each holding 10-digit decimal number
 Each digit is represented by a ring of 10 vacuum tubes
 5,000 additions per second

 Manually programmed by setting switches and plugging/unplugging

cables
ENIAC
 Von Neumann Machine
 The task of entering and altering programs for the ENIAC was
extremely tedious.
 The programming process could be facilitated if the program
could be represented in a form suitable for storing in memory
alongside the data.
 Then, a computer could get its instructions by reading them
from memory, and a program could be set or altered by setting
the values of a portion of memory.
 The Stored Program Concept

 Von Neumann’s proposal was to store the program instructions

right along with the data

 The stored program concept was proposed about fifty years

ago; to this day, it is the fundamental architecture that fuels
computers.
 von Neumann/Turing
 Stored Program concept
 Main memory storing instructions and data
 ALU operating on binary data
 Control unit interpreting instructions from memory and
executing
 Input and output equipment operated by control unit
 Princeton Institute for Advanced Studies
◦ IAS
 Completed 1952
The Von Neumann Machine & IAS
Structure of IAS Computer
 The Stored Program Concept and its
Implications
 The Stored Program concept had several technical
ramifications:
◦ Four key sub-components operate together to make the
stored program concept work
◦ The process that moves information through the sub-
components is called the “fetch execute” cycle
◦ Unless otherwise indicated, program instructions are
executed in sequential order
 Four Sub-Components
 There are four sub-components in von Neumann architecture:
◦ Memory
◦ Input/Output (called “IO”)
◦ Arithmetic-Logic Unit
◦ Control Unit
 While only 4 sub-components are called out, there is a 5th, key
player in this operation: a bus, or wire, that connects the
components together and over which data flows from one sub-
component to another
 Let’s look at each sub-component in more detail …
 Memory
 As you already know, there are several different flavors of
memory
 Each type of memory represents cost/benefit tradeoffs
between capability and cost .
Memory Types: RAM
 RAM is typically volatile memory (meaning it doesn’t retain
voltage settings once power is removed)
 RAM is an array of cells, each with a unique address
 A cell is the minimum unit of access. Originally, this was 8
bits taken together as a byte. In today’s computer, word-sized
cells (16 bits, grouped in 4) are more typical.
 RAM gets its name from its access performance. In RAM
memory, theoretically, it would take the same amount of time
to access any memory cell, regardless of its location with the
memory bank (“random” access).
Memory Types: ROM
 It gets its name from its cell-protection feature. This type of
memory cell can be read from, but not written to.
 Unlike RAM, ROM is non-volatile; it retains its settings after
power is removed.
 ROM is more expensive than RAM, and to protect this
investment, you only store critical information in ROM …
ROM (Read Only
Memory)
Types of ROM:

◦ Programmable ROM, where the data is written after the memory chip has been
created. It is non-volatile.

◦ Erasable Programmable ROM, where the data on this non-volatile memory chip
can be erased by exposing it to high-intensity UV light.

◦ Electrically Erasable Programmable ROM, where the data on this non-volatile

memory chip can be electrically erased using field electron emission.
Memory Types: Registers
 There is a third, key type of memory in every computer –
registers.
 Register cells are powerful, costly, and physically located
close to the heart of computing.
 Registers are the main participants in the fetch execute cycle.
Memory Types: Other
 Modern computers include other forms of memory, such as
cache memory.
 Remember, memory types exist at different trade offs.
I/O: Input and Output
 There is both a human-machine interface and a machine-
machine interface to I/O.
◦ Examples of the human-machine interface include a
keyboard, screen or printer.
◦ Examples of the machine-machine interface include things
like mass storage and secondary storage devices.
 Input and output devices are the least standardized of the
various sub-components, which means that you have to pay
extra special attention to make certain that your input or
output devices are compatible with your machine.
The ALU
 The third component in the von Neumann architecture is
called the Arithmetic Logic Unit.
 This is the subcomponent that performs the arithmetic and
logic operations for which we have been building parts.
 The ALU is the “brain” of the computer.
 It contains the circuitry to perform addition, subtraction,
multiplication and division, as well as logical comparisons
(less than, equal to and greater than).
Control Unit

 The last of the four subcomponents is the Control Unit.

 The control unit drives the fetch and execute cycle.
 Controls which address is loaded into the memory and what
operation is taking place in the data.
 IAS - details
 The memory of the IAS consists of 1000 storage
locations, called words, of 40 binary digits each.
 Both data and instructions are stored there.
 Each number is represented by a sign bit and a 39-bit

value.
 A word may also contain two 20-bit instructions, with

each instruction consisting of an 8-bit operation code

specifying the operation to be performed and 12-bit
address designating one of the words in memory.
 IAS Memory Formats

NUMBER WORD
0 1 39

Sign
Bit
 Instruction Word

Left Instruction Right Instruction

0 8 20 28 39

Opcode Opcode Address

Address
 Set of registers (storage in CPU)
◦ Memory Buffer Register
◦ Memory Address Register
◦ Instruction Register
◦ Instruction Buffer Register
◦ Program Counter
◦ Accumulator
◦ Multiplier Quotient
Expanded Structure of IAS Computer
 Registers
 MBR – Memory Buffer Register contains a word to be stored
in memory or sent to the I/O unit or is used to receive a word
from memory.
 MAR – Memory Address Register specifies the address of the
word to be written from MBR, to be read into
MBR.
 Instruction Register (IR) - 8 bit opcode instruction being
executed.
 Instruction Buffer Register (IBR)– hold the right hand
instruction from a word in memory.
 Program Counter(PC) – address of the next instruction pair
fetched from memory.
Contd.,
Accumulator (AC) , Multiplier Quotient (MQ)
temporarily hold operands and the results of
ALU operations
Example:
40 bit multiply operation
Most Significant Bit - AC
Least Significant Bit - MQ
CONTD.,

 IAS – Instruction Cycle

 Subcycles
 Fetch cycle
 Execute cycle
 Fetch cycle
i) Opcode of next instruction is loaded in IR
ii) Address portion is loaded in MAR
iii) Instruction taken from IBR or can be obtained from
memory (MBR)
Contd.,
 Execute cycle
1. Once the opcode is in IR the execute cycle is performed
2. Control circuitry interprets the opcode and executes
instruction by sending out control signals, which allows Data
movement or operation to be performed by ALU.
LOAD M(X),500

ADD M(X),501

=1

LOAD M(X),500
ADD M(X),501

=1

=1

EXAMPLE
 MBR=3 =3

500
500

EXAMPLE
 MBR =4

4
PC=2
ADD M(X) 501

501

EXAMPLE
STOR M(X),500 Other Ins

STOR M(X) 500, (Other Ins)

MAR = 2
2

EXAMPLE
MAR =500
500

EXAMPLE
 IAS Instruction Set
 Data Transfer – moves the data between Memory and ALU
registers or between two ALU registers
 Unconditional Branch – CU executes instructions in
sequence from memory, sequence can be changed by branch
instructions (repetitive operations)
 Conditional Branch – branch can be made dependent on
condition.
 Arithmetic – operations performed by ALU
 Address modify – permits the address to be computed in the
ALU and then inserted into instructions stored in memory.
Harvard Architecture
 Finished at Harvard University in 1947.
 It wasn't so modern as the computer from von

Neumann team. But it introduced a slightly different

architecture.
 Memory for data was separated from the memory for

instruction. This concept is known as the Harvard

architecture.
Diagrammatic view of Harvard
Architecture
Advantages of Harvard
 since it has two memories , this allows parallel access
to data and instructions.
 Development of the Control Unit is expensive and

needs more time

 Data and instructions are accessed the same way.
 Both memories can use different cell sizes.
Disadvantages of Harvard
 Free data memory cant be used for instruction and vice-
versa.
 Production of a computer with two buses is more

expensive and needs more time.

RISC and CISC
Architectures
RISC (Reduced Instruction Set
Computer)
 A Reduced Instruction Set Computer is a type of
microprocessor architecture that utilizes a small, highly-
optimized set of instructions rather than the highly-
specialized set of instructions typically found in other
architectures.
 Examples of RISC processors: IBM RS6000, MC88100;
DEC’s Alpha 21064, 21164 and 21264 processors
 It is a highly customized set of instructions used in
portable devices due to system reliability such as Apple
iPod, mobiles/smartphones, Nintendo DS
RISC Features
 RISC processors use a small and limited

number of instructions.

 RISC machines mostly uses hardwired

control unit.

 RISC processors consume less power and are

having high performance.

 Each instruction is very simple and

consistent.

 RISC processors uses simple addressing

modes.

 RISC instruction is of uniform fixed length.

CISC (Complex Instruction Set
Computer)
 A complex instruction set computer (CISC) is a computer
architecture in which single instructions can execute several low-
level operations (such as a load from memory, an arithmetic
operation, and a memory store) or are capable of multi-step
operations or addressing modes within single instructions.
 Examples of CISC processors are: Intel 386, 486, Pentium,
Pentium Pro, Pentium II, Pentium III ; Motorola’s 68000, 68020,
68040, etc.
 It has a large collection of complex instructions that range from
simple to very complex and specialized in the assembly language
level, which takes a long time to execute the instructions.
CISC Feature
 CISC chips have a large amount of
different and complex instructions.
 CISC machines generally make use of
complex addressing modes.
 Different machine programs can be
executed on CISC machine.
 CISC machines uses micro-program
control unit.
 CISC processors are having limited
number of registers.
CISC Multiplication

MULT 1:2,2:1
CISC vs RISC
 CISC uses a large set of complex machine language
instructions, while RISC uses a reduced set of simpler
instructions
 The primary difference between RISC and CISC architecture is
that RISC-based machines execute one instruction per
clock cycle. In a CISC processor, each instruction performs so
many actions that it takes several clock cycles to complete.